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PSP-03.00.00.03
[linux-ginger.git] / drivers / net / davinci_emac.c
blob4f2a1eb4cfc4ce3ee4ca5ff0bb787ec51427aee8
1 /*
2 * DaVinci Ethernet Medium Access Controller
3 *
4 * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine
5 *
6 * Copyright (C) 2009 Texas Instruments.
7 *
8 * ---------------------------------------------------------------------------
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * ---------------------------------------------------------------------------
24 * History:
25 * 0-5 A number of folks worked on this driver in bits and pieces but the major
26 * contribution came from Suraj Iyer and Anant Gole
27 * 6.0 Anant Gole - rewrote the driver as per Linux conventions
28 * 6.1 Chaithrika U S - added support for Gigabit and RMII features,
29 * PHY layer usage
30 */
31
32 /** Pending Items in this driver:
33 * 1. Use Linux cache infrastcture for DMA'ed memory (dma_xxx functions)
34 */
35
36 #include <linux/module.h>
37 #include <linux/kernel.h>
38 #include <linux/sched.h>
39 #include <linux/string.h>
40 #include <linux/timer.h>
41 #include <linux/errno.h>
42 #include <linux/in.h>
43 #include <linux/ioport.h>
44 #include <linux/slab.h>
45 #include <linux/mm.h>
46 #include <linux/interrupt.h>
47 #include <linux/init.h>
48 #include <linux/netdevice.h>
49 #include <linux/etherdevice.h>
50 #include <linux/skbuff.h>
51 #include <linux/ethtool.h>
52 #include <linux/highmem.h>
53 #include <linux/proc_fs.h>
54 #include <linux/ctype.h>
55 #include <linux/version.h>
56 #include <linux/spinlock.h>
57 #include <linux/dma-mapping.h>
58 #include <linux/clk.h>
59 #include <linux/platform_device.h>
60 #include <linux/semaphore.h>
61 #include <linux/phy.h>
62 #include <linux/bitops.h>
63 #include <linux/io.h>
64 #include <linux/uaccess.h>
65 #include <linux/davinci_emac.h>
66
67 #include <asm/irq.h>
68 #include <asm/page.h>
69
70 static int debug_level;
71 module_param(debug_level, int, 0);
72 MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)");
73
74 /* Netif debug messages possible */
75 #define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV | \
76 NETIF_MSG_PROBE | \
77 NETIF_MSG_LINK | \
78 NETIF_MSG_TIMER | \
79 NETIF_MSG_IFDOWN | \
80 NETIF_MSG_IFUP | \
81 NETIF_MSG_RX_ERR | \
82 NETIF_MSG_TX_ERR | \
83 NETIF_MSG_TX_QUEUED | \
84 NETIF_MSG_INTR | \
85 NETIF_MSG_TX_DONE | \
86 NETIF_MSG_RX_STATUS | \
87 NETIF_MSG_PKTDATA | \
88 NETIF_MSG_HW | \
89 NETIF_MSG_WOL)
90
91 /* version info */
92 #define EMAC_MAJOR_VERSION 6
93 #define EMAC_MINOR_VERSION 1
94 #define EMAC_MODULE_VERSION "6.1"
95 MODULE_VERSION(EMAC_MODULE_VERSION);
96 static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
97
98 /* Configuration items */
99 #define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC upto frames */
100 #define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */
101 #define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */
102 #define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */
103 #define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */
104 #define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */
105 #define EMAC_DEF_PROM_EN (0) /* Promiscous disabled */
106 #define EMAC_DEF_PROM_CH (0) /* Promiscous channel is 0 */
107 #define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */
108 #define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */
109 #define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */
110 #define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */
111
112 #define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */
113 #define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/
114
115 #define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */
116 #define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */
117 #define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4)
118 #define EMAC_DEF_TX_CH (0) /* Default 0th channel */
119 #define EMAC_DEF_RX_CH (0) /* Default 0th channel */
120 #define EMAC_DEF_MDIO_TICK_MS (10) /* typically 1 tick=1 ms) */
121 #define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */
122 #define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */
123 #define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */
124
125 /* Buffer descriptor parameters */
126 #define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */
127 #define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */
128
129 /* EMAC register related defines */
130 #define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF)
131 #define EMAC_NUM_MULTICAST_BITS (64)
132 #define EMAC_TEARDOWN_VALUE (0xFFFFFFFC)
133 #define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1)
134 #define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1)
135 #define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2)
136 #define EMAC_RX_UNICAST_CLEAR_ALL (0xFF)
137 #define EMAC_INT_MASK_CLEAR (0xFF)
138
139 /* RX MBP register bit positions */
140 #define EMAC_RXMBP_PASSCRC_MASK BIT(30)
141 #define EMAC_RXMBP_QOSEN_MASK BIT(29)
142 #define EMAC_RXMBP_NOCHAIN_MASK BIT(28)
143 #define EMAC_RXMBP_CMFEN_MASK BIT(24)
144 #define EMAC_RXMBP_CSFEN_MASK BIT(23)
145 #define EMAC_RXMBP_CEFEN_MASK BIT(22)
146 #define EMAC_RXMBP_CAFEN_MASK BIT(21)
147 #define EMAC_RXMBP_PROMCH_SHIFT (16)
148 #define EMAC_RXMBP_PROMCH_MASK (0x7 << 16)
149 #define EMAC_RXMBP_BROADEN_MASK BIT(13)
150 #define EMAC_RXMBP_BROADCH_SHIFT (8)
151 #define EMAC_RXMBP_BROADCH_MASK (0x7 << 8)
152 #define EMAC_RXMBP_MULTIEN_MASK BIT(5)
153 #define EMAC_RXMBP_MULTICH_SHIFT (0)
154 #define EMAC_RXMBP_MULTICH_MASK (0x7)
155 #define EMAC_RXMBP_CHMASK (0x7)
156
157 /* EMAC register definitions/bit maps used */
158 # define EMAC_MBP_RXPROMISC (0x00200000)
159 # define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16)
160 # define EMAC_MBP_RXBCAST (0x00002000)
161 # define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8)
162 # define EMAC_MBP_RXMCAST (0x00000020)
163 # define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7)
164
165 /* EMAC mac_control register */
166 #define EMAC_MACCONTROL_TXPTYPE BIT(9)
167 #define EMAC_MACCONTROL_TXPACEEN BIT(6)
168 #define EMAC_MACCONTROL_GMIIEN BIT(5)
169 #define EMAC_MACCONTROL_GIGABITEN BIT(7)
170 #define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0)
171 #define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15)
172
173 /* GIGABIT MODE related bits */
174 #define EMAC_DM646X_MACCONTORL_GIG BIT(7)
175 #define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17)
176
177 /* EMAC mac_status register */
178 #define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000)
179 #define EMAC_MACSTATUS_TXERRCODE_SHIFT (20)
180 #define EMAC_MACSTATUS_TXERRCH_MASK (0x7)
181 #define EMAC_MACSTATUS_TXERRCH_SHIFT (16)
182 #define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000)
183 #define EMAC_MACSTATUS_RXERRCODE_SHIFT (12)
184 #define EMAC_MACSTATUS_RXERRCH_MASK (0x7)
185 #define EMAC_MACSTATUS_RXERRCH_SHIFT (8)
186
187 /* EMAC RX register masks */
188 #define EMAC_RX_MAX_LEN_MASK (0xFFFF)
189 #define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF)
190
191 /* MAC_IN_VECTOR (0x180) register bit fields */
192 #define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17)
193 #define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16)
194 #define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8)
195 #define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0)
196
197 /** NOTE:: For DM646x the IN_VECTOR has changed */
198 #define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH)
199 #define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH)
200 #define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26)
201 #define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27)
202
203 /* CPPI bit positions */
204 #define EMAC_CPPI_SOP_BIT BIT(31)
205 #define EMAC_CPPI_EOP_BIT BIT(30)
206 #define EMAC_CPPI_OWNERSHIP_BIT BIT(29)
207 #define EMAC_CPPI_EOQ_BIT BIT(28)
208 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27)
209 #define EMAC_CPPI_PASS_CRC_BIT BIT(26)
210 #define EMAC_RX_BD_BUF_SIZE (0xFFFF)
211 #define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */
212 #define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF)
213
214 /* Max hardware defines */
215 #define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */
216 #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */
217
218 /* EMAC Peripheral Device Register Memory Layout structure */
219 #define EMAC_TXIDVER 0x0
220 #define EMAC_TXCONTROL 0x4
221 #define EMAC_TXTEARDOWN 0x8
222 #define EMAC_RXIDVER 0x10
223 #define EMAC_RXCONTROL 0x14
224 #define EMAC_RXTEARDOWN 0x18
225 #define EMAC_TXINTSTATRAW 0x80
226 #define EMAC_TXINTSTATMASKED 0x84
227 #define EMAC_TXINTMASKSET 0x88
228 #define EMAC_TXINTMASKCLEAR 0x8C
229 #define EMAC_MACINVECTOR 0x90
230
231 #define EMAC_DM646X_MACEOIVECTOR 0x94
232
233 #define EMAC_RXINTSTATRAW 0xA0
234 #define EMAC_RXINTSTATMASKED 0xA4
235 #define EMAC_RXINTMASKSET 0xA8
236 #define EMAC_RXINTMASKCLEAR 0xAC
237 #define EMAC_MACINTSTATRAW 0xB0
238 #define EMAC_MACINTSTATMASKED 0xB4
239 #define EMAC_MACINTMASKSET 0xB8
240 #define EMAC_MACINTMASKCLEAR 0xBC
241
242 #define EMAC_RXMBPENABLE 0x100
243 #define EMAC_RXUNICASTSET 0x104
244 #define EMAC_RXUNICASTCLEAR 0x108
245 #define EMAC_RXMAXLEN 0x10C
246 #define EMAC_RXBUFFEROFFSET 0x110
247 #define EMAC_RXFILTERLOWTHRESH 0x114
248
249 #define EMAC_MACCONTROL 0x160
250 #define EMAC_MACSTATUS 0x164
251 #define EMAC_EMCONTROL 0x168
252 #define EMAC_FIFOCONTROL 0x16C
253 #define EMAC_MACCONFIG 0x170
254 #define EMAC_SOFTRESET 0x174
255 #define EMAC_MACSRCADDRLO 0x1D0
256 #define EMAC_MACSRCADDRHI 0x1D4
257 #define EMAC_MACHASH1 0x1D8
258 #define EMAC_MACHASH2 0x1DC
259 #define EMAC_MACADDRLO 0x500
260 #define EMAC_MACADDRHI 0x504
261 #define EMAC_MACINDEX 0x508
262
263 /* EMAC HDP and Completion registors */
264 #define EMAC_TXHDP(ch) (0x600 + (ch * 4))
265 #define EMAC_RXHDP(ch) (0x620 + (ch * 4))
266 #define EMAC_TXCP(ch) (0x640 + (ch * 4))
267 #define EMAC_RXCP(ch) (0x660 + (ch * 4))
268
269 /* EMAC statistics registers */
270 #define EMAC_RXGOODFRAMES 0x200
271 #define EMAC_RXBCASTFRAMES 0x204
272 #define EMAC_RXMCASTFRAMES 0x208
273 #define EMAC_RXPAUSEFRAMES 0x20C
274 #define EMAC_RXCRCERRORS 0x210
275 #define EMAC_RXALIGNCODEERRORS 0x214
276 #define EMAC_RXOVERSIZED 0x218
277 #define EMAC_RXJABBER 0x21C
278 #define EMAC_RXUNDERSIZED 0x220
279 #define EMAC_RXFRAGMENTS 0x224
280 #define EMAC_RXFILTERED 0x228
281 #define EMAC_RXQOSFILTERED 0x22C
282 #define EMAC_RXOCTETS 0x230
283 #define EMAC_TXGOODFRAMES 0x234
284 #define EMAC_TXBCASTFRAMES 0x238
285 #define EMAC_TXMCASTFRAMES 0x23C
286 #define EMAC_TXPAUSEFRAMES 0x240
287 #define EMAC_TXDEFERRED 0x244
288 #define EMAC_TXCOLLISION 0x248
289 #define EMAC_TXSINGLECOLL 0x24C
290 #define EMAC_TXMULTICOLL 0x250
291 #define EMAC_TXEXCESSIVECOLL 0x254
292 #define EMAC_TXLATECOLL 0x258
293 #define EMAC_TXUNDERRUN 0x25C
294 #define EMAC_TXCARRIERSENSE 0x260
295 #define EMAC_TXOCTETS 0x264
296 #define EMAC_NETOCTETS 0x280
297 #define EMAC_RXSOFOVERRUNS 0x284
298 #define EMAC_RXMOFOVERRUNS 0x288
299 #define EMAC_RXDMAOVERRUNS 0x28C
300
301 /* EMAC DM644x control registers */
302 #define EMAC_CTRL_EWCTL (0x4)
303 #define EMAC_CTRL_EWINTTCNT (0x8)
304
305 /* EMAC MDIO related */
306 /* Mask & Control defines */
307 #define MDIO_CONTROL_CLKDIV (0xFF)
308 #define MDIO_CONTROL_ENABLE BIT(30)
309 #define MDIO_USERACCESS_GO BIT(31)
310 #define MDIO_USERACCESS_WRITE BIT(30)
311 #define MDIO_USERACCESS_READ (0)
312 #define MDIO_USERACCESS_REGADR (0x1F << 21)
313 #define MDIO_USERACCESS_PHYADR (0x1F << 16)
314 #define MDIO_USERACCESS_DATA (0xFFFF)
315 #define MDIO_USERPHYSEL_LINKSEL BIT(7)
316 #define MDIO_VER_MODID (0xFFFF << 16)
317 #define MDIO_VER_REVMAJ (0xFF << 8)
318 #define MDIO_VER_REVMIN (0xFF)
319
320 #define MDIO_USERACCESS(inst) (0x80 + (inst * 8))
321 #define MDIO_USERPHYSEL(inst) (0x84 + (inst * 8))
322 #define MDIO_CONTROL (0x04)
323
324 /* EMAC DM646X control module registers */
325 #define EMAC_DM646X_CMRXINTEN (0x14)
326 #define EMAC_DM646X_CMTXINTEN (0x18)
327
328 /* EMAC EOI codes for C0 */
329 #define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01)
330 #define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02)
331
332 /* EMAC Stats Clear Mask */
333 #define EMAC_STATS_CLR_MASK (0xFFFFFFFF)
334
335 /** net_buf_obj: EMAC network bufferdata structure
336 *
337 * EMAC network buffer data structure
338 */
339 struct emac_netbufobj {
340 void *buf_token;
341 char *data_ptr;
342 int length;
343 };
344
345 /** net_pkt_obj: EMAC network packet data structure
346 *
347 * EMAC network packet data structure - supports buffer list (for future)
348 */
349 struct emac_netpktobj {
350 void *pkt_token; /* data token may hold tx/rx chan id */
351 struct emac_netbufobj *buf_list; /* array of network buffer objects */
352 int num_bufs;
353 int pkt_length;
354 };
355
356 /** emac_tx_bd: EMAC TX Buffer descriptor data structure
357 *
358 * EMAC TX Buffer descriptor data structure
359 */
360 struct emac_tx_bd {
361 int h_next;
362 int buff_ptr;
363 int off_b_len;
364 int mode; /* SOP, EOP, ownership, EOQ, teardown,Qstarv, length */
365 struct emac_tx_bd __iomem *next;
366 void *buf_token;
367 };
368
369 /** emac_txch: EMAC TX Channel data structure
370 *
371 * EMAC TX Channel data structure
372 */
373 struct emac_txch {
374 /* Config related */
375 u32 num_bd;
376 u32 service_max;
377
378 /* CPPI specific */
379 u32 alloc_size;
380 void __iomem *bd_mem;
381 struct emac_tx_bd __iomem *bd_pool_head;
382 struct emac_tx_bd __iomem *active_queue_head;
383 struct emac_tx_bd __iomem *active_queue_tail;
384 struct emac_tx_bd __iomem *last_hw_bdprocessed;
385 u32 queue_active;
386 u32 teardown_pending;
387 u32 *tx_complete;
388
389 /** statistics */
390 u32 proc_count; /* TX: # of times emac_tx_bdproc is called */
391 u32 mis_queued_packets;
392 u32 queue_reinit;
393 u32 end_of_queue_add;
394 u32 out_of_tx_bd;
395 u32 no_active_pkts; /* IRQ when there were no packets to process */
396 u32 active_queue_count;
397 };
398
399 /** emac_rx_bd: EMAC RX Buffer descriptor data structure
400 *
401 * EMAC RX Buffer descriptor data structure
402 */
403 struct emac_rx_bd {
404 int h_next;
405 int buff_ptr;
406 int off_b_len;
407 int mode;
408 struct emac_rx_bd __iomem *next;
409 void *data_ptr;
410 void *buf_token;
411 };
412
413 /** emac_rxch: EMAC RX Channel data structure
414 *
415 * EMAC RX Channel data structure
416 */
417 struct emac_rxch {
418 /* configuration info */
419 u32 num_bd;
420 u32 service_max;
421 u32 buf_size;
422 char mac_addr[6];
423
424 /** CPPI specific */
425 u32 alloc_size;
426 void __iomem *bd_mem;
427 struct emac_rx_bd __iomem *bd_pool_head;
428 struct emac_rx_bd __iomem *active_queue_head;
429 struct emac_rx_bd __iomem *active_queue_tail;
430 u32 queue_active;
431 u32 teardown_pending;
432
433 /* packet and buffer objects */
434 struct emac_netpktobj pkt_queue;
435 struct emac_netbufobj buf_queue;
436
437 /** statistics */
438 u32 proc_count; /* number of times emac_rx_bdproc is called */
439 u32 processed_bd;
440 u32 recycled_bd;
441 u32 out_of_rx_bd;
442 u32 out_of_rx_buffers;
443 u32 queue_reinit;
444 u32 end_of_queue_add;
445 u32 end_of_queue;
446 u32 mis_queued_packets;
447 };
448
449 /* emac_priv: EMAC private data structure
450 *
451 * EMAC adapter private data structure
452 */
453 struct emac_priv {
454 u32 msg_enable;
455 struct net_device *ndev;
456 struct platform_device *pdev;
457 struct napi_struct napi;
458 char mac_addr[6];
459 spinlock_t tx_lock;
460 spinlock_t rx_lock;
461 void __iomem *remap_addr;
462 u32 emac_base_phys;
463 void __iomem *emac_base;
464 void __iomem *ctrl_base;
465 void __iomem *emac_ctrl_ram;
466 u32 ctrl_ram_size;
467 u32 hw_ram_addr;
468 struct emac_txch *txch[EMAC_DEF_MAX_TX_CH];
469 struct emac_rxch *rxch[EMAC_DEF_MAX_RX_CH];
470 u32 link; /* 1=link on, 0=link off */
471 u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
472 u32 duplex; /* Link duplex: 0=Half, 1=Full */
473 u32 rx_buf_size;
474 u32 isr_count;
475 u8 rmii_en;
476 u8 version;
477 struct net_device_stats net_dev_stats;
478 u32 mac_hash1;
479 u32 mac_hash2;
480 u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS];
481 u32 rx_addr_type;
482 /* periodic timer required for MDIO polling */
483 struct timer_list periodic_timer;
484 u32 periodic_ticks;
485 u32 timer_active;
486 u32 phy_mask;
487 /* mii_bus,phy members */
488 struct mii_bus *mii_bus;
489 struct phy_device *phydev;
490 spinlock_t lock;
491 /*platform specific members*/
492 void (*wrapper_int_enable) (void);
493 void (*wrapper_int_disable) (void);
494 };
495
496 /* clock frequency for EMAC */
497 static struct clk *emac_clk = NULL;
498 static struct clk *emac_phy_clk = NULL;
499 static unsigned long emac_bus_frequency;
500 static unsigned long mdio_max_freq;
501
502 #define emac_virt_to_phys(addr, priv) \
503 (((u32 __force)(addr) - (u32 __force)(priv->emac_ctrl_ram)) \
504 + priv->hw_ram_addr)
505
506 /* Cache macros - Packet buffers would be from skb pool which is cached */
507 #define EMAC_VIRT_NOCACHE(addr) (addr)
508 #define EMAC_CACHE_INVALIDATE(addr, size) \
509 dma_cache_maint((void *)addr, size, DMA_FROM_DEVICE)
510 #define EMAC_CACHE_WRITEBACK(addr, size) \
511 dma_cache_maint((void *)addr, size, DMA_TO_DEVICE)
512 #define EMAC_CACHE_WRITEBACK_INVALIDATE(addr, size) \
513 dma_cache_maint((void *)addr, size, DMA_BIDIRECTIONAL)
514
515 /* DM644x does not have BD's in cached memory - so no cache functions */
516 #define BD_CACHE_INVALIDATE(addr, size)
517 #define BD_CACHE_WRITEBACK(addr, size)
518 #define BD_CACHE_WRITEBACK_INVALIDATE(addr, size)
519
520 /* EMAC TX Host Error description strings */
521 static char *emac_txhost_errcodes[16] = {
522 "No error", "SOP error", "Ownership bit not set in SOP buffer",
523 "Zero Next Buffer Descriptor Pointer Without EOP",
524 "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error",
525 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
526 "Reserved", "Reserved", "Reserved", "Reserved"
527 };
528
529 /* EMAC RX Host Error description strings */
530 static char *emac_rxhost_errcodes[16] = {
531 "No error", "Reserved", "Ownership bit not set in input buffer",
532 "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved",
533 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
534 "Reserved", "Reserved", "Reserved", "Reserved"
535 };
536
537 /* Helper macros */
538 #define emac_read(reg) ioread32(priv->emac_base + (reg))
539 #define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg))
540
541 #define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg)))
542 #define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg)))
543
544 #define emac_mdio_read(reg) ioread32(bus->priv + (reg))
545 #define emac_mdio_write(reg, val) iowrite32(val, (bus->priv + (reg)))
546
547 /**
548 * emac_dump_regs: Dump important EMAC registers to debug terminal
549 * @priv: The DaVinci EMAC private adapter structure
550 *
551 * Executes ethtool set cmd & sets phy mode
552 *
553 */
554 static void emac_dump_regs(struct emac_priv *priv)
555 {
556 struct device *emac_dev = &priv->ndev->dev;
557
558 /* Print important registers in EMAC */
559 dev_info(emac_dev, "EMAC Basic registers\n");
560 dev_info(emac_dev, "EMAC: EWCTL: %08X, EWINTTCNT: %08X\n",
561 emac_ctrl_read(EMAC_CTRL_EWCTL),
562 emac_ctrl_read(EMAC_CTRL_EWINTTCNT));
563 dev_info(emac_dev, "EMAC: TXID: %08X %s, RXID: %08X %s\n",
564 emac_read(EMAC_TXIDVER),
565 ((emac_read(EMAC_TXCONTROL)) ? "enabled" : "disabled"),
566 emac_read(EMAC_RXIDVER),
567 ((emac_read(EMAC_RXCONTROL)) ? "enabled" : "disabled"));
568 dev_info(emac_dev, "EMAC: TXIntRaw:%08X, TxIntMasked: %08X, "\
569 "TxIntMasSet: %08X\n", emac_read(EMAC_TXINTSTATRAW),
570 emac_read(EMAC_TXINTSTATMASKED), emac_read(EMAC_TXINTMASKSET));
571 dev_info(emac_dev, "EMAC: RXIntRaw:%08X, RxIntMasked: %08X, "\
572 "RxIntMasSet: %08X\n", emac_read(EMAC_RXINTSTATRAW),
573 emac_read(EMAC_RXINTSTATMASKED), emac_read(EMAC_RXINTMASKSET));
574 dev_info(emac_dev, "EMAC: MacIntRaw:%08X, MacIntMasked: %08X, "\
575 "MacInVector=%08X\n", emac_read(EMAC_MACINTSTATRAW),
576 emac_read(EMAC_MACINTSTATMASKED), emac_read(EMAC_MACINVECTOR));
577 dev_info(emac_dev, "EMAC: EmuControl:%08X, FifoControl: %08X\n",
578 emac_read(EMAC_EMCONTROL), emac_read(EMAC_FIFOCONTROL));
579 dev_info(emac_dev, "EMAC: MBPEnable:%08X, RXUnicastSet: %08X, "\
580 "RXMaxLen=%08X\n", emac_read(EMAC_RXMBPENABLE),
581 emac_read(EMAC_RXUNICASTSET), emac_read(EMAC_RXMAXLEN));
582 dev_info(emac_dev, "EMAC: MacControl:%08X, MacStatus: %08X, "\
583 "MacConfig=%08X\n", emac_read(EMAC_MACCONTROL),
584 emac_read(EMAC_MACSTATUS), emac_read(EMAC_MACCONFIG));
585 dev_info(emac_dev, "EMAC: TXHDP[0]:%08X, RXHDP[0]: %08X\n",
586 emac_read(EMAC_TXHDP(0)), emac_read(EMAC_RXHDP(0)));
587 dev_info(emac_dev, "EMAC Statistics\n");
588 dev_info(emac_dev, "EMAC: rx_good_frames:%d\n",
589 emac_read(EMAC_RXGOODFRAMES));
590 dev_info(emac_dev, "EMAC: rx_broadcast_frames:%d\n",
591 emac_read(EMAC_RXBCASTFRAMES));
592 dev_info(emac_dev, "EMAC: rx_multicast_frames:%d\n",
593 emac_read(EMAC_RXMCASTFRAMES));
594 dev_info(emac_dev, "EMAC: rx_pause_frames:%d\n",
595 emac_read(EMAC_RXPAUSEFRAMES));
596 dev_info(emac_dev, "EMAC: rx_crcerrors:%d\n",
597 emac_read(EMAC_RXCRCERRORS));
598 dev_info(emac_dev, "EMAC: rx_align_code_errors:%d\n",
599 emac_read(EMAC_RXALIGNCODEERRORS));
600 dev_info(emac_dev, "EMAC: rx_oversized_frames:%d\n",
601 emac_read(EMAC_RXOVERSIZED));
602 dev_info(emac_dev, "EMAC: rx_jabber_frames:%d\n",
603 emac_read(EMAC_RXJABBER));
604 dev_info(emac_dev, "EMAC: rx_undersized_frames:%d\n",
605 emac_read(EMAC_RXUNDERSIZED));
606 dev_info(emac_dev, "EMAC: rx_fragments:%d\n",
607 emac_read(EMAC_RXFRAGMENTS));
608 dev_info(emac_dev, "EMAC: rx_filtered_frames:%d\n",
609 emac_read(EMAC_RXFILTERED));
610 dev_info(emac_dev, "EMAC: rx_qos_filtered_frames:%d\n",
611 emac_read(EMAC_RXQOSFILTERED));
612 dev_info(emac_dev, "EMAC: rx_octets:%d\n",
613 emac_read(EMAC_RXOCTETS));
614 dev_info(emac_dev, "EMAC: tx_goodframes:%d\n",
615 emac_read(EMAC_TXGOODFRAMES));
616 dev_info(emac_dev, "EMAC: tx_bcastframes:%d\n",
617 emac_read(EMAC_TXBCASTFRAMES));
618 dev_info(emac_dev, "EMAC: tx_mcastframes:%d\n",
619 emac_read(EMAC_TXMCASTFRAMES));
620 dev_info(emac_dev, "EMAC: tx_pause_frames:%d\n",
621 emac_read(EMAC_TXPAUSEFRAMES));
622 dev_info(emac_dev, "EMAC: tx_deferred_frames:%d\n",
623 emac_read(EMAC_TXDEFERRED));
624 dev_info(emac_dev, "EMAC: tx_collision_frames:%d\n",
625 emac_read(EMAC_TXCOLLISION));
626 dev_info(emac_dev, "EMAC: tx_single_coll_frames:%d\n",
627 emac_read(EMAC_TXSINGLECOLL));
628 dev_info(emac_dev, "EMAC: tx_mult_coll_frames:%d\n",
629 emac_read(EMAC_TXMULTICOLL));
630 dev_info(emac_dev, "EMAC: tx_excessive_collisions:%d\n",
631 emac_read(EMAC_TXEXCESSIVECOLL));
632 dev_info(emac_dev, "EMAC: tx_late_collisions:%d\n",
633 emac_read(EMAC_TXLATECOLL));
634 dev_info(emac_dev, "EMAC: tx_underrun:%d\n",
635 emac_read(EMAC_TXUNDERRUN));
636 dev_info(emac_dev, "EMAC: tx_carrier_sense_errors:%d\n",
637 emac_read(EMAC_TXCARRIERSENSE));
638 dev_info(emac_dev, "EMAC: tx_octets:%d\n",
639 emac_read(EMAC_TXOCTETS));
640 dev_info(emac_dev, "EMAC: net_octets:%d\n",
641 emac_read(EMAC_NETOCTETS));
642 dev_info(emac_dev, "EMAC: rx_sof_overruns:%d\n",
643 emac_read(EMAC_RXSOFOVERRUNS));
644 dev_info(emac_dev, "EMAC: rx_mof_overruns:%d\n",
645 emac_read(EMAC_RXMOFOVERRUNS));
646 dev_info(emac_dev, "EMAC: rx_dma_overruns:%d\n",
647 emac_read(EMAC_RXDMAOVERRUNS));
648 }
649
650 /*************************************************************************
651 * EMAC MDIO/Phy Functionality
652 *************************************************************************/
653 /**
654 * emac_get_drvinfo: Get EMAC driver information
655 * @ndev: The DaVinci EMAC network adapter
656 * @info: ethtool info structure containing name and version
657 *
658 * Returns EMAC driver information (name and version)
659 *
660 */
661 static void emac_get_drvinfo(struct net_device *ndev,
662 struct ethtool_drvinfo *info)
663 {
664 strcpy(info->driver, emac_version_string);
665 strcpy(info->version, EMAC_MODULE_VERSION);
666 }
667
668 /**
669 * emac_get_settings: Get EMAC settings
670 * @ndev: The DaVinci EMAC network adapter
671 * @ecmd: ethtool command
672 *
673 * Executes ethool get command
674 *
675 */
676 static int emac_get_settings(struct net_device *ndev,
677 struct ethtool_cmd *ecmd)
678 {
679 struct emac_priv *priv = netdev_priv(ndev);
680 if (priv->phy_mask)
681 return phy_ethtool_gset(priv->phydev, ecmd);
682 else
683 return -EOPNOTSUPP;
684
685 }
686
687 /**
688 * emac_set_settings: Set EMAC settings
689 * @ndev: The DaVinci EMAC network adapter
690 * @ecmd: ethtool command
691 *
692 * Executes ethool set command
693 *
694 */
695 static int emac_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
696 {
697 struct emac_priv *priv = netdev_priv(ndev);
698 if (priv->phy_mask)
699 return phy_ethtool_sset(priv->phydev, ecmd);
700 else
701 return -EOPNOTSUPP;
702
703 }
704
705 /**
706 * ethtool_ops: DaVinci EMAC Ethtool structure
707 *
708 * Ethtool support for EMAC adapter
709 *
710 */
711 static const struct ethtool_ops ethtool_ops = {
712 .get_drvinfo = emac_get_drvinfo,
713 .get_settings = emac_get_settings,
714 .set_settings = emac_set_settings,
715 .get_link = ethtool_op_get_link,
716 };
717
718 /**
719 * emac_update_phystatus: Update Phy status
720 * @priv: The DaVinci EMAC private adapter structure
721 *
722 * Updates phy status and takes action for network queue if required
723 * based upon link status
724 *
725 */
726 static void emac_update_phystatus(struct emac_priv *priv)
727 {
728 u32 mac_control;
729 u32 new_duplex;
730 u32 cur_duplex;
731 struct net_device *ndev = priv->ndev;
732
733 mac_control = emac_read(EMAC_MACCONTROL);
734 cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ?
735 DUPLEX_FULL : DUPLEX_HALF;
736 if (priv->phy_mask)
737 new_duplex = priv->phydev->duplex;
738 else
739 new_duplex = DUPLEX_FULL;
740
741 /* We get called only if link has changed (speed/duplex/status) */
742 if ((priv->link) && (new_duplex != cur_duplex)) {
743 priv->duplex = new_duplex;
744 if (DUPLEX_FULL == priv->duplex)
745 mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN);
746 else
747 mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN);
748 }
749
750 if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) {
751 mac_control = emac_read(EMAC_MACCONTROL);
752 mac_control |= (EMAC_DM646X_MACCONTORL_GIG |
753 EMAC_DM646X_MACCONTORL_GIGFORCE);
754 } else {
755 /* Clear the GIG bit and GIGFORCE bit */
756 mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE |
757 EMAC_DM646X_MACCONTORL_GIG);
758
759 if (priv->rmii_en && (priv->speed == SPEED_100))
760 mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK;
761 else
762 mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK;
763 }
764
765 /* Update mac_control if changed */
766 emac_write(EMAC_MACCONTROL, mac_control);
767
768 if (priv->link) {
769 /* link ON */
770 if (!netif_carrier_ok(ndev))
771 netif_carrier_on(ndev);
772 /* reactivate the transmit queue if it is stopped */
773 if (netif_running(ndev) && netif_queue_stopped(ndev))
774 netif_wake_queue(ndev);
775 } else {
776 /* link OFF */
777 if (netif_carrier_ok(ndev))
778 netif_carrier_off(ndev);
779 if (!netif_queue_stopped(ndev))
780 netif_stop_queue(ndev);
781 }
782 }
783
784 /**
785 * hash_get: Calculate hash value from mac address
786 * @addr: mac address to delete from hash table
787 *
788 * Calculates hash value from mac address
789 *
790 */
791 static u32 hash_get(u8 *addr)
792 {
793 u32 hash;
794 u8 tmpval;
795 int cnt;
796 hash = 0;
797
798 for (cnt = 0; cnt < 2; cnt++) {
799 tmpval = *addr++;
800 hash ^= (tmpval >> 2) ^ (tmpval << 4);
801 tmpval = *addr++;
802 hash ^= (tmpval >> 4) ^ (tmpval << 2);
803 tmpval = *addr++;
804 hash ^= (tmpval >> 6) ^ (tmpval);
805 }
806
807 return hash & 0x3F;
808 }
809
810 /**
811 * hash_add: Hash function to add mac addr from hash table
812 * @priv: The DaVinci EMAC private adapter structure
813 * mac_addr: mac address to delete from hash table
814 *
815 * Adds mac address to the internal hash table
816 *
817 */
818 static int hash_add(struct emac_priv *priv, u8 *mac_addr)
819 {
820 struct device *emac_dev = &priv->ndev->dev;
821 u32 rc = 0;
822 u32 hash_bit;
823 u32 hash_value = hash_get(mac_addr);
824
825 if (hash_value >= EMAC_NUM_MULTICAST_BITS) {
826 if (netif_msg_drv(priv)) {
827 dev_err(emac_dev, "DaVinci EMAC: hash_add(): Invalid "\
828 "Hash %08x, should not be greater than %08x",
829 hash_value, (EMAC_NUM_MULTICAST_BITS - 1));
830 }
831 return -1;
832 }
833
834 /* set the hash bit only if not previously set */
835 if (priv->multicast_hash_cnt[hash_value] == 0) {
836 rc = 1; /* hash value changed */
837 if (hash_value < 32) {
838 hash_bit = BIT(hash_value);
839 priv->mac_hash1 |= hash_bit;
840 } else {
841 hash_bit = BIT((hash_value - 32));
842 priv->mac_hash2 |= hash_bit;
843 }
844 }
845
846 /* incr counter for num of mcast addr's mapped to "this" hash bit */
847 ++priv->multicast_hash_cnt[hash_value];
848
849 return rc;
850 }
851
852 /**
853 * hash_del: Hash function to delete mac addr from hash table
854 * @priv: The DaVinci EMAC private adapter structure
855 * mac_addr: mac address to delete from hash table
856 *
857 * Removes mac address from the internal hash table
858 *
859 */
860 static int hash_del(struct emac_priv *priv, u8 *mac_addr)
861 {
862 u32 hash_value;
863 u32 hash_bit;
864
865 hash_value = hash_get(mac_addr);
866 if (priv->multicast_hash_cnt[hash_value] > 0) {
867 /* dec cntr for num of mcast addr's mapped to this hash bit */
868 --priv->multicast_hash_cnt[hash_value];
869 }
870
871 /* if counter still > 0, at least one multicast address refers
872 * to this hash bit. so return 0 */
873 if (priv->multicast_hash_cnt[hash_value] > 0)
874 return 0;
875
876 if (hash_value < 32) {
877 hash_bit = BIT(hash_value);
878 priv->mac_hash1 &= ~hash_bit;
879 } else {
880 hash_bit = BIT((hash_value - 32));
881 priv->mac_hash2 &= ~hash_bit;
882 }
883
884 /* return 1 to indicate change in mac_hash registers reqd */
885 return 1;
886 }
887
888 /* EMAC multicast operation */
889 #define EMAC_MULTICAST_ADD 0
890 #define EMAC_MULTICAST_DEL 1
891 #define EMAC_ALL_MULTI_SET 2
892 #define EMAC_ALL_MULTI_CLR 3
893
894 /**
895 * emac_add_mcast: Set multicast address in the EMAC adapter (Internal)
896 * @priv: The DaVinci EMAC private adapter structure
897 * @action: multicast operation to perform
898 * mac_addr: mac address to set
899 *
900 * Set multicast addresses in EMAC adapter - internal function
901 *
902 */
903 static void emac_add_mcast(struct emac_priv *priv, u32 action, u8 *mac_addr)
904 {
905 struct device *emac_dev = &priv->ndev->dev;
906 int update = -1;
907
908 switch (action) {
909 case EMAC_MULTICAST_ADD:
910 update = hash_add(priv, mac_addr);
911 break;
912 case EMAC_MULTICAST_DEL:
913 update = hash_del(priv, mac_addr);
914 break;
915 case EMAC_ALL_MULTI_SET:
916 update = 1;
917 priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE;
918 priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE;
919 break;
920 case EMAC_ALL_MULTI_CLR:
921 update = 1;
922 priv->mac_hash1 = 0;
923 priv->mac_hash2 = 0;
924 memset(&(priv->multicast_hash_cnt[0]), 0,
925 sizeof(priv->multicast_hash_cnt[0]) *
926 EMAC_NUM_MULTICAST_BITS);
927 break;
928 default:
929 if (netif_msg_drv(priv))
930 dev_err(emac_dev, "DaVinci EMAC: add_mcast"\
931 ": bad operation %d", action);
932 break;
933 }
934
935 /* write to the hardware only if the register status chances */
936 if (update > 0) {
937 emac_write(EMAC_MACHASH1, priv->mac_hash1);
938 emac_write(EMAC_MACHASH2, priv->mac_hash2);
939 }
940 }
941
942 /**
943 * emac_dev_mcast_set: Set multicast address in the EMAC adapter
944 * @ndev: The DaVinci EMAC network adapter
945 *
946 * Set multicast addresses in EMAC adapter
947 *
948 */
949 static void emac_dev_mcast_set(struct net_device *ndev)
950 {
951 u32 mbp_enable;
952 struct emac_priv *priv = netdev_priv(ndev);
953
954 mbp_enable = emac_read(EMAC_RXMBPENABLE);
955 if (ndev->flags & IFF_PROMISC) {
956 mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH));
957 mbp_enable |= (EMAC_MBP_RXPROMISC);
958 } else {
959 mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC);
960 if ((ndev->flags & IFF_ALLMULTI) ||
961 (ndev->mc_count > EMAC_DEF_MAX_MULTICAST_ADDRESSES)) {
962 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
963 emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL);
964 }
965 if (ndev->mc_count > 0) {
966 struct dev_mc_list *mc_ptr;
967 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
968 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
969 /* program multicast address list into EMAC hardware */
970 for (mc_ptr = ndev->mc_list; mc_ptr;
971 mc_ptr = mc_ptr->next) {
972 emac_add_mcast(priv, EMAC_MULTICAST_ADD,
973 (u8 *)mc_ptr->dmi_addr);
974 }
975 } else {
976 mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST);
977 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
978 }
979 }
980 /* Set mbp config register */
981 emac_write(EMAC_RXMBPENABLE, mbp_enable);
982 }
983
984 /*************************************************************************
985 * EMAC Hardware manipulation
986 *************************************************************************/
987
988 /**
989 * emac_int_disable: Disable EMAC module interrupt (from adapter)
990 * @priv: The DaVinci EMAC private adapter structure
991 *
992 * Disable EMAC interrupt on the adapter
993 *
994 */
995 static void emac_int_disable(struct emac_priv *priv)
996 {
997 if (priv->version == EMAC_VERSION_2) {
998 unsigned long flags;
999
1000 local_irq_save(flags);
1001
1002 /* Program C0_Int_En to zero to turn off
1003 * interrupts to the CPU */
1004 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0);
1005 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0);
1006 /* NOTE: Rx Threshold and Misc interrupts are not disabled */
1007 if (priv->wrapper_int_disable)
1008 priv->wrapper_int_disable();
1009
1010 local_irq_restore(flags);
1011
1012 } else {
1013 /* Set DM644x control registers for interrupt control */
1014 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0);
1015 }
1016 }
1017
1018 /**
1019 * emac_int_enable: Enable EMAC module interrupt (from adapter)
1020 * @priv: The DaVinci EMAC private adapter structure
1021 *
1022 * Enable EMAC interrupt on the adapter
1023 *
1024 */
1025 static void emac_int_enable(struct emac_priv *priv)
1026 {
1027 if (priv->version == EMAC_VERSION_2) {
1028 if (priv->wrapper_int_enable)
1029 priv->wrapper_int_enable();
1030
1031 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff);
1032 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff);
1033
1034 /* In addition to turning on interrupt Enable, we need
1035 * ack by writing appropriate values to the EOI
1036 * register */
1037
1038 /* NOTE: Rx Threshold and Misc interrupts are not enabled */
1039
1040 /* ack rxen only then a new pulse will be generated */
1041 emac_write(EMAC_DM646X_MACEOIVECTOR,
1042 EMAC_DM646X_MAC_EOI_C0_RXEN);
1043
1044 /* ack txen- only then a new pulse will be generated */
1045 emac_write(EMAC_DM646X_MACEOIVECTOR,
1046 EMAC_DM646X_MAC_EOI_C0_TXEN);
1047
1048 } else {
1049 /* Set DM644x control registers for interrupt control */
1050 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1);
1051 }
1052 }
1053
1054 /**
1055 * emac_irq: EMAC interrupt handler
1056 * @irq: interrupt number
1057 * @dev_id: EMAC network adapter data structure ptr
1058 *
1059 * EMAC Interrupt handler - we only schedule NAPI and not process any packets
1060 * here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function
1061 *
1062 * Returns interrupt handled condition
1063 */
1064 static irqreturn_t emac_irq(int irq, void *dev_id)
1065 {
1066 struct net_device *ndev = (struct net_device *)dev_id;
1067 struct emac_priv *priv = netdev_priv(ndev);
1068
1069 ++priv->isr_count;
1070 if (likely(netif_running(priv->ndev))) {
1071 emac_int_disable(priv);
1072 napi_schedule(&priv->napi);
1073 } else {
1074 /* we are closing down, so dont process anything */
1075 }
1076 return IRQ_HANDLED;
1077 }
1078
1079 /** EMAC on-chip buffer descriptor memory
1080 *
1081 * WARNING: Please note that the on chip memory is used for both TX and RX
1082 * buffer descriptor queues and is equally divided between TX and RX desc's
1083 * If the number of TX or RX descriptors change this memory pointers need
1084 * to be adjusted. If external memory is allocated then these pointers can
1085 * pointer to the memory
1086 *
1087 */
1088 #define EMAC_TX_BD_MEM(priv) ((priv)->emac_ctrl_ram)
1089 #define EMAC_RX_BD_MEM(priv) ((priv)->emac_ctrl_ram + \
1090 (((priv)->ctrl_ram_size) >> 1))
1091
1092 /**
1093 * emac_init_txch: TX channel initialization
1094 * @priv: The DaVinci EMAC private adapter structure
1095 * @ch: RX channel number
1096 *
1097 * Called during device init to setup a TX channel (allocate buffer desc
1098 * create free pool and keep ready for transmission
1099 *
1100 * Returns success(0) or mem alloc failures error code
1101 */
1102 static int emac_init_txch(struct emac_priv *priv, u32 ch)
1103 {
1104 struct device *emac_dev = &priv->ndev->dev;
1105 u32 cnt, bd_size;
1106 void __iomem *mem;
1107 struct emac_tx_bd __iomem *curr_bd;
1108 struct emac_txch *txch = NULL;
1109
1110 txch = kzalloc(sizeof(struct emac_txch), GFP_KERNEL);
1111 if (NULL == txch) {
1112 dev_err(emac_dev, "DaVinci EMAC: TX Ch mem alloc failed");
1113 return -ENOMEM;
1114 }
1115 priv->txch[ch] = txch;
1116 txch->service_max = EMAC_DEF_TX_MAX_SERVICE;
1117 txch->active_queue_head = NULL;
1118 txch->active_queue_tail = NULL;
1119 txch->queue_active = 0;
1120 txch->teardown_pending = 0;
1121
1122 /* allocate memory for TX CPPI channel on a 4 byte boundry */
1123 txch->tx_complete = kzalloc(txch->service_max * sizeof(u32),
1124 GFP_KERNEL);
1125 if (NULL == txch->tx_complete) {
1126 dev_err(emac_dev, "DaVinci EMAC: Tx service mem alloc failed");
1127 kfree(txch);
1128 return -ENOMEM;
1129 }
1130
1131 /* allocate buffer descriptor pool align every BD on four word
1132 * boundry for future requirements */
1133 bd_size = (sizeof(struct emac_tx_bd) + 0xF) & ~0xF;
1134 txch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size;
1135 txch->alloc_size = (((bd_size * txch->num_bd) + 0xF) & ~0xF);
1136
1137 /* alloc TX BD memory */
1138 txch->bd_mem = EMAC_TX_BD_MEM(priv);
1139 __memzero((void __force *)txch->bd_mem, txch->alloc_size);
1140
1141 /* initialize the BD linked list */
1142 mem = (void __force __iomem *)
1143 (((u32 __force) txch->bd_mem + 0xF) & ~0xF);
1144 txch->bd_pool_head = NULL;
1145 for (cnt = 0; cnt < txch->num_bd; cnt++) {
1146 curr_bd = mem + (cnt * bd_size);
1147 curr_bd->next = txch->bd_pool_head;
1148 txch->bd_pool_head = curr_bd;
1149 }
1150
1151 /* reset statistics counters */
1152 txch->out_of_tx_bd = 0;
1153 txch->no_active_pkts = 0;
1154 txch->active_queue_count = 0;
1155
1156 return 0;
1157 }
1158
1159 /**
1160 * emac_cleanup_txch: Book-keep function to clean TX channel resources
1161 * @priv: The DaVinci EMAC private adapter structure
1162 * @ch: TX channel number
1163 *
1164 * Called to clean up TX channel resources
1165 *
1166 */
1167 static void emac_cleanup_txch(struct emac_priv *priv, u32 ch)
1168 {
1169 struct emac_txch *txch = priv->txch[ch];
1170
1171 if (txch) {
1172 if (txch->bd_mem)
1173 txch->bd_mem = NULL;
1174 kfree(txch->tx_complete);
1175 kfree(txch);
1176 priv->txch[ch] = NULL;
1177 }
1178 }
1179
1180 /**
1181 * emac_net_tx_complete: TX packet completion function
1182 * @priv: The DaVinci EMAC private adapter structure
1183 * @net_data_tokens: packet token - skb pointer
1184 * @num_tokens: number of skb's to free
1185 * @ch: TX channel number
1186 *
1187 * Frees the skb once packet is transmitted
1188 *
1189 */
1190 static int emac_net_tx_complete(struct emac_priv *priv,
1191 void **net_data_tokens,
1192 int num_tokens, u32 ch)
1193 {
1194 u32 cnt;
1195
1196 if (unlikely(num_tokens && netif_queue_stopped(priv->ndev)))
1197 netif_start_queue(priv->ndev);
1198 for (cnt = 0; cnt < num_tokens; cnt++) {
1199 struct sk_buff *skb = (struct sk_buff *)net_data_tokens[cnt];
1200 if (skb == NULL)
1201 continue;
1202 priv->net_dev_stats.tx_packets++;
1203 priv->net_dev_stats.tx_bytes += skb->len;
1204 dev_kfree_skb_any(skb);
1205 }
1206 return 0;
1207 }
1208
1209 /**
1210 * emac_txch_teardown: TX channel teardown
1211 * @priv: The DaVinci EMAC private adapter structure
1212 * @ch: TX channel number
1213 *
1214 * Called to teardown TX channel
1215 *
1216 */
1217 static void emac_txch_teardown(struct emac_priv *priv, u32 ch)
1218 {
1219 struct device *emac_dev = &priv->ndev->dev;
1220 u32 teardown_cnt = 0xFFFFFFF0; /* Some high value */
1221 struct emac_txch *txch = priv->txch[ch];
1222 struct emac_tx_bd __iomem *curr_bd;
1223
1224 while ((emac_read(EMAC_TXCP(ch)) & EMAC_TEARDOWN_VALUE) !=
1225 EMAC_TEARDOWN_VALUE) {
1226 /* wait till tx teardown complete */
1227 cpu_relax(); /* TODO: check if this helps ... */
1228 --teardown_cnt;
1229 if (0 == teardown_cnt) {
1230 dev_err(emac_dev, "EMAC: TX teardown aborted\n");
1231 break;
1232 }
1233 }
1234 emac_write(EMAC_TXCP(ch), EMAC_TEARDOWN_VALUE);
1235
1236 /* process sent packets and return skb's to upper layer */
1237 if (1 == txch->queue_active) {
1238 curr_bd = txch->active_queue_head;
1239 while (curr_bd != NULL) {
1240 emac_net_tx_complete(priv, (void __force *)
1241 &curr_bd->buf_token, 1, ch);
1242 if (curr_bd != txch->active_queue_tail)
1243 curr_bd = curr_bd->next;
1244 else
1245 break;
1246 }
1247 txch->bd_pool_head = txch->active_queue_head;
1248 txch->active_queue_head =
1249 txch->active_queue_tail = NULL;
1250 }
1251 }
1252
1253 /**
1254 * emac_stop_txch: Stop TX channel operation
1255 * @priv: The DaVinci EMAC private adapter structure
1256 * @ch: TX channel number
1257 *
1258 * Called to stop TX channel operation
1259 *
1260 */
1261 static void emac_stop_txch(struct emac_priv *priv, u32 ch)
1262 {
1263 struct emac_txch *txch = priv->txch[ch];
1264
1265 if (txch) {
1266 txch->teardown_pending = 1;
1267 emac_write(EMAC_TXTEARDOWN, 0);
1268 emac_txch_teardown(priv, ch);
1269 txch->teardown_pending = 0;
1270 emac_write(EMAC_TXINTMASKCLEAR, BIT(ch));
1271 }
1272 }
1273
1274 /**
1275 * emac_tx_bdproc: TX buffer descriptor (packet) processing
1276 * @priv: The DaVinci EMAC private adapter structure
1277 * @ch: TX channel number to process buffer descriptors for
1278 * @budget: number of packets allowed to process
1279 * @pending: indication to caller that packets are pending to process
1280 *
1281 * Processes TX buffer descriptors after packets are transmitted - checks
1282 * ownership bit on the TX * descriptor and requeues it to free pool & frees
1283 * the SKB buffer. Only "budget" number of packets are processed and
1284 * indication of pending packets provided to the caller
1285 *
1286 * Returns number of packets processed
1287 */
1288 static int emac_tx_bdproc(struct emac_priv *priv, u32 ch, u32 budget)
1289 {
1290 struct device *emac_dev = &priv->ndev->dev;
1291 unsigned long flags;
1292 u32 frame_status;
1293 u32 pkts_processed = 0;
1294 u32 tx_complete_cnt = 0;
1295 struct emac_tx_bd __iomem *curr_bd;
1296 struct emac_txch *txch = priv->txch[ch];
1297 u32 *tx_complete_ptr = txch->tx_complete;
1298
1299 if (unlikely(1 == txch->teardown_pending)) {
1300 if (netif_msg_tx_err(priv) && net_ratelimit()) {
1301 dev_err(emac_dev, "DaVinci EMAC:emac_tx_bdproc: "\
1302 "teardown pending\n");
1303 }
1304 return 0; /* dont handle any pkt completions */
1305 }
1306
1307 ++txch->proc_count;
1308 spin_lock_irqsave(&priv->tx_lock, flags);
1309 curr_bd = txch->active_queue_head;
1310 if (NULL == curr_bd) {
1311 emac_write(EMAC_TXCP(ch),
1312 emac_virt_to_phys(txch->last_hw_bdprocessed, priv));
1313 txch->no_active_pkts++;
1314 spin_unlock_irqrestore(&priv->tx_lock, flags);
1315 return 0;
1316 }
1317 BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1318 frame_status = curr_bd->mode;
1319 while ((curr_bd) &&
1320 ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) &&
1321 (pkts_processed < budget)) {
1322 emac_write(EMAC_TXCP(ch), emac_virt_to_phys(curr_bd, priv));
1323 txch->active_queue_head = curr_bd->next;
1324 if (frame_status & EMAC_CPPI_EOQ_BIT) {
1325 if (curr_bd->next) { /* misqueued packet */
1326 emac_write(EMAC_TXHDP(ch), curr_bd->h_next);
1327 ++txch->mis_queued_packets;
1328 } else {
1329 txch->queue_active = 0; /* end of queue */
1330 }
1331 }
1332 *tx_complete_ptr = (u32) curr_bd->buf_token;
1333 ++tx_complete_ptr;
1334 ++tx_complete_cnt;
1335 curr_bd->next = txch->bd_pool_head;
1336 txch->bd_pool_head = curr_bd;
1337 --txch->active_queue_count;
1338 pkts_processed++;
1339 txch->last_hw_bdprocessed = curr_bd;
1340 curr_bd = txch->active_queue_head;
1341 if (curr_bd) {
1342 BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1343 frame_status = curr_bd->mode;
1344 }
1345 } /* end of pkt processing loop */
1346
1347 emac_net_tx_complete(priv,
1348 (void *)&txch->tx_complete[0],
1349 tx_complete_cnt, ch);
1350 spin_unlock_irqrestore(&priv->tx_lock, flags);
1351 return pkts_processed;
1352 }
1353
1354 #define EMAC_ERR_TX_OUT_OF_BD -1
1355
1356 /**
1357 * emac_send: EMAC Transmit function (internal)
1358 * @priv: The DaVinci EMAC private adapter structure
1359 * @pkt: packet pointer (contains skb ptr)
1360 * @ch: TX channel number
1361 *
1362 * Called by the transmit function to queue the packet in EMAC hardware queue
1363 *
1364 * Returns success(0) or error code (typically out of desc's)
1365 */
1366 static int emac_send(struct emac_priv *priv, struct emac_netpktobj *pkt, u32 ch)
1367 {
1368 unsigned long flags;
1369 struct emac_tx_bd __iomem *curr_bd;
1370 struct emac_txch *txch;
1371 struct emac_netbufobj *buf_list;
1372
1373 txch = priv->txch[ch];
1374 buf_list = pkt->buf_list; /* get handle to the buffer array */
1375
1376 /* check packet size and pad if short */
1377 if (pkt->pkt_length < EMAC_DEF_MIN_ETHPKTSIZE) {
1378 buf_list->length += (EMAC_DEF_MIN_ETHPKTSIZE - pkt->pkt_length);
1379 pkt->pkt_length = EMAC_DEF_MIN_ETHPKTSIZE;
1380 }
1381
1382 spin_lock_irqsave(&priv->tx_lock, flags);
1383 curr_bd = txch->bd_pool_head;
1384 if (curr_bd == NULL) {
1385 txch->out_of_tx_bd++;
1386 spin_unlock_irqrestore(&priv->tx_lock, flags);
1387 return EMAC_ERR_TX_OUT_OF_BD;
1388 }
1389
1390 txch->bd_pool_head = curr_bd->next;
1391 curr_bd->buf_token = buf_list->buf_token;
1392 /* FIXME buff_ptr = dma_map_single(... data_ptr ...) */
1393 curr_bd->buff_ptr = virt_to_phys(buf_list->data_ptr);
1394 curr_bd->off_b_len = buf_list->length;
1395 curr_bd->h_next = 0;
1396 curr_bd->next = NULL;
1397 curr_bd->mode = (EMAC_CPPI_SOP_BIT | EMAC_CPPI_OWNERSHIP_BIT |
1398 EMAC_CPPI_EOP_BIT | pkt->pkt_length);
1399
1400 /* flush the packet from cache if write back cache is present */
1401 BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1402
1403 /* send the packet */
1404 if (txch->active_queue_head == NULL) {
1405 txch->active_queue_head = curr_bd;
1406 txch->active_queue_tail = curr_bd;
1407 if (1 != txch->queue_active) {
1408 emac_write(EMAC_TXHDP(ch),
1409 emac_virt_to_phys(curr_bd, priv));
1410 txch->queue_active = 1;
1411 }
1412 ++txch->queue_reinit;
1413 } else {
1414 register struct emac_tx_bd __iomem *tail_bd;
1415 register u32 frame_status;
1416
1417 tail_bd = txch->active_queue_tail;
1418 tail_bd->next = curr_bd;
1419 txch->active_queue_tail = curr_bd;
1420 tail_bd = EMAC_VIRT_NOCACHE(tail_bd);
1421 tail_bd->h_next = (int)emac_virt_to_phys(curr_bd, priv);
1422 frame_status = tail_bd->mode;
1423 if (frame_status & EMAC_CPPI_EOQ_BIT) {
1424 emac_write(EMAC_TXHDP(ch),
1425 emac_virt_to_phys(curr_bd, priv));
1426 frame_status &= ~(EMAC_CPPI_EOQ_BIT);
1427 tail_bd->mode = frame_status;
1428 ++txch->end_of_queue_add;
1429 }
1430 }
1431 txch->active_queue_count++;
1432 spin_unlock_irqrestore(&priv->tx_lock, flags);
1433 return 0;
1434 }
1435
1436 /**
1437 * emac_dev_xmit: EMAC Transmit function
1438 * @skb: SKB pointer
1439 * @ndev: The DaVinci EMAC network adapter
1440 *
1441 * Called by the system to transmit a packet - we queue the packet in
1442 * EMAC hardware transmit queue
1443 *
1444 * Returns success(NETDEV_TX_OK) or error code (typically out of desc's)
1445 */
1446 static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev)
1447 {
1448 struct device *emac_dev = &ndev->dev;
1449 int ret_code;
1450 struct emac_netbufobj tx_buf; /* buffer obj-only single frame support */
1451 struct emac_netpktobj tx_packet; /* packet object */
1452 struct emac_priv *priv = netdev_priv(ndev);
1453
1454 /* If no link, return */
1455 if (unlikely(!priv->link)) {
1456 if (netif_msg_tx_err(priv) && net_ratelimit())
1457 dev_err(emac_dev, "DaVinci EMAC: No link to transmit");
1458 return NETDEV_TX_BUSY;
1459 }
1460
1461 /* Build the buffer and packet objects - Since only single fragment is
1462 * supported, need not set length and token in both packet & object.
1463 * Doing so for completeness sake & to show that this needs to be done
1464 * in multifragment case
1465 */
1466 tx_packet.buf_list = &tx_buf;
1467 tx_packet.num_bufs = 1; /* only single fragment supported */
1468 tx_packet.pkt_length = skb->len;
1469 tx_packet.pkt_token = (void *)skb;
1470 tx_buf.length = skb->len;
1471 tx_buf.buf_token = (void *)skb;
1472 tx_buf.data_ptr = skb->data;
1473 EMAC_CACHE_WRITEBACK((unsigned long)skb->data, skb->len);
1474 ndev->trans_start = jiffies;
1475 ret_code = emac_send(priv, &tx_packet, EMAC_DEF_TX_CH);
1476 if (unlikely(ret_code != 0)) {
1477 if (ret_code == EMAC_ERR_TX_OUT_OF_BD) {
1478 if (netif_msg_tx_err(priv) && net_ratelimit())
1479 dev_err(emac_dev, "DaVinci EMAC: xmit() fatal"\
1480 " err. Out of TX BD's");
1481 netif_stop_queue(priv->ndev);
1482 }
1483 priv->net_dev_stats.tx_dropped++;
1484 return NETDEV_TX_BUSY;
1485 }
1486
1487 return NETDEV_TX_OK;
1488 }
1489
1490 /**
1491 * emac_dev_tx_timeout: EMAC Transmit timeout function
1492 * @ndev: The DaVinci EMAC network adapter
1493 *
1494 * Called when system detects that a skb timeout period has expired
1495 * potentially due to a fault in the adapter in not being able to send
1496 * it out on the wire. We teardown the TX channel assuming a hardware
1497 * error and re-initialize the TX channel for hardware operation
1498 *
1499 */
1500 static void emac_dev_tx_timeout(struct net_device *ndev)
1501 {
1502 struct emac_priv *priv = netdev_priv(ndev);
1503 struct device *emac_dev = &ndev->dev;
1504
1505 if (netif_msg_tx_err(priv))
1506 dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX");
1507
1508 priv->net_dev_stats.tx_errors++;
1509 emac_int_disable(priv);
1510 emac_stop_txch(priv, EMAC_DEF_TX_CH);
1511 emac_cleanup_txch(priv, EMAC_DEF_TX_CH);
1512 emac_init_txch(priv, EMAC_DEF_TX_CH);
1513 emac_write(EMAC_TXHDP(0), 0);
1514 emac_write(EMAC_TXINTMASKSET, BIT(EMAC_DEF_TX_CH));
1515 emac_int_enable(priv);
1516 }
1517
1518 /**
1519 * emac_net_alloc_rx_buf: Allocate a skb for RX
1520 * @priv: The DaVinci EMAC private adapter structure
1521 * @buf_size: size of SKB data buffer to allocate
1522 * @data_token: data token returned (skb handle for storing in buffer desc)
1523 * @ch: RX channel number
1524 *
1525 * Called during RX channel setup - allocates skb buffer of required size
1526 * and provides the skb handle and allocated buffer data pointer to caller
1527 *
1528 * Returns skb data pointer or 0 on failure to alloc skb
1529 */
1530 static void *emac_net_alloc_rx_buf(struct emac_priv *priv, int buf_size,
1531 void **data_token, u32 ch)
1532 {
1533 struct net_device *ndev = priv->ndev;
1534 struct device *emac_dev = &ndev->dev;
1535 struct sk_buff *p_skb;
1536
1537 p_skb = dev_alloc_skb(buf_size);
1538 if (unlikely(NULL == p_skb)) {
1539 if (netif_msg_rx_err(priv) && net_ratelimit())
1540 dev_err(emac_dev, "DaVinci EMAC: failed to alloc skb");
1541 return NULL;
1542 }
1543
1544 /* set device pointer in skb and reserve space for extra bytes */
1545 p_skb->dev = ndev;
1546 skb_reserve(p_skb, NET_IP_ALIGN);
1547 *data_token = (void *) p_skb;
1548 EMAC_CACHE_WRITEBACK_INVALIDATE((unsigned long)p_skb->data, buf_size);
1549 return p_skb->data;
1550 }
1551
1552 /**
1553 * emac_init_rxch: RX channel initialization
1554 * @priv: The DaVinci EMAC private adapter structure
1555 * @ch: RX channel number
1556 * @param: mac address for RX channel
1557 *
1558 * Called during device init to setup a RX channel (allocate buffers and
1559 * buffer descriptors, create queue and keep ready for reception
1560 *
1561 * Returns success(0) or mem alloc failures error code
1562 */
1563 static int emac_init_rxch(struct emac_priv *priv, u32 ch, char *param)
1564 {
1565 struct device *emac_dev = &priv->ndev->dev;
1566 u32 cnt, bd_size;
1567 void __iomem *mem;
1568 struct emac_rx_bd __iomem *curr_bd;
1569 struct emac_rxch *rxch = NULL;
1570
1571 rxch = kzalloc(sizeof(struct emac_rxch), GFP_KERNEL);
1572 if (NULL == rxch) {
1573 dev_err(emac_dev, "DaVinci EMAC: RX Ch mem alloc failed");
1574 return -ENOMEM;
1575 }
1576 priv->rxch[ch] = rxch;
1577 rxch->buf_size = priv->rx_buf_size;
1578 rxch->service_max = EMAC_DEF_RX_MAX_SERVICE;
1579 rxch->queue_active = 0;
1580 rxch->teardown_pending = 0;
1581
1582 /* save mac address */
1583 for (cnt = 0; cnt < 6; cnt++)
1584 rxch->mac_addr[cnt] = param[cnt];
1585
1586 /* allocate buffer descriptor pool align every BD on four word
1587 * boundry for future requirements */
1588 bd_size = (sizeof(struct emac_rx_bd) + 0xF) & ~0xF;
1589 rxch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size;
1590 rxch->alloc_size = (((bd_size * rxch->num_bd) + 0xF) & ~0xF);
1591 rxch->bd_mem = EMAC_RX_BD_MEM(priv);
1592 __memzero((void __force *)rxch->bd_mem, rxch->alloc_size);
1593 rxch->pkt_queue.buf_list = &rxch->buf_queue;
1594
1595 /* allocate RX buffer and initialize the BD linked list */
1596 mem = (void __force __iomem *)
1597 (((u32 __force) rxch->bd_mem + 0xF) & ~0xF);
1598 rxch->active_queue_head = NULL;
1599 rxch->active_queue_tail = mem;
1600 for (cnt = 0; cnt < rxch->num_bd; cnt++) {
1601 curr_bd = mem + (cnt * bd_size);
1602 /* for future use the last parameter contains the BD ptr */
1603 curr_bd->data_ptr = emac_net_alloc_rx_buf(priv,
1604 rxch->buf_size,
1605 (void __force **)&curr_bd->buf_token,
1606 EMAC_DEF_RX_CH);
1607 if (curr_bd->data_ptr == NULL) {
1608 dev_err(emac_dev, "DaVinci EMAC: RX buf mem alloc " \
1609 "failed for ch %d\n", ch);
1610 kfree(rxch);
1611 return -ENOMEM;
1612 }
1613
1614 /* populate the hardware descriptor */
1615 curr_bd->h_next = emac_virt_to_phys(rxch->active_queue_head,
1616 priv);
1617 /* FIXME buff_ptr = dma_map_single(... data_ptr ...) */
1618 curr_bd->buff_ptr = virt_to_phys(curr_bd->data_ptr);
1619 curr_bd->off_b_len = rxch->buf_size;
1620 curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT;
1621
1622 /* write back to hardware memory */
1623 BD_CACHE_WRITEBACK_INVALIDATE((u32) curr_bd,
1624 EMAC_BD_LENGTH_FOR_CACHE);
1625 curr_bd->next = rxch->active_queue_head;
1626 rxch->active_queue_head = curr_bd;
1627 }
1628
1629 /* At this point rxCppi->activeQueueHead points to the first
1630 RX BD ready to be given to RX HDP and rxch->active_queue_tail
1631 points to the last RX BD
1632 */
1633 return 0;
1634 }
1635
1636 /**
1637 * emac_rxch_teardown: RX channel teardown
1638 * @priv: The DaVinci EMAC private adapter structure
1639 * @ch: RX channel number
1640 *
1641 * Called during device stop to teardown RX channel
1642 *
1643 */
1644 static void emac_rxch_teardown(struct emac_priv *priv, u32 ch)
1645 {
1646 struct device *emac_dev = &priv->ndev->dev;
1647 u32 teardown_cnt = 0xFFFFFFF0; /* Some high value */
1648
1649 while ((emac_read(EMAC_RXCP(ch)) & EMAC_TEARDOWN_VALUE) !=
1650 EMAC_TEARDOWN_VALUE) {
1651 /* wait till tx teardown complete */
1652 cpu_relax(); /* TODO: check if this helps ... */
1653 --teardown_cnt;
1654 if (0 == teardown_cnt) {
1655 dev_err(emac_dev, "EMAC: RX teardown aborted\n");
1656 break;
1657 }
1658 }
1659 emac_write(EMAC_RXCP(ch), EMAC_TEARDOWN_VALUE);
1660 }
1661
1662 /**
1663 * emac_stop_rxch: Stop RX channel operation
1664 * @priv: The DaVinci EMAC private adapter structure
1665 * @ch: RX channel number
1666 *
1667 * Called during device stop to stop RX channel operation
1668 *
1669 */
1670 static void emac_stop_rxch(struct emac_priv *priv, u32 ch)
1671 {
1672 struct emac_rxch *rxch = priv->rxch[ch];
1673
1674 if (rxch) {
1675 rxch->teardown_pending = 1;
1676 emac_write(EMAC_RXTEARDOWN, ch);
1677 /* wait for teardown complete */
1678 emac_rxch_teardown(priv, ch);
1679 rxch->teardown_pending = 0;
1680 emac_write(EMAC_RXINTMASKCLEAR, BIT(ch));
1681 }
1682 }
1683
1684 /**
1685 * emac_cleanup_rxch: Book-keep function to clean RX channel resources
1686 * @priv: The DaVinci EMAC private adapter structure
1687 * @ch: RX channel number
1688 *
1689 * Called during device stop to clean up RX channel resources
1690 *
1691 */
1692 static void emac_cleanup_rxch(struct emac_priv *priv, u32 ch)
1693 {
1694 struct emac_rxch *rxch = priv->rxch[ch];
1695 struct emac_rx_bd __iomem *curr_bd;
1696
1697 if (rxch) {
1698 /* free the receive buffers previously allocated */
1699 curr_bd = rxch->active_queue_head;
1700 while (curr_bd) {
1701 if (curr_bd->buf_token) {
1702 dev_kfree_skb_any((struct sk_buff *)\
1703 curr_bd->buf_token);
1704 }
1705 curr_bd = curr_bd->next;
1706 }
1707 if (rxch->bd_mem)
1708 rxch->bd_mem = NULL;
1709 kfree(rxch);
1710 priv->rxch[ch] = NULL;
1711 }
1712 }
1713
1714 /**
1715 * emac_set_type0addr: Set EMAC Type0 mac address
1716 * @priv: The DaVinci EMAC private adapter structure
1717 * @ch: RX channel number
1718 * @mac_addr: MAC address to set in device
1719 *
1720 * Called internally to set Type0 mac address of the adapter (Device)
1721 *
1722 * Returns success (0) or appropriate error code (none as of now)
1723 */
1724 static void emac_set_type0addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1725 {
1726 u32 val;
1727 val = ((mac_addr[5] << 8) | (mac_addr[4]));
1728 emac_write(EMAC_MACSRCADDRLO, val);
1729
1730 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1731 (mac_addr[1] << 8) | (mac_addr[0]));
1732 emac_write(EMAC_MACSRCADDRHI, val);
1733 val = emac_read(EMAC_RXUNICASTSET);
1734 val |= BIT(ch);
1735 emac_write(EMAC_RXUNICASTSET, val);
1736 val = emac_read(EMAC_RXUNICASTCLEAR);
1737 val &= ~BIT(ch);
1738 emac_write(EMAC_RXUNICASTCLEAR, val);
1739 }
1740
1741 /**
1742 * emac_set_type1addr: Set EMAC Type1 mac address
1743 * @priv: The DaVinci EMAC private adapter structure
1744 * @ch: RX channel number
1745 * @mac_addr: MAC address to set in device
1746 *
1747 * Called internally to set Type1 mac address of the adapter (Device)
1748 *
1749 * Returns success (0) or appropriate error code (none as of now)
1750 */
1751 static void emac_set_type1addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1752 {
1753 u32 val;
1754 emac_write(EMAC_MACINDEX, ch);
1755 val = ((mac_addr[5] << 8) | mac_addr[4]);
1756 emac_write(EMAC_MACADDRLO, val);
1757 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1758 (mac_addr[1] << 8) | (mac_addr[0]));
1759 emac_write(EMAC_MACADDRHI, val);
1760 emac_set_type0addr(priv, ch, mac_addr);
1761 }
1762
1763 /**
1764 * emac_set_type2addr: Set EMAC Type2 mac address
1765 * @priv: The DaVinci EMAC private adapter structure
1766 * @ch: RX channel number
1767 * @mac_addr: MAC address to set in device
1768 * @index: index into RX address entries
1769 * @match: match parameter for RX address matching logic
1770 *
1771 * Called internally to set Type2 mac address of the adapter (Device)
1772 *
1773 * Returns success (0) or appropriate error code (none as of now)
1774 */
1775 static void emac_set_type2addr(struct emac_priv *priv, u32 ch,
1776 char *mac_addr, int index, int match)
1777 {
1778 u32 val;
1779 emac_write(EMAC_MACINDEX, index);
1780 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1781 (mac_addr[1] << 8) | (mac_addr[0]));
1782 emac_write(EMAC_MACADDRHI, val);
1783 val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \
1784 (match << 19) | BIT(20));
1785 emac_write(EMAC_MACADDRLO, val);
1786 emac_set_type0addr(priv, ch, mac_addr);
1787 }
1788
1789 /**
1790 * emac_setmac: Set mac address in the adapter (internal function)
1791 * @priv: The DaVinci EMAC private adapter structure
1792 * @ch: RX channel number
1793 * @mac_addr: MAC address to set in device
1794 *
1795 * Called internally to set the mac address of the adapter (Device)
1796 *
1797 * Returns success (0) or appropriate error code (none as of now)
1798 */
1799 static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr)
1800 {
1801 struct device *emac_dev = &priv->ndev->dev;
1802
1803 if (priv->rx_addr_type == 0) {
1804 emac_set_type0addr(priv, ch, mac_addr);
1805 } else if (priv->rx_addr_type == 1) {
1806 u32 cnt;
1807 for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++)
1808 emac_set_type1addr(priv, ch, mac_addr);
1809 } else if (priv->rx_addr_type == 2) {
1810 emac_set_type2addr(priv, ch, mac_addr, ch, 1);
1811 emac_set_type0addr(priv, ch, mac_addr);
1812 } else {
1813 if (netif_msg_drv(priv))
1814 dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n");
1815 }
1816 }
1817
1818 /**
1819 * emac_dev_setmac_addr: Set mac address in the adapter
1820 * @ndev: The DaVinci EMAC network adapter
1821 * @addr: MAC address to set in device
1822 *
1823 * Called by the system to set the mac address of the adapter (Device)
1824 *
1825 * Returns success (0) or appropriate error code (none as of now)
1826 */
1827 static int emac_dev_setmac_addr(struct net_device *ndev, void *addr)
1828 {
1829 struct emac_priv *priv = netdev_priv(ndev);
1830 struct emac_rxch *rxch = priv->rxch[EMAC_DEF_RX_CH];
1831 struct device *emac_dev = &priv->ndev->dev;
1832 struct sockaddr *sa = addr;
1833
1834 if (!is_valid_ether_addr(sa->sa_data))
1835 return -EINVAL;
1836
1837 /* Store mac addr in priv and rx channel and set it in EMAC hw */
1838 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
1839 memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len);
1840
1841 /* If the interface is down - rxch is NULL. */
1842 /* MAC address is configured only after the interface is enabled. */
1843 if (netif_running(ndev)) {
1844 memcpy(rxch->mac_addr, sa->sa_data, ndev->addr_len);
1845 emac_setmac(priv, EMAC_DEF_RX_CH, rxch->mac_addr);
1846 }
1847
1848 if (netif_msg_drv(priv))
1849 dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n",
1850 priv->mac_addr);
1851
1852 return 0;
1853 }
1854
1855 /**
1856 * emac_addbd_to_rx_queue: Recycle RX buffer descriptor
1857 * @priv: The DaVinci EMAC private adapter structure
1858 * @ch: RX channel number to process buffer descriptors for
1859 * @curr_bd: current buffer descriptor
1860 * @buffer: buffer pointer for descriptor
1861 * @buf_token: buffer token (stores skb information)
1862 *
1863 * Prepares the recycled buffer descriptor and addes it to hardware
1864 * receive queue - if queue empty this descriptor becomes the head
1865 * else addes the descriptor to end of queue
1866 *
1867 */
1868 static void emac_addbd_to_rx_queue(struct emac_priv *priv, u32 ch,
1869 struct emac_rx_bd __iomem *curr_bd,
1870 char *buffer, void *buf_token)
1871 {
1872 struct emac_rxch *rxch = priv->rxch[ch];
1873
1874 /* populate the hardware descriptor */
1875 curr_bd->h_next = 0;
1876 /* FIXME buff_ptr = dma_map_single(... buffer ...) */
1877 curr_bd->buff_ptr = virt_to_phys(buffer);
1878 curr_bd->off_b_len = rxch->buf_size;
1879 curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT;
1880 curr_bd->next = NULL;
1881 curr_bd->data_ptr = buffer;
1882 curr_bd->buf_token = buf_token;
1883
1884 /* write back */
1885 BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1886 if (rxch->active_queue_head == NULL) {
1887 rxch->active_queue_head = curr_bd;
1888 rxch->active_queue_tail = curr_bd;
1889 if (0 != rxch->queue_active) {
1890 emac_write(EMAC_RXHDP(ch),
1891 emac_virt_to_phys(rxch->active_queue_head, priv));
1892 rxch->queue_active = 1;
1893 }
1894 } else {
1895 struct emac_rx_bd __iomem *tail_bd;
1896 u32 frame_status;
1897
1898 tail_bd = rxch->active_queue_tail;
1899 rxch->active_queue_tail = curr_bd;
1900 tail_bd->next = curr_bd;
1901 tail_bd = EMAC_VIRT_NOCACHE(tail_bd);
1902 tail_bd->h_next = emac_virt_to_phys(curr_bd, priv);
1903 frame_status = tail_bd->mode;
1904 if (frame_status & EMAC_CPPI_EOQ_BIT) {
1905 emac_write(EMAC_RXHDP(ch),
1906 emac_virt_to_phys(curr_bd, priv));
1907 frame_status &= ~(EMAC_CPPI_EOQ_BIT);
1908 tail_bd->mode = frame_status;
1909 ++rxch->end_of_queue_add;
1910 }
1911 }
1912 ++rxch->recycled_bd;
1913 }
1914
1915 /**
1916 * emac_net_rx_cb: Prepares packet and sends to upper layer
1917 * @priv: The DaVinci EMAC private adapter structure
1918 * @net_pkt_list: Network packet list (received packets)
1919 *
1920 * Invalidates packet buffer memory and sends the received packet to upper
1921 * layer
1922 *
1923 * Returns success or appropriate error code (none as of now)
1924 */
1925 static int emac_net_rx_cb(struct emac_priv *priv,
1926 struct emac_netpktobj *net_pkt_list)
1927 {
1928 struct sk_buff *p_skb;
1929 p_skb = (struct sk_buff *)net_pkt_list->pkt_token;
1930 /* set length of packet */
1931 skb_put(p_skb, net_pkt_list->pkt_length);
1932 EMAC_CACHE_INVALIDATE((unsigned long)p_skb->data, p_skb->len);
1933 p_skb->protocol = eth_type_trans(p_skb, priv->ndev);
1934 netif_receive_skb(p_skb);
1935 priv->net_dev_stats.rx_bytes += net_pkt_list->pkt_length;
1936 priv->net_dev_stats.rx_packets++;
1937 return 0;
1938 }
1939
1940 /**
1941 * emac_rx_bdproc: RX buffer descriptor (packet) processing
1942 * @priv: The DaVinci EMAC private adapter structure
1943 * @ch: RX channel number to process buffer descriptors for
1944 * @budget: number of packets allowed to process
1945 * @pending: indication to caller that packets are pending to process
1946 *
1947 * Processes RX buffer descriptors - checks ownership bit on the RX buffer
1948 * descriptor, sends the receive packet to upper layer, allocates a new SKB
1949 * and recycles the buffer descriptor (requeues it in hardware RX queue).
1950 * Only "budget" number of packets are processed and indication of pending
1951 * packets provided to the caller.
1952 *
1953 * Returns number of packets processed (and indication of pending packets)
1954 */
1955 static int emac_rx_bdproc(struct emac_priv *priv, u32 ch, u32 budget)
1956 {
1957 unsigned long flags;
1958 u32 frame_status;
1959 u32 pkts_processed = 0;
1960 char *new_buffer;
1961 struct emac_rx_bd __iomem *curr_bd;
1962 struct emac_rx_bd __iomem *last_bd;
1963 struct emac_netpktobj *curr_pkt, pkt_obj;
1964 struct emac_netbufobj buf_obj;
1965 struct emac_netbufobj *rx_buf_obj;
1966 void *new_buf_token;
1967 struct emac_rxch *rxch = priv->rxch[ch];
1968
1969 if (unlikely(1 == rxch->teardown_pending))
1970 return 0;
1971 ++rxch->proc_count;
1972 spin_lock_irqsave(&priv->rx_lock, flags);
1973 pkt_obj.buf_list = &buf_obj;
1974 curr_pkt = &pkt_obj;
1975 curr_bd = rxch->active_queue_head;
1976 BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1977 frame_status = curr_bd->mode;
1978
1979 while ((curr_bd) &&
1980 ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) &&
1981 (pkts_processed < budget)) {
1982
1983 new_buffer = emac_net_alloc_rx_buf(priv, rxch->buf_size,
1984 &new_buf_token, EMAC_DEF_RX_CH);
1985 if (unlikely(NULL == new_buffer)) {
1986 ++rxch->out_of_rx_buffers;
1987 goto end_emac_rx_bdproc;
1988 }
1989
1990 /* populate received packet data structure */
1991 rx_buf_obj = &curr_pkt->buf_list[0];
1992 rx_buf_obj->data_ptr = (char *)curr_bd->data_ptr;
1993 rx_buf_obj->length = curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE;
1994 rx_buf_obj->buf_token = curr_bd->buf_token;
1995 curr_pkt->pkt_token = curr_pkt->buf_list->buf_token;
1996 curr_pkt->num_bufs = 1;
1997 curr_pkt->pkt_length =
1998 (frame_status & EMAC_RX_BD_PKT_LENGTH_MASK);
1999 emac_write(EMAC_RXCP(ch), emac_virt_to_phys(curr_bd, priv));
2000 ++rxch->processed_bd;
2001 last_bd = curr_bd;
2002 curr_bd = last_bd->next;
2003 rxch->active_queue_head = curr_bd;
2004
2005 /* check if end of RX queue ? */
2006 if (frame_status & EMAC_CPPI_EOQ_BIT) {
2007 if (curr_bd) {
2008 ++rxch->mis_queued_packets;
2009 emac_write(EMAC_RXHDP(ch),
2010 emac_virt_to_phys(curr_bd, priv));
2011 } else {
2012 ++rxch->end_of_queue;
2013 rxch->queue_active = 0;
2014 }
2015 }
2016
2017 /* recycle BD */
2018 emac_addbd_to_rx_queue(priv, ch, last_bd, new_buffer,
2019 new_buf_token);
2020
2021 /* return the packet to the user - BD ptr passed in
2022 * last parameter for potential *future* use */
2023 spin_unlock_irqrestore(&priv->rx_lock, flags);
2024 emac_net_rx_cb(priv, curr_pkt);
2025 spin_lock_irqsave(&priv->rx_lock, flags);
2026 curr_bd = rxch->active_queue_head;
2027 if (curr_bd) {
2028 BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
2029 frame_status = curr_bd->mode;
2030 }
2031 ++pkts_processed;
2032 }
2033
2034 end_emac_rx_bdproc:
2035 spin_unlock_irqrestore(&priv->rx_lock, flags);
2036 return pkts_processed;
2037 }
2038
2039 /**
2040 * emac_hw_enable: Enable EMAC hardware for packet transmission/reception
2041 * @priv: The DaVinci EMAC private adapter structure
2042 *
2043 * Enables EMAC hardware for packet processing - enables PHY, enables RX
2044 * for packet reception and enables device interrupts and then NAPI
2045 *
2046 * Returns success (0) or appropriate error code (none right now)
2047 */
2048 static int emac_hw_enable(struct emac_priv *priv)
2049 {
2050 u32 ch, val, mbp_enable, mac_control;
2051
2052 /* Soft reset */
2053 emac_write(EMAC_SOFTRESET, 1);
2054 while (emac_read(EMAC_SOFTRESET))
2055 cpu_relax();
2056
2057 /* Disable interrupt & Set pacing for more interrupts initially */
2058 emac_int_disable(priv);
2059
2060 /* Full duplex enable bit set when auto negotiation happens */
2061 mac_control =
2062 (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) |
2063 ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) |
2064 ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) |
2065 ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0));
2066 emac_write(EMAC_MACCONTROL, mac_control);
2067
2068 mbp_enable =
2069 (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) |
2070 ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) |
2071 ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) |
2072 ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) |
2073 ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) |
2074 ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) |
2075 ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) |
2076 ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \
2077 EMAC_RXMBP_PROMCH_SHIFT) |
2078 ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) |
2079 ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \
2080 EMAC_RXMBP_BROADCH_SHIFT) |
2081 ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) |
2082 ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \
2083 EMAC_RXMBP_MULTICH_SHIFT));
2084 emac_write(EMAC_RXMBPENABLE, mbp_enable);
2085 emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE &
2086 EMAC_RX_MAX_LEN_MASK));
2087 emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET &
2088 EMAC_RX_BUFFER_OFFSET_MASK));
2089 emac_write(EMAC_RXFILTERLOWTHRESH, 0);
2090 emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL);
2091 priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF;
2092
2093 val = emac_read(EMAC_TXCONTROL);
2094 val |= EMAC_TX_CONTROL_TX_ENABLE_VAL;
2095 emac_write(EMAC_TXCONTROL, val);
2096 val = emac_read(EMAC_RXCONTROL);
2097 val |= EMAC_RX_CONTROL_RX_ENABLE_VAL;
2098 emac_write(EMAC_RXCONTROL, val);
2099 emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL);
2100
2101 for (ch = 0; ch < EMAC_DEF_MAX_TX_CH; ch++) {
2102 emac_write(EMAC_TXHDP(ch), 0);
2103 emac_write(EMAC_TXINTMASKSET, BIT(ch));
2104 }
2105 for (ch = 0; ch < EMAC_DEF_MAX_RX_CH; ch++) {
2106 struct emac_rxch *rxch = priv->rxch[ch];
2107 emac_setmac(priv, ch, rxch->mac_addr);
2108 emac_write(EMAC_RXINTMASKSET, BIT(ch));
2109 rxch->queue_active = 1;
2110 emac_write(EMAC_RXHDP(ch),
2111 emac_virt_to_phys(rxch->active_queue_head, priv));
2112 }
2113
2114 /* Enable MII */
2115 val = emac_read(EMAC_MACCONTROL);
2116 val |= (EMAC_MACCONTROL_GMIIEN);
2117 emac_write(EMAC_MACCONTROL, val);
2118
2119 /* Enable NAPI and interrupts */
2120 napi_enable(&priv->napi);
2121 emac_int_enable(priv);
2122 return 0;
2123
2124 }
2125
2126 /**
2127 * emac_poll: EMAC NAPI Poll function
2128 * @ndev: The DaVinci EMAC network adapter
2129 * @budget: Number of receive packets to process (as told by NAPI layer)
2130 *
2131 * NAPI Poll function implemented to process packets as per budget. We check
2132 * the type of interrupt on the device and accordingly call the TX or RX
2133 * packet processing functions. We follow the budget for RX processing and
2134 * also put a cap on number of TX pkts processed through config param. The
2135 * NAPI schedule function is called if more packets pending.
2136 *
2137 * Returns number of packets received (in most cases; else TX pkts - rarely)
2138 */
2139 static int emac_poll(struct napi_struct *napi, int budget)
2140 {
2141 unsigned int mask;
2142 struct emac_priv *priv = container_of(napi, struct emac_priv, napi);
2143 struct net_device *ndev = priv->ndev;
2144 struct device *emac_dev = &ndev->dev;
2145 u32 status = 0;
2146 u32 num_pkts = 0;
2147
2148 /* Check interrupt vectors and call packet processing */
2149 status = emac_read(EMAC_MACINVECTOR);
2150
2151 mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC;
2152
2153 if (priv->version == EMAC_VERSION_2)
2154 mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC;
2155
2156 if (status & mask) {
2157 num_pkts = emac_tx_bdproc(priv, EMAC_DEF_TX_CH,
2158 EMAC_DEF_TX_MAX_SERVICE);
2159 } /* TX processing */
2160
2161 if (num_pkts)
2162 return budget;
2163
2164 mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC;
2165
2166 if (priv->version == EMAC_VERSION_2)
2167 mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC;
2168
2169 if (status & mask) {
2170 num_pkts = emac_rx_bdproc(priv, EMAC_DEF_RX_CH, budget);
2171 } /* RX processing */
2172
2173 if (num_pkts < budget) {
2174 napi_complete(napi);
2175 emac_int_enable(priv);
2176 }
2177
2178 mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT;
2179 if (priv->version == EMAC_VERSION_2)
2180 mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT;
2181
2182 if (unlikely(status & mask)) {
2183 u32 ch, cause;
2184 dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n");
2185 netif_stop_queue(ndev);
2186 napi_disable(&priv->napi);
2187
2188 status = emac_read(EMAC_MACSTATUS);
2189 cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >>
2190 EMAC_MACSTATUS_TXERRCODE_SHIFT);
2191 if (cause) {
2192 ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >>
2193 EMAC_MACSTATUS_TXERRCH_SHIFT);
2194 if (net_ratelimit()) {
2195 dev_err(emac_dev, "TX Host error %s on ch=%d\n",
2196 &emac_txhost_errcodes[cause][0], ch);
2197 }
2198 }
2199 cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >>
2200 EMAC_MACSTATUS_RXERRCODE_SHIFT);
2201 if (cause) {
2202 ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >>
2203 EMAC_MACSTATUS_RXERRCH_SHIFT);
2204 if (netif_msg_hw(priv) && net_ratelimit())
2205 dev_err(emac_dev, "RX Host error %s on ch=%d\n",
2206 &emac_rxhost_errcodes[cause][0], ch);
2207 }
2208 } /* Host error processing */
2209
2210 return num_pkts;
2211 }
2212
2213 #ifdef CONFIG_NET_POLL_CONTROLLER
2214 /**
2215 * emac_poll_controller: EMAC Poll controller function
2216 * @ndev: The DaVinci EMAC network adapter
2217 *
2218 * Polled functionality used by netconsole and others in non interrupt mode
2219 *
2220 */
2221 void emac_poll_controller(struct net_device *ndev)
2222 {
2223 struct emac_priv *priv = netdev_priv(ndev);
2224
2225 emac_int_disable(priv);
2226 emac_irq(ndev->irq, priv);
2227 emac_int_enable(priv);
2228 }
2229 #endif
2230
2231 /* PHY/MII bus related */
2232
2233 /* Wait until mdio is ready for next command */
2234 #define MDIO_WAIT_FOR_USER_ACCESS\
2235 while ((emac_mdio_read((MDIO_USERACCESS(0))) &\
2236 MDIO_USERACCESS_GO) != 0)
2237
2238 static int emac_mii_read(struct mii_bus *bus, int phy_id, int phy_reg)
2239 {
2240 unsigned int phy_data = 0;
2241 unsigned int phy_control;
2242
2243 /* Wait until mdio is ready for next command */
2244 MDIO_WAIT_FOR_USER_ACCESS;
2245
2246 phy_control = (MDIO_USERACCESS_GO |
2247 MDIO_USERACCESS_READ |
2248 ((phy_reg << 21) & MDIO_USERACCESS_REGADR) |
2249 ((phy_id << 16) & MDIO_USERACCESS_PHYADR) |
2250 (phy_data & MDIO_USERACCESS_DATA));
2251 emac_mdio_write(MDIO_USERACCESS(0), phy_control);
2252
2253 /* Wait until mdio is ready for next command */
2254 MDIO_WAIT_FOR_USER_ACCESS;
2255
2256 return emac_mdio_read(MDIO_USERACCESS(0)) & MDIO_USERACCESS_DATA;
2257
2258 }
2259
2260 static int emac_mii_write(struct mii_bus *bus, int phy_id,
2261 int phy_reg, u16 phy_data)
2262 {
2263
2264 unsigned int control;
2265
2266 /* until mdio is ready for next command */
2267 MDIO_WAIT_FOR_USER_ACCESS;
2268
2269 control = (MDIO_USERACCESS_GO |
2270 MDIO_USERACCESS_WRITE |
2271 ((phy_reg << 21) & MDIO_USERACCESS_REGADR) |
2272 ((phy_id << 16) & MDIO_USERACCESS_PHYADR) |
2273 (phy_data & MDIO_USERACCESS_DATA));
2274 emac_mdio_write(MDIO_USERACCESS(0), control);
2275
2276 return 0;
2277 }
2278
2279 static int emac_mii_reset(struct mii_bus *bus)
2280 {
2281 unsigned int clk_div;
2282 int mdio_bus_freq = emac_bus_frequency;
2283
2284 if (mdio_max_freq & mdio_bus_freq)
2285 clk_div = ((mdio_bus_freq / mdio_max_freq) - 1);
2286 else
2287 clk_div = 0xFF;
2288
2289 clk_div &= MDIO_CONTROL_CLKDIV;
2290
2291 /* Set enable and clock divider in MDIOControl */
2292 emac_mdio_write(MDIO_CONTROL, (clk_div | MDIO_CONTROL_ENABLE));
2293
2294 return 0;
2295
2296 }
2297
2298 static int mii_irqs[PHY_MAX_ADDR] = { PHY_POLL, PHY_POLL };
2299
2300 /* emac_driver: EMAC MII bus structure */
2301
2302 static struct mii_bus *emac_mii;
2303
2304 static void emac_adjust_link(struct net_device *ndev)
2305 {
2306 struct emac_priv *priv = netdev_priv(ndev);
2307 struct phy_device *phydev = priv->phydev;
2308 unsigned long flags;
2309 int new_state = 0;
2310
2311 spin_lock_irqsave(&priv->lock, flags);
2312
2313 if (phydev->link) {
2314 /* check the mode of operation - full/half duplex */
2315 if (phydev->duplex != priv->duplex) {
2316 new_state = 1;
2317 priv->duplex = phydev->duplex;
2318 }
2319 if (phydev->speed != priv->speed) {
2320 new_state = 1;
2321 priv->speed = phydev->speed;
2322 }
2323 if (!priv->link) {
2324 new_state = 1;
2325 priv->link = 1;
2326 }
2327
2328 } else if (priv->link) {
2329 new_state = 1;
2330 priv->link = 0;
2331 priv->speed = 0;
2332 priv->duplex = ~0;
2333 }
2334 if (new_state) {
2335 emac_update_phystatus(priv);
2336 phy_print_status(priv->phydev);
2337 }
2338
2339 spin_unlock_irqrestore(&priv->lock, flags);
2340 }
2341
2342 /*************************************************************************
2343 * Linux Driver Model
2344 *************************************************************************/
2345
2346 /**
2347 * emac_devioctl: EMAC adapter ioctl
2348 * @ndev: The DaVinci EMAC network adapter
2349 * @ifrq: request parameter
2350 * @cmd: command parameter
2351 *
2352 * EMAC driver ioctl function
2353 *
2354 * Returns success(0) or appropriate error code
2355 */
2356 static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd)
2357 {
2358 dev_warn(&ndev->dev, "DaVinci EMAC: ioctl not supported\n");
2359
2360 if (!(netif_running(ndev)))
2361 return -EINVAL;
2362
2363 /* TODO: Add phy read and write and private statistics get feature */
2364
2365 return -EOPNOTSUPP;
2366 }
2367
2368 /**
2369 * emac_dev_open: EMAC device open
2370 * @ndev: The DaVinci EMAC network adapter
2371 *
2372 * Called when system wants to start the interface. We init TX/RX channels
2373 * and enable the hardware for packet reception/transmission and start the
2374 * network queue.
2375 *
2376 * Returns 0 for a successful open, or appropriate error code
2377 */
2378 static int emac_dev_open(struct net_device *ndev)
2379 {
2380 struct device *emac_dev = &ndev->dev;
2381 u32 rc, cnt, ch;
2382 int phy_addr;
2383 struct resource *res;
2384 int q, m;
2385 int i = 0;
2386 int k = 0;
2387 struct emac_priv *priv = netdev_priv(ndev);
2388
2389 netif_carrier_off(ndev);
2390 for (cnt = 0; cnt <= ETH_ALEN; cnt++)
2391 ndev->dev_addr[cnt] = priv->mac_addr[cnt];
2392
2393 /* Configuration items */
2394 priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN;
2395
2396 /* Clear basic hardware */
2397 for (ch = 0; ch < EMAC_MAX_TXRX_CHANNELS; ch++) {
2398 emac_write(EMAC_TXHDP(ch), 0);
2399 emac_write(EMAC_RXHDP(ch), 0);
2400 emac_write(EMAC_RXHDP(ch), 0);
2401 emac_write(EMAC_RXINTMASKCLEAR, EMAC_INT_MASK_CLEAR);
2402 emac_write(EMAC_TXINTMASKCLEAR, EMAC_INT_MASK_CLEAR);
2403 }
2404 priv->mac_hash1 = 0;
2405 priv->mac_hash2 = 0;
2406 emac_write(EMAC_MACHASH1, 0);
2407 emac_write(EMAC_MACHASH2, 0);
2408
2409 /* multi ch not supported - open 1 TX, 1RX ch by default */
2410 rc = emac_init_txch(priv, EMAC_DEF_TX_CH);
2411 if (0 != rc) {
2412 dev_err(emac_dev, "DaVinci EMAC: emac_init_txch() failed");
2413 return rc;
2414 }
2415 rc = emac_init_rxch(priv, EMAC_DEF_RX_CH, priv->mac_addr);
2416 if (0 != rc) {
2417 dev_err(emac_dev, "DaVinci EMAC: emac_init_rxch() failed");
2418 return rc;
2419 }
2420
2421 /* Request IRQ */
2422
2423 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
2424 for (i = res->start; i <= res->end; i++) {
2425 if (request_irq(i, emac_irq, IRQF_DISABLED,
2426 ndev->name, ndev))
2427 goto rollback;
2428 }
2429 k++;
2430 }
2431
2432 /* Start/Enable EMAC hardware */
2433 emac_hw_enable(priv);
2434
2435 /* find the first phy */
2436 priv->phydev = NULL;
2437 if (priv->phy_mask) {
2438 emac_mii_reset(priv->mii_bus);
2439 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
2440 if (priv->mii_bus->phy_map[phy_addr]) {
2441 priv->phydev = priv->mii_bus->phy_map[phy_addr];
2442 break;
2443 }
2444 }
2445
2446 if (!priv->phydev) {
2447 printk(KERN_ERR "%s: no PHY found\n", ndev->name);
2448 return -1;
2449 }
2450
2451 priv->phydev = phy_connect(ndev, dev_name(&priv->phydev->dev),
2452 &emac_adjust_link, 0, PHY_INTERFACE_MODE_MII);
2453
2454 if (IS_ERR(priv->phydev)) {
2455 printk(KERN_ERR "%s: Could not attach to PHY\n",
2456 ndev->name);
2457 return PTR_ERR(priv->phydev);
2458 }
2459
2460 priv->link = 0;
2461 priv->speed = 0;
2462 priv->duplex = ~0;
2463
2464 printk(KERN_INFO "%s: attached PHY driver [%s] "
2465 "(mii_bus:phy_addr=%s, id=%x)\n", ndev->name,
2466 priv->phydev->drv->name, dev_name(&priv->phydev->dev),
2467 priv->phydev->phy_id);
2468 } else{
2469 /* No PHY , fix the link, speed and duplex settings */
2470 priv->link = 1;
2471 priv->speed = SPEED_100;
2472 priv->duplex = DUPLEX_FULL;
2473 emac_update_phystatus(priv);
2474 }
2475
2476 if (!netif_running(ndev)) /* debug only - to avoid compiler warning */
2477 emac_dump_regs(priv);
2478
2479 if (netif_msg_drv(priv))
2480 dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name);
2481
2482 if (priv->phy_mask)
2483 phy_start(priv->phydev);
2484
2485 return 0;
2486
2487 rollback:
2488
2489 dev_err(emac_dev, "DaVinci EMAC: request_irq() failed");
2490
2491 for (q = k; k >= 0; k--) {
2492 for (m = i; m >= res->start; m--)
2493 free_irq(m, ndev);
2494 res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k-1);
2495 m = res->end;
2496 }
2497 return -EBUSY;
2498 }
2499
2500 /**
2501 * emac_dev_stop: EMAC device stop
2502 * @ndev: The DaVinci EMAC network adapter
2503 *
2504 * Called when system wants to stop or down the interface. We stop the network
2505 * queue, disable interrupts and cleanup TX/RX channels.
2506 *
2507 * We return the statistics in net_device_stats structure pulled from emac
2508 */
2509 static int emac_dev_stop(struct net_device *ndev)
2510 {
2511 struct resource *res;
2512 int i = 0;
2513 int irq_num;
2514 struct emac_priv *priv = netdev_priv(ndev);
2515 struct device *emac_dev = &ndev->dev;
2516
2517 /* inform the upper layers. */
2518 netif_stop_queue(ndev);
2519 napi_disable(&priv->napi);
2520
2521 netif_carrier_off(ndev);
2522 emac_int_disable(priv);
2523 emac_stop_txch(priv, EMAC_DEF_TX_CH);
2524 emac_stop_rxch(priv, EMAC_DEF_RX_CH);
2525 emac_cleanup_txch(priv, EMAC_DEF_TX_CH);
2526 emac_cleanup_rxch(priv, EMAC_DEF_RX_CH);
2527 emac_write(EMAC_SOFTRESET, 1);
2528
2529 if (priv->phydev)
2530 phy_disconnect(priv->phydev);
2531
2532 /* Free IRQ */
2533 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, i))) {
2534 for (irq_num = res->start; irq_num <= res->end; irq_num++)
2535 free_irq(irq_num, priv->ndev);
2536 i++;
2537 }
2538
2539 if (netif_msg_drv(priv))
2540 dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name);
2541
2542 return 0;
2543 }
2544
2545 /**
2546 * emac_dev_getnetstats: EMAC get statistics function
2547 * @ndev: The DaVinci EMAC network adapter
2548 *
2549 * Called when system wants to get statistics from the device.
2550 *
2551 * We return the statistics in net_device_stats structure pulled from emac
2552 */
2553 static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev)
2554 {
2555 struct emac_priv *priv = netdev_priv(ndev);
2556 u32 mac_control;
2557 u32 stats_clear_mask;
2558
2559 /* update emac hardware stats and reset the registers*/
2560
2561 mac_control = emac_read(EMAC_MACCONTROL);
2562
2563 if (mac_control & EMAC_MACCONTROL_GMIIEN)
2564 stats_clear_mask = EMAC_STATS_CLR_MASK;
2565 else
2566 stats_clear_mask = 0;
2567
2568 priv->net_dev_stats.multicast += emac_read(EMAC_RXMCASTFRAMES);
2569 emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask);
2570
2571 priv->net_dev_stats.collisions += (emac_read(EMAC_TXCOLLISION) +
2572 emac_read(EMAC_TXSINGLECOLL) +
2573 emac_read(EMAC_TXMULTICOLL));
2574 emac_write(EMAC_TXCOLLISION, stats_clear_mask);
2575 emac_write(EMAC_TXSINGLECOLL, stats_clear_mask);
2576 emac_write(EMAC_TXMULTICOLL, stats_clear_mask);
2577
2578 priv->net_dev_stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) +
2579 emac_read(EMAC_RXJABBER) +
2580 emac_read(EMAC_RXUNDERSIZED));
2581 emac_write(EMAC_RXOVERSIZED, stats_clear_mask);
2582 emac_write(EMAC_RXJABBER, stats_clear_mask);
2583 emac_write(EMAC_RXUNDERSIZED, stats_clear_mask);
2584
2585 priv->net_dev_stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) +
2586 emac_read(EMAC_RXMOFOVERRUNS));
2587 emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask);
2588 emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask);
2589
2590 priv->net_dev_stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS);
2591 emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask);
2592
2593 priv->net_dev_stats.tx_carrier_errors +=
2594 emac_read(EMAC_TXCARRIERSENSE);
2595 emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask);
2596
2597 priv->net_dev_stats.tx_fifo_errors = emac_read(EMAC_TXUNDERRUN);
2598 emac_write(EMAC_TXUNDERRUN, stats_clear_mask);
2599
2600 return &priv->net_dev_stats;
2601 }
2602
2603 static const struct net_device_ops emac_netdev_ops = {
2604 .ndo_open = emac_dev_open,
2605 .ndo_stop = emac_dev_stop,
2606 .ndo_start_xmit = emac_dev_xmit,
2607 .ndo_set_multicast_list = emac_dev_mcast_set,
2608 .ndo_set_mac_address = emac_dev_setmac_addr,
2609 .ndo_do_ioctl = emac_devioctl,
2610 .ndo_tx_timeout = emac_dev_tx_timeout,
2611 .ndo_get_stats = emac_dev_getnetstats,
2612 #ifdef CONFIG_NET_POLL_CONTROLLER
2613 .ndo_poll_controller = emac_poll_controller,
2614 #endif
2615 };
2616
2617 /**
2618 * davinci_emac_probe: EMAC device probe
2619 * @pdev: The DaVinci EMAC device that we are removing
2620 *
2621 * Called when probing for emac devicesr. We get details of instances and
2622 * resource information from platform init and register a network device
2623 * and allocate resources necessary for driver to perform
2624 */
2625 static int __devinit davinci_emac_probe(struct platform_device *pdev)
2626 {
2627 int rc = 0;
2628 struct resource *res;
2629 struct net_device *ndev;
2630 struct emac_priv *priv;
2631 unsigned long size;
2632 struct emac_platform_data *pdata;
2633 struct device *emac_dev;
2634
2635 /* obtain emac clock from kernel */
2636 emac_clk = clk_get(&pdev->dev, "emac_ck");
2637 if (IS_ERR(emac_clk)) {
2638 printk(KERN_ERR "DaVinci EMAC: Failed to get EMAC clock\n");
2639 return -EBUSY;
2640 }
2641 /* obtain emac phy clock from kernel */
2642 emac_phy_clk = clk_get(&pdev->dev, "emac_phy_ck");
2643 if (IS_ERR(emac_phy_clk)) {
2644 printk(KERN_ERR "DaVinci EMAC: Failed to get EMAC PHY clock\n");
2645 clk_put(emac_clk);
2646 return -EBUSY;
2647 }
2648 emac_bus_frequency = clk_get_rate(emac_clk);
2649 /* TODO: Probe PHY here if possible */
2650
2651 ndev = alloc_etherdev(sizeof(struct emac_priv));
2652 if (!ndev) {
2653 printk(KERN_ERR "DaVinci EMAC: Error allocating net_device\n");
2654 clk_put(emac_clk);
2655 clk_put(emac_phy_clk);
2656 return -ENOMEM;
2657 }
2658
2659 platform_set_drvdata(pdev, ndev);
2660 priv = netdev_priv(ndev);
2661 priv->pdev = pdev;
2662 priv->ndev = ndev;
2663 priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG);
2664
2665 spin_lock_init(&priv->tx_lock);
2666 spin_lock_init(&priv->rx_lock);
2667 spin_lock_init(&priv->lock);
2668
2669 pdata = pdev->dev.platform_data;
2670 if (!pdata) {
2671 printk(KERN_ERR "DaVinci EMAC: No platfrom data\n");
2672 return -ENODEV;
2673 }
2674
2675 /* MAC addr and PHY mask , RMII enable info from platform_data */
2676 memcpy(priv->mac_addr, pdata->mac_addr, 6);
2677 priv->phy_mask = pdata->phy_mask;
2678 priv->rmii_en = pdata->rmii_en;
2679 priv->version = pdata->version;
2680 priv->wrapper_int_enable = pdata->wrapper_interrupt_enable;
2681 priv->wrapper_int_disable = pdata->wrapper_interrupt_disable;
2682
2683 emac_dev = &ndev->dev;
2684 /* Get EMAC platform data */
2685 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2686 if (!res) {
2687 dev_err(emac_dev, "DaVinci EMAC: Error getting res\n");
2688 rc = -ENOENT;
2689 goto probe_quit;
2690 }
2691
2692 priv->emac_base_phys = res->start + pdata->ctrl_reg_offset;
2693 size = res->end - res->start + 1;
2694 if (!request_mem_region(res->start, size, ndev->name)) {
2695 dev_err(emac_dev, "DaVinci EMAC: failed request_mem_region() \
2696 for regs\n");
2697 rc = -ENXIO;
2698 goto probe_quit;
2699 }
2700
2701 priv->remap_addr = ioremap(res->start, size);
2702 if (!priv->remap_addr) {
2703 dev_err(emac_dev, "Unable to map IO\n");
2704 rc = -ENOMEM;
2705 release_mem_region(res->start, size);
2706 goto probe_quit;
2707 }
2708 priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset;
2709 ndev->base_addr = (unsigned long)priv->remap_addr;
2710
2711 priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset;
2712 priv->ctrl_ram_size = pdata->ctrl_ram_size;
2713 priv->emac_ctrl_ram = priv->remap_addr + pdata->ctrl_ram_offset;
2714
2715 if (pdata->hw_ram_addr)
2716 priv->hw_ram_addr = pdata->hw_ram_addr;
2717 else
2718 priv->hw_ram_addr = (u32 __force)res->start +
2719 pdata->ctrl_ram_offset;
2720
2721 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2722 if (!res) {
2723 dev_err(emac_dev, "DaVinci EMAC: Error getting irq res\n");
2724 rc = -ENOENT;
2725 goto no_irq_res;
2726 }
2727 ndev->irq = res->start;
2728
2729 if (!is_valid_ether_addr(priv->mac_addr)) {
2730 /* Use random MAC if none passed */
2731 random_ether_addr(priv->mac_addr);
2732 printk(KERN_WARNING "%s: using random MAC addr: %pM\n",
2733 __func__, priv->mac_addr);
2734 }
2735
2736 ndev->netdev_ops = &emac_netdev_ops;
2737 SET_ETHTOOL_OPS(ndev, &ethtool_ops);
2738 netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT);
2739
2740 clk_enable(emac_clk);
2741 clk_enable(emac_phy_clk);
2742
2743 /* register the network device */
2744 SET_NETDEV_DEV(ndev, &pdev->dev);
2745 rc = register_netdev(ndev);
2746 if (rc) {
2747 dev_err(emac_dev, "DaVinci EMAC: Error in register_netdev\n");
2748 rc = -ENODEV;
2749 goto netdev_reg_err;
2750 }
2751
2752 /* MII/Phy intialisation, mdio bus registration */
2753 emac_mii = mdiobus_alloc();
2754 if (emac_mii == NULL) {
2755 dev_err(emac_dev, "DaVinci EMAC: Error allocating mii_bus\n");
2756 rc = -ENOMEM;
2757 goto mdio_alloc_err;
2758 }
2759
2760 priv->mii_bus = emac_mii;
2761 emac_mii->name = "emac-mii",
2762 emac_mii->read = emac_mii_read,
2763 emac_mii->write = emac_mii_write,
2764 emac_mii->reset = emac_mii_reset,
2765 emac_mii->irq = mii_irqs,
2766 emac_mii->phy_mask = ~(priv->phy_mask);
2767 emac_mii->parent = &pdev->dev;
2768 emac_mii->priv = priv->remap_addr + pdata->mdio_reg_offset;
2769 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%x", priv->pdev->id);
2770 mdio_max_freq = pdata->mdio_max_freq;
2771 emac_mii->reset(emac_mii);
2772
2773 /* Register the MII bus */
2774 rc = mdiobus_register(emac_mii);
2775 if (rc)
2776 goto mdiobus_quit;
2777
2778 if (netif_msg_probe(priv)) {
2779 dev_notice(emac_dev, "DaVinci EMAC Probe found device "\
2780 "(regs: %p, irq: %d)\n",
2781 (void *)priv->emac_base_phys, ndev->irq);
2782 }
2783 return 0;
2784
2785 mdiobus_quit:
2786 mdiobus_free(emac_mii);
2787
2788 netdev_reg_err:
2789 mdio_alloc_err:
2790 no_irq_res:
2791 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2792 release_mem_region(res->start, res->end - res->start + 1);
2793 iounmap(priv->remap_addr);
2794
2795 probe_quit:
2796 clk_put(emac_clk);
2797 clk_put(emac_phy_clk);
2798 free_netdev(ndev);
2799 return rc;
2800 }
2801
2802 /**
2803 * davinci_emac_remove: EMAC device remove
2804 * @pdev: The DaVinci EMAC device that we are removing
2805 *
2806 * Called when removing the device driver. We disable clock usage and release
2807 * the resources taken up by the driver and unregister network device
2808 */
2809 static int __devexit davinci_emac_remove(struct platform_device *pdev)
2810 {
2811 struct resource *res;
2812 struct net_device *ndev = platform_get_drvdata(pdev);
2813 struct emac_priv *priv = netdev_priv(ndev);
2814
2815 dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n");
2816
2817 platform_set_drvdata(pdev, NULL);
2818 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2819 mdiobus_unregister(priv->mii_bus);
2820 mdiobus_free(priv->mii_bus);
2821
2822 release_mem_region(res->start, res->end - res->start + 1);
2823
2824 unregister_netdev(ndev);
2825 free_netdev(ndev);
2826 iounmap(priv->remap_addr);
2827
2828 clk_disable(emac_clk);
2829 clk_disable(emac_phy_clk);
2830 clk_put(emac_clk);
2831 clk_put(emac_phy_clk);
2832
2833 return 0;
2834 }
2835
2836 #ifdef CONFIG_PM
2837 static
2838 int davinci_emac_suspend(struct platform_device *pdev, pm_message_t state)
2839 {
2840 struct net_device *dev = platform_get_drvdata(pdev);
2841
2842 if (netif_running(dev))
2843 emac_dev_stop(dev);
2844
2845 clk_disable(emac_clk);
2846 clk_disable(emac_phy_clk);
2847
2848 return 0;
2849 }
2850
2851 static int davinci_emac_resume(struct platform_device *pdev)
2852 {
2853 struct net_device *dev = platform_get_drvdata(pdev);
2854
2855 clk_enable(emac_phy_clk);
2856
2857 clk_enable(emac_clk);
2858
2859 if (netif_running(dev))
2860 emac_dev_open(dev);
2861
2862 return 0;
2863 }
2864 #else
2865 #define davinci_emac_suspend NULL
2866 #define davinci_emac_resume NULL
2867 #endif
2868
2869 /**
2870 * davinci_emac_driver: EMAC platform driver structure
2871 * Suspend/Resume supported for non-OFF mode use cases
2872 */
2873 static struct platform_driver davinci_emac_driver = {
2874 .driver = {
2875 .name = "davinci_emac",
2876 .owner = THIS_MODULE,
2877 },
2878 .probe = davinci_emac_probe,
2879 .remove = __devexit_p(davinci_emac_remove),
2880 .suspend = davinci_emac_suspend,
2881 .resume = davinci_emac_resume,
2882 };
2883
2884 /**
2885 * davinci_emac_init: EMAC driver module init
2886 *
2887 * Called when initializing the driver. We register the driver with
2888 * the platform.
2889 */
2890 static int __init davinci_emac_init(void)
2891 {
2892 return platform_driver_register(&davinci_emac_driver);
2893 }
2894 late_initcall(davinci_emac_init);
2895
2896 /**
2897 * davinci_emac_exit: EMAC driver module exit
2898 *
2899 * Called when exiting the driver completely. We unregister the driver with
2900 * the platform and exit
2901 */
2902 static void __exit davinci_emac_exit(void)
2903 {
2904 platform_driver_unregister(&davinci_emac_driver);
2905 }
2906 module_exit(davinci_emac_exit);
2907
2908 MODULE_LICENSE("GPL");
2909 MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>");
2910 MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>");
2911 MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver");
Linux for Ginger Game Console