drivers/usb/musb/musb_core.h

   1 /*
   2  * MUSB OTG driver defines
   3  *
   4  * Copyright 2005 Mentor Graphics Corporation
   5  * Copyright (C) 2005-2006 by Texas Instruments
   6  * Copyright (C) 2006-2007 Nokia Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20  * 02110-1301 USA
  21  *
  22  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
  23  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  24  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  25  * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  28  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  29  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  */
  34
  35 #ifndef __MUSB_CORE_H__
  36 #define __MUSB_CORE_H__
  37
  38 #include <linux/slab.h>
  39 #include <linux/list.h>
  40 #include <linux/interrupt.h>
  41 #include <linux/errno.h>
  42 #include <linux/clk.h>
  43 #include <linux/device.h>
  44 #include <linux/usb/ch9.h>
  45 #include <linux/usb/gadget.h>
  46 #include <linux/usb.h>
  47 #include <linux/usb/otg.h>
  48 #include <linux/usb/musb.h>
  49
  50 struct musb;
  51 struct musb_hw_ep;
  52 struct musb_ep;
  53
  54
  55 #include "musb_debug.h"
  56 #include "musb_dma.h"
  57
  58 #include "musb_io.h"
  59 #include "musb_regs.h"
  60
  61 #include "musb_gadget.h"
  62 #include "../core/hcd.h"
  63 #include "musb_host.h"
  64
  65
  66
  67 #ifdef CONFIG_USB_MUSB_OTG
  68
  69 #define is_peripheral_enabled(musb)     ((musb)->board_mode != MUSB_HOST)
  70 #define is_host_enabled(musb)           ((musb)->board_mode != MUSB_PERIPHERAL)
  71 #define is_otg_enabled(musb)            ((musb)->board_mode == MUSB_OTG)
  72
  73 /* NOTE:  otg and peripheral-only state machines start at B_IDLE.
  74  * OTG or host-only go to A_IDLE when ID is sensed.
  75  */
  76 #define is_peripheral_active(m)         (!(m)->is_host)
  77 #define is_host_active(m)               ((m)->is_host)
  78
  79 #else
  80 #define is_peripheral_enabled(musb)     is_peripheral_capable()
  81 #define is_host_enabled(musb)           is_host_capable()
  82 #define is_otg_enabled(musb)            0
  83
  84 #define is_peripheral_active(musb)      is_peripheral_capable()
  85 #define is_host_active(musb)            is_host_capable()
  86 #endif
  87
  88 #if defined(CONFIG_USB_MUSB_OTG) || defined(CONFIG_USB_MUSB_PERIPHERAL)
  89 /* for some reason, the "select USB_GADGET_MUSB_HDRC" doesn't always
  90  * override that choice selection (often USB_GADGET_DUMMY_HCD).
  91  */
  92 #ifndef CONFIG_USB_GADGET_MUSB_HDRC
  93 #error bogus Kconfig output ... select CONFIG_USB_GADGET_MUSB_HDRC
  94 #endif
  95 #endif  /* need MUSB gadget selection */
  96
  97 #ifndef CONFIG_HAVE_CLK
  98 /* Dummy stub for clk framework */
  99 #define clk_get(dev, id)        NULL
 100 #define clk_put(clock)          do {} while (0)
 101 #define clk_enable(clock)       do {} while (0)
 102 #define clk_disable(clock)      do {} while (0)
 103 #endif
 104
 105 #ifdef CONFIG_PROC_FS
 106 #include <linux/fs.h>
 107 #define MUSB_CONFIG_PROC_FS
 108 #endif
 109
 110 /****************************** PERIPHERAL ROLE *****************************/
 111
 112 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
 113
 114 #define is_peripheral_capable() (1)
 115
 116 extern irqreturn_t musb_g_ep0_irq(struct musb *);
 117 extern void musb_g_tx(struct musb *, u8);
 118 extern void musb_g_rx(struct musb *, u8);
 119 extern void musb_g_reset(struct musb *);
 120 extern void musb_g_suspend(struct musb *);
 121 extern void musb_g_resume(struct musb *);
 122 extern void musb_g_wakeup(struct musb *);
 123 extern void musb_g_disconnect(struct musb *);
 124
 125 #else
 126
 127 #define is_peripheral_capable() (0)
 128
 129 static inline irqreturn_t musb_g_ep0_irq(struct musb *m) { return IRQ_NONE; }
 130 static inline void musb_g_reset(struct musb *m) {}
 131 static inline void musb_g_suspend(struct musb *m) {}
 132 static inline void musb_g_resume(struct musb *m) {}
 133 static inline void musb_g_wakeup(struct musb *m) {}
 134 static inline void musb_g_disconnect(struct musb *m) {}
 135
 136 #endif
 137
 138 /****************************** HOST ROLE ***********************************/
 139
 140 #ifdef CONFIG_USB_MUSB_HDRC_HCD
 141
 142 #define is_host_capable()       (1)
 143
 144 extern irqreturn_t musb_h_ep0_irq(struct musb *);
 145 extern void musb_host_tx(struct musb *, u8);
 146 extern void musb_host_rx(struct musb *, u8);
 147
 148 #else
 149
 150 #define is_host_capable()       (0)
 151
 152 static inline irqreturn_t musb_h_ep0_irq(struct musb *m) { return IRQ_NONE; }
 153 static inline void musb_host_tx(struct musb *m, u8 e) {}
 154 static inline void musb_host_rx(struct musb *m, u8 e) {}
 155
 156 #endif
 157
 158
 159 /****************************** CONSTANTS ********************************/
 160
 161 #ifndef MUSB_C_NUM_EPS
 162 #define MUSB_C_NUM_EPS ((u8)16)
 163 #endif
 164
 165 #ifndef MUSB_MAX_END0_PACKET
 166 #define MUSB_MAX_END0_PACKET ((u16)MUSB_EP0_FIFOSIZE)
 167 #endif
 168
 169 /* host side ep0 states */
 170 enum musb_h_ep0_state {
 171         MUSB_EP0_IDLE,
 172         MUSB_EP0_START,                 /* expect ack of setup */
 173         MUSB_EP0_IN,                    /* expect IN DATA */
 174         MUSB_EP0_OUT,                   /* expect ack of OUT DATA */
 175         MUSB_EP0_STATUS,                /* expect ack of STATUS */
 176 } __attribute__ ((packed));
 177
 178 /* peripheral side ep0 states */
 179 enum musb_g_ep0_state {
 180         MUSB_EP0_STAGE_IDLE,            /* idle, waiting for SETUP */
 181         MUSB_EP0_STAGE_SETUP,           /* received SETUP */
 182         MUSB_EP0_STAGE_TX,              /* IN data */
 183         MUSB_EP0_STAGE_RX,              /* OUT data */
 184         MUSB_EP0_STAGE_STATUSIN,        /* (after OUT data) */
 185         MUSB_EP0_STAGE_STATUSOUT,       /* (after IN data) */
 186         MUSB_EP0_STAGE_ACKWAIT,         /* after zlp, before statusin */
 187 } __attribute__ ((packed));
 188
 189 /* OTG protocol constants */
 190 #define OTG_TIME_A_WAIT_VRISE   100             /* msec (max) */
 191 #define OTG_TIME_A_WAIT_BCON    0               /* 0=infinite; min 1000 msec */
 192 #define OTG_TIME_A_IDLE_BDIS    200             /* msec (min) */
 193
 194 /*************************** REGISTER ACCESS ********************************/
 195
 196 /* Endpoint registers (other than dynfifo setup) can be accessed either
 197  * directly with the "flat" model, or after setting up an index register.
 198  */
 199
 200 #if defined(CONFIG_ARCH_DAVINCI) || defined(CONFIG_ARCH_OMAP2430) \
 201                 || defined(CONFIG_ARCH_OMAP3430) || defined(CONFIG_BLACKFIN)
 202 /* REVISIT indexed access seemed to
 203  * misbehave (on DaVinci) for at least peripheral IN ...
 204  */
 205 #define MUSB_FLAT_REG
 206 #endif
 207
 208 /* TUSB mapping: "flat" plus ep0 special cases */
 209 #if     defined(CONFIG_USB_TUSB6010)
 210 #define musb_ep_select(_mbase, _epnum) \
 211         musb_writeb((_mbase), MUSB_INDEX, (_epnum))
 212 #define MUSB_EP_OFFSET                  MUSB_TUSB_OFFSET
 213
 214 /* "flat" mapping: each endpoint has its own i/o address */
 215 #elif   defined(MUSB_FLAT_REG)
 216 #define musb_ep_select(_mbase, _epnum)  (((void)(_mbase)), ((void)(_epnum)))
 217 #define MUSB_EP_OFFSET                  MUSB_FLAT_OFFSET
 218
 219 /* "indexed" mapping: INDEX register controls register bank select */
 220 #else
 221 #define musb_ep_select(_mbase, _epnum) \
 222         musb_writeb((_mbase), MUSB_INDEX, (_epnum))
 223 #define MUSB_EP_OFFSET                  MUSB_INDEXED_OFFSET
 224 #endif
 225
 226 /****************************** FUNCTIONS ********************************/
 227
 228 #define MUSB_HST_MODE(_musb)\
 229         { (_musb)->is_host = true; }
 230 #define MUSB_DEV_MODE(_musb) \
 231         { (_musb)->is_host = false; }
 232
 233 #define test_devctl_hst_mode(_x) \
 234         (musb_readb((_x)->mregs, MUSB_DEVCTL)&MUSB_DEVCTL_HM)
 235
 236 #define MUSB_MODE(musb) ((musb)->is_host ? "Host" : "Peripheral")
 237
 238 /******************************** TYPES *************************************/
 239
 240 /*
 241  * struct musb_hw_ep - endpoint hardware (bidirectional)
 242  *
 243  * Ordered slightly for better cacheline locality.
 244  */
 245 struct musb_hw_ep {
 246         struct musb             *musb;
 247         void __iomem            *fifo;
 248         void __iomem            *regs;
 249
 250 #ifdef CONFIG_USB_TUSB6010
 251         void __iomem            *conf;
 252 #endif
 253
 254         /* index in musb->endpoints[]  */
 255         u8                      epnum;
 256
 257         /* hardware configuration, possibly dynamic */
 258         bool                    is_shared_fifo;
 259         bool                    tx_double_buffered;
 260         bool                    rx_double_buffered;
 261         u16                     max_packet_sz_tx;
 262         u16                     max_packet_sz_rx;
 263
 264         struct dma_channel      *tx_channel;
 265         struct dma_channel      *rx_channel;
 266
 267 #ifdef CONFIG_USB_TUSB6010
 268         /* TUSB has "asynchronous" and "synchronous" dma modes */
 269         dma_addr_t              fifo_async;
 270         dma_addr_t              fifo_sync;
 271         void __iomem            *fifo_sync_va;
 272 #endif
 273
 274 #ifdef CONFIG_USB_MUSB_HDRC_HCD
 275         void __iomem            *target_regs;
 276
 277         /* currently scheduled peripheral endpoint */
 278         struct musb_qh          *in_qh;
 279         struct musb_qh          *out_qh;
 280
 281         u8                      rx_reinit;
 282         u8                      tx_reinit;
 283 #endif
 284
 285 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
 286         /* peripheral side */
 287         struct musb_ep          ep_in;                  /* TX */
 288         struct musb_ep          ep_out;                 /* RX */
 289 #endif
 290 };
 291
 292 static inline struct usb_request *next_in_request(struct musb_hw_ep *hw_ep)
 293 {
 294 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
 295         return next_request(&hw_ep->ep_in);
 296 #else
 297         return NULL;
 298 #endif
 299 }
 300
 301 static inline struct usb_request *next_out_request(struct musb_hw_ep *hw_ep)
 302 {
 303 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
 304         return next_request(&hw_ep->ep_out);
 305 #else
 306         return NULL;
 307 #endif
 308 }
 309
 310 /*
 311  * struct musb - Driver instance data.
 312  */
 313 struct musb {
 314         /* device lock */
 315         spinlock_t              lock;
 316         struct clk              *clock;
 317         irqreturn_t             (*isr)(int, void *);
 318         struct work_struct      irq_work;
 319
 320 /* this hub status bit is reserved by USB 2.0 and not seen by usbcore */
 321 #define MUSB_PORT_STAT_RESUME   (1 << 31)
 322
 323         u32                     port1_status;
 324
 325 #ifdef CONFIG_USB_MUSB_HDRC_HCD
 326         unsigned long           rh_timer;
 327
 328         enum musb_h_ep0_state   ep0_stage;
 329
 330         /* bulk traffic normally dedicates endpoint hardware, and each
 331          * direction has its own ring of host side endpoints.
 332          * we try to progress the transfer at the head of each endpoint's
 333          * queue until it completes or NAKs too much; then we try the next
 334          * endpoint.
 335          */
 336         struct musb_hw_ep       *bulk_ep;
 337
 338         struct list_head        control;        /* of musb_qh */
 339         struct list_head        in_bulk;        /* of musb_qh */
 340         struct list_head        out_bulk;       /* of musb_qh */
 341 #endif
 342
 343         /* called with IRQs blocked; ON/nonzero implies starting a session,
 344          * and waiting at least a_wait_vrise_tmout.
 345          */
 346         void                    (*board_set_vbus)(struct musb *, int is_on);
 347
 348         struct dma_controller   *dma_controller;
 349
 350         struct device           *controller;
 351         void __iomem            *ctrl_base;
 352         void __iomem            *mregs;
 353
 354 #ifdef CONFIG_USB_TUSB6010
 355         dma_addr_t              async;
 356         dma_addr_t              sync;
 357         void __iomem            *sync_va;
 358 #endif
 359
 360 #ifdef CONFIG_MACH_OMAP3517EVM
 361 /* Backup registers required for the workaround of AM3517 bytewise
 362  * read issue. FADDR, POWER, INTRTXE, INTRRXE and INTRUSBE register
 363  * read would actually clear the interrupt registers and would cause
 364  * missing interrupt event.
 365  * Only POWER register has a few read-only bits and other registers
 366  * are programmed by software so any read to them would get the last
 367  * written data dave in below registers.Even for POWER registers
 368  * we need to read actual registers only at few places where we want
 369  * to know the status of read-only bits.
 370  */
 371 #define AM3517_READ_ISSUE_FADDR         BIT(0)
 372 #define AM3517_READ_ISSUE_POWER         BIT(1)
 373 #define AM3517_READ_ISSUE_INTRTXE       BIT(2)
 374 #define AM3517_READ_ISSUE_INTRRXE       BIT(3)
 375 #define AM3517_READ_ISSUE_INTRUSBE      BIT(4)
 376         u8                      read_mask;
 377         u8                      faddr;
 378         u8                      power;
 379         u16                     intrtxe;
 380         u16                     intrrxe;
 381         u8                      intrusbe;
 382 #endif
 383         /* passed down from chip/board specific irq handlers */
 384         u8                      int_usb;
 385         u16                     int_rx;
 386         u16                     int_tx;
 387
 388         struct otg_transceiver  *xceiv;
 389
 390         int nIrq;
 391         unsigned                irq_wake:1;
 392
 393         struct musb_hw_ep        endpoints[MUSB_C_NUM_EPS];
 394 #define control_ep              endpoints
 395
 396 #define VBUSERR_RETRY_COUNT     3
 397         u16                     vbuserr_retry;
 398         u16 epmask;
 399         u8 nr_endpoints;
 400
 401         u8 board_mode;          /* enum musb_mode */
 402         int                     (*board_set_power)(int state);
 403
 404         int                     (*set_clock)(struct clk *clk, int is_active);
 405
 406         u8                      min_power;      /* vbus for periph, in mA/2 */
 407
 408         bool                    is_host;
 409
 410         int                     a_wait_bcon;    /* VBUS timeout in msecs */
 411         unsigned long           idle_timeout;   /* Next timeout in jiffies */
 412
 413         /* active means connected and not suspended */
 414         unsigned                is_active:1;
 415
 416         unsigned is_multipoint:1;
 417         unsigned ignore_disconnect:1;   /* during bus resets */
 418
 419         unsigned                hb_iso_rx:1;    /* high bandwidth iso rx? */
 420         unsigned                hb_iso_tx:1;    /* high bandwidth iso tx? */
 421
 422 #ifdef C_MP_TX
 423         unsigned bulk_split:1;
 424 #define can_bulk_split(musb,type) \
 425                 (((type) == USB_ENDPOINT_XFER_BULK) && (musb)->bulk_split)
 426 #else
 427 #define can_bulk_split(musb, type)      0
 428 #endif
 429
 430 #ifdef C_MP_RX
 431         unsigned bulk_combine:1;
 432 #define can_bulk_combine(musb,type) \
 433                 (((type) == USB_ENDPOINT_XFER_BULK) && (musb)->bulk_combine)
 434 #else
 435 #define can_bulk_combine(musb, type)    0
 436 #endif
 437
 438 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
 439         /* is_suspended means USB B_PERIPHERAL suspend */
 440         unsigned                is_suspended:1;
 441
 442         /* may_wakeup means remote wakeup is enabled */
 443         unsigned                may_wakeup:1;
 444
 445         /* is_self_powered is reported in device status and the
 446          * config descriptor.  is_bus_powered means B_PERIPHERAL
 447          * draws some VBUS current; both can be true.
 448          */
 449         unsigned                is_self_powered:1;
 450         unsigned                is_bus_powered:1;
 451
 452         unsigned                set_address:1;
 453         unsigned                test_mode:1;
 454         unsigned                softconnect:1;
 455
 456         u8                      address;
 457         u8                      test_mode_nr;
 458         u16                     ackpend;                /* ep0 */
 459         enum musb_g_ep0_state   ep0_state;
 460         struct usb_gadget       g;                      /* the gadget */
 461         struct usb_gadget_driver *gadget_driver;        /* its driver */
 462 #endif
 463
 464         struct musb_hdrc_config *config;
 465
 466 #ifdef MUSB_CONFIG_PROC_FS
 467         struct proc_dir_entry *proc_entry;
 468 #endif
 469 };
 470
 471 #ifdef CONFIG_PM
 472 struct musb_csr_regs {
 473         /* FIFO registers */
 474         u16 txmaxp, txcsr, rxmaxp, rxcsr, rxcount;
 475         u16 rxfifoadd, txfifoadd;
 476         u8 txtype, txinterval, rxtype, rxinterval;
 477         u8 rxfifosz, txfifosz;
 478         u8 txfunaddr, txhubaddr, txhubport;
 479         u8 rxfunaddr, rxhubaddr, rxhubport;
 480 };
 481
 482 struct musb_context_registers {
 483
 484 #if defined(CONFIG_ARCH_OMAP34XX)
 485         u32 otg_sysconfig, otg_forcestandby;
 486 #endif
 487         u8 faddr, power;
 488         u16 intrtx, intrrx, intrtxe, intrrxe;
 489         u8 intrusb, intrusbe;
 490         u16 frame;
 491         u8 index, testmode;
 492
 493         u8 devctl, misc;
 494
 495         struct musb_csr_regs index_regs[MUSB_C_NUM_EPS];
 496 };
 497
 498 #if defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP2430)
 499 extern void musb_platform_save_context(struct musb_context_registers
 500                 *musb_context);
 501 extern void musb_platform_restore_context(struct musb_context_registers
 502                 *musb_context);
 503 #else
 504 #define musb_platform_save_context(x)           do {} while (0)
 505 #define musb_platform_restore_context(x)        do {} while (0)
 506 #endif
 507
 508 #endif
 509
 510 static inline void musb_set_vbus(struct musb *musb, int is_on)
 511 {
 512         musb->board_set_vbus(musb, is_on);
 513 }
 514
 515 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
 516 static inline struct musb *gadget_to_musb(struct usb_gadget *g)
 517 {
 518         return container_of(g, struct musb, g);
 519 }
 520 #endif
 521
 522 #ifdef CONFIG_BLACKFIN
 523 static inline int musb_read_fifosize(struct musb *musb,
 524                 struct musb_hw_ep *hw_ep, u8 epnum)
 525 {
 526         musb->nr_endpoints++;
 527         musb->epmask |= (1 << epnum);
 528
 529         if (epnum < 5) {
 530                 hw_ep->max_packet_sz_tx = 128;
 531                 hw_ep->max_packet_sz_rx = 128;
 532         } else {
 533                 hw_ep->max_packet_sz_tx = 1024;
 534                 hw_ep->max_packet_sz_rx = 1024;
 535         }
 536         hw_ep->is_shared_fifo = false;
 537
 538         return 0;
 539 }
 540
 541 static inline void musb_configure_ep0(struct musb *musb)
 542 {
 543         musb->endpoints[0].max_packet_sz_tx = MUSB_EP0_FIFOSIZE;
 544         musb->endpoints[0].max_packet_sz_rx = MUSB_EP0_FIFOSIZE;
 545         musb->endpoints[0].is_shared_fifo = true;
 546 }
 547
 548 #else
 549
 550 static inline int musb_read_fifosize(struct musb *musb,
 551                 struct musb_hw_ep *hw_ep, u8 epnum)
 552 {
 553         void *mbase = musb->mregs;
 554         u8 reg = 0;
 555
 556         /* read from core using indexed model */
 557         reg = musb_readb(mbase, MUSB_EP_OFFSET(epnum, MUSB_FIFOSIZE));
 558         /* 0's returned when no more endpoints */
 559         if (!reg)
 560                 return -ENODEV;
 561
 562         musb->nr_endpoints++;
 563         musb->epmask |= (1 << epnum);
 564
 565         hw_ep->max_packet_sz_tx = 1 << (reg & 0x0f);
 566
 567         /* shared TX/RX FIFO? */
 568         if ((reg & 0xf0) == 0xf0) {
 569                 hw_ep->max_packet_sz_rx = hw_ep->max_packet_sz_tx;
 570                 hw_ep->is_shared_fifo = true;
 571                 return 0;
 572         } else {
 573                 hw_ep->max_packet_sz_rx = 1 << ((reg & 0xf0) >> 4);
 574                 hw_ep->is_shared_fifo = false;
 575         }
 576
 577         return 0;
 578 }
 579
 580 static inline void musb_configure_ep0(struct musb *musb)
 581 {
 582         musb->endpoints[0].max_packet_sz_tx = MUSB_EP0_FIFOSIZE;
 583         musb->endpoints[0].max_packet_sz_rx = MUSB_EP0_FIFOSIZE;
 584         musb->endpoints[0].is_shared_fifo = true;
 585 }
 586 #endif /* CONFIG_BLACKFIN */
 587
 588
 589 /***************************** Glue it together *****************************/
 590
 591 extern const char musb_driver_name[];
 592
 593 extern void musb_start(struct musb *musb);
 594 extern void musb_stop(struct musb *musb);
 595
 596 extern void musb_write_fifo(struct musb_hw_ep *ep, u16 len, const u8 *src);
 597 extern void musb_read_fifo(struct musb_hw_ep *ep, u16 len, u8 *dst);
 598
 599 extern void musb_load_testpacket(struct musb *);
 600
 601 extern irqreturn_t musb_interrupt(struct musb *);
 602
 603 extern void musb_platform_enable(struct musb *musb);
 604 extern void musb_platform_disable(struct musb *musb);
 605
 606 extern void musb_hnp_stop(struct musb *musb);
 607
 608 extern int musb_platform_set_mode(struct musb *musb, u8 musb_mode);
 609
 610 #if defined(CONFIG_USB_TUSB6010) || defined(CONFIG_BLACKFIN) || \
 611         defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
 612 extern void musb_platform_try_idle(struct musb *musb, unsigned long timeout);
 613 #else
 614 #define musb_platform_try_idle(x, y)            do {} while (0)
 615 #endif
 616
 617 #if defined(CONFIG_USB_TUSB6010) || defined(CONFIG_BLACKFIN)
 618 extern int musb_platform_get_vbus_status(struct musb *musb);
 619 #else
 620 #define musb_platform_get_vbus_status(x)        0
 621 #endif
 622
 623 extern int __init musb_platform_init(struct musb *musb);
 624 extern int musb_platform_exit(struct musb *musb);
 625
 626 /*-------------------------- ProcFS definitions ---------------------*/
 627
 628 struct proc_dir_entry;
 629
 630 #if defined(CONFIG_USB_MUSB_DEBUG) && defined(MUSB_CONFIG_PROC_FS)
 631 extern struct proc_dir_entry *musb_debug_create(char *name, struct musb *data);
 632 extern void musb_debug_delete(char *name, struct musb *data);
 633
 634 #else
 635 static inline struct proc_dir_entry *
 636 musb_debug_create(char *name, struct musb *data)
 637 {
 638         return NULL;
 639 }
 640 static inline void musb_debug_delete(char *name, struct musb *data)
 641 {
 642 }
 643 #endif
 644
 645 #endif  /* __MUSB_CORE_H__ */