drivers/usb/musb/musbhsdma.h

   1 /*
   2  * MUSB OTG driver - support for Mentor's DMA controller
   3  *
   4  * Copyright 2005 Mentor Graphics Corporation
   5  * Copyright (C) 2005-2007 by Texas Instruments
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * version 2 as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  19  * 02110-1301 USA
  20  *
  21  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
  22  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  23  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  24  * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  27  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  28  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  *
  32  */
  33
  34 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
  35 #include "omap2430.h"
  36 #endif
  37
  38 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
  39 #include "omap2430.h"
  40 #endif
  41
  42 #ifdef CONFIG_MUSB_USE_SYSTEM_DMA_RX
  43 static int use_sdma = 1;
  44 #else
  45 #define use_sdma          0
  46 #endif
  47
  48 int use_system_dma(void)
  49 {
  50         return use_sdma;
  51 }
  52
  53 #ifndef CONFIG_BLACKFIN
  54
  55 #define MUSB_HSDMA_BASE         0x200
  56 #define MUSB_HSDMA_INTR         (MUSB_HSDMA_BASE + 0)
  57 #define MUSB_HSDMA_CONTROL              0x4
  58 #define MUSB_HSDMA_ADDRESS              0x8
  59 #define MUSB_HSDMA_COUNT                0xc
  60
  61 #define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset)           \
  62                 (MUSB_HSDMA_BASE + (_bchannel << 4) + _offset)
  63
  64 #define musb_read_hsdma_addr(mbase, bchannel)   \
  65         musb_readl(mbase,       \
  66                    MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS))
  67
  68 #define musb_write_hsdma_addr(mbase, bchannel, addr) \
  69         musb_writel(mbase, \
  70                     MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS), \
  71                     addr)
  72
  73 #define musb_write_hsdma_count(mbase, bchannel, len) \
  74         musb_writel(mbase, \
  75                     MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT), \
  76                     len)
  77 #else
  78
  79 #define MUSB_HSDMA_BASE         0x400
  80 #define MUSB_HSDMA_INTR         (MUSB_HSDMA_BASE + 0)
  81 #define MUSB_HSDMA_CONTROL              0x04
  82 #define MUSB_HSDMA_ADDR_LOW             0x08
  83 #define MUSB_HSDMA_ADDR_HIGH            0x0C
  84 #define MUSB_HSDMA_COUNT_LOW            0x10
  85 #define MUSB_HSDMA_COUNT_HIGH           0x14
  86
  87 #define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset)           \
  88                 (MUSB_HSDMA_BASE + (_bchannel * 0x20) + _offset)
  89
  90 static inline u32 musb_read_hsdma_addr(void __iomem *mbase, u8 bchannel)
  91 {
  92         u32 addr = musb_readw(mbase,
  93                 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_HIGH));
  94
  95         addr = addr << 16;
  96
  97         addr |= musb_readw(mbase,
  98                 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_LOW));
  99
 100         return addr;
 101 }
 102
 103 static inline void musb_write_hsdma_addr(void __iomem *mbase,
 104                                 u8 bchannel, dma_addr_t dma_addr)
 105 {
 106         musb_writew(mbase,
 107                 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_LOW),
 108                 ((u16)((u32) dma_addr & 0xFFFF)));
 109         musb_writew(mbase,
 110                 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_HIGH),
 111                 ((u16)(((u32) dma_addr >> 16) & 0xFFFF)));
 112 }
 113
 114 static inline void musb_write_hsdma_count(void __iomem *mbase,
 115                                 u8 bchannel, u32 len)
 116 {
 117         musb_writew(mbase,
 118                 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_LOW),
 119                 ((u16)((u32) len & 0xFFFF)));
 120         musb_writew(mbase,
 121                 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_HIGH),
 122                 ((u16)(((u32) len >> 16) & 0xFFFF)));
 123 }
 124
 125 #endif /* CONFIG_BLACKFIN */
 126
 127 /* control register (16-bit): */
 128 #define MUSB_HSDMA_ENABLE_SHIFT         0
 129 #define MUSB_HSDMA_TRANSMIT_SHIFT       1
 130 #define MUSB_HSDMA_MODE1_SHIFT          2
 131 #define MUSB_HSDMA_IRQENABLE_SHIFT      3
 132 #define MUSB_HSDMA_ENDPOINT_SHIFT       4
 133 #define MUSB_HSDMA_BUSERROR_SHIFT       8
 134 #define MUSB_HSDMA_BURSTMODE_SHIFT      9
 135 #define MUSB_HSDMA_BURSTMODE            (3 << MUSB_HSDMA_BURSTMODE_SHIFT)
 136 #define MUSB_HSDMA_BURSTMODE_UNSPEC     0
 137 #define MUSB_HSDMA_BURSTMODE_INCR4      1
 138 #define MUSB_HSDMA_BURSTMODE_INCR8      2
 139 #define MUSB_HSDMA_BURSTMODE_INCR16     3
 140
 141 #define MUSB_HSDMA_CHANNELS             8
 142
 143 #define MUSB_FIFO_ADDRESS(epnum)      \
 144         ((unsigned long) (OMAP_HSOTG_BASE + MUSB_FIFO_OFFSET(epnum)))
 145
 146 struct musb_dma_controller;
 147
 148 struct musb_dma_channel {
 149         struct dma_channel              channel;
 150         struct musb_dma_controller      *controller;
 151         u32                             start_addr;
 152         u32                             len;
 153         u16                             max_packet_sz;
 154         u8                              idx;
 155         u8                              epnum;
 156         u8                              transmit;
 157         int                             sysdma_channel;
 158 };
 159
 160 struct musb_dma_controller {
 161         struct dma_controller           controller;
 162         struct musb_dma_channel         channel[MUSB_HSDMA_CHANNELS];
 163         void                            *private_data;
 164         void __iomem                    *base;
 165         u8                              channel_count;
 166         u8                              used_channels;
 167         u8                              irq;
 168 };