arch/alpha/include/asm/core_polaris.h

   1 #ifndef __ALPHA_POLARIS__H__
   2 #define __ALPHA_POLARIS__H__
   3
   4 #include <linux/types.h>
   5 #include <asm/compiler.h>
   6
   7 /*
   8  * POLARIS is the internal name for a core logic chipset which provides
   9  * memory controller and PCI access for the 21164PC chip based systems.
  10  *
  11  * This file is based on:
  12  *
  13  * Polaris System Controller
  14  * Device Functional Specification
  15  * 22-Jan-98
  16  * Rev. 4.2
  17  *
  18  */
  19
  20 /* Polaris memory regions */
  21 #define POLARIS_SPARSE_MEM_BASE         (IDENT_ADDR + 0xf800000000UL)
  22 #define POLARIS_DENSE_MEM_BASE          (IDENT_ADDR + 0xf900000000UL)
  23 #define POLARIS_SPARSE_IO_BASE          (IDENT_ADDR + 0xf980000000UL)
  24 #define POLARIS_SPARSE_CONFIG_BASE      (IDENT_ADDR + 0xf9c0000000UL)
  25 #define POLARIS_IACK_BASE               (IDENT_ADDR + 0xf9f8000000UL)
  26 #define POLARIS_DENSE_IO_BASE           (IDENT_ADDR + 0xf9fc000000UL)
  27 #define POLARIS_DENSE_CONFIG_BASE       (IDENT_ADDR + 0xf9fe000000UL)
  28
  29 #define POLARIS_IACK_SC                 POLARIS_IACK_BASE
  30
  31 /* The Polaris command/status registers live in PCI Config space for
  32  * bus 0/device 0.  As such, they may be bytes, words, or doublewords.
  33  */
  34 #define POLARIS_W_VENID         (POLARIS_DENSE_CONFIG_BASE)
  35 #define POLARIS_W_DEVID         (POLARIS_DENSE_CONFIG_BASE+2)
  36 #define POLARIS_W_CMD           (POLARIS_DENSE_CONFIG_BASE+4)
  37 #define POLARIS_W_STATUS        (POLARIS_DENSE_CONFIG_BASE+6)
  38
  39 /*
  40  * Data structure for handling POLARIS machine checks:
  41  */
  42 struct el_POLARIS_sysdata_mcheck {
  43     u_long      psc_status;
  44     u_long      psc_pcictl0;
  45     u_long      psc_pcictl1;
  46     u_long      psc_pcictl2;
  47 };
  48
  49 #ifdef __KERNEL__
  50
  51 #ifndef __EXTERN_INLINE
  52 #define __EXTERN_INLINE extern inline
  53 #define __IO_EXTERN_INLINE
  54 #endif
  55
  56 /*
  57  * I/O functions:
  58  *
  59  * POLARIS, the PCI/memory support chipset for the PCA56 (21164PC)
  60  * processors, can use either a sparse address  mapping scheme, or the
  61  * so-called byte-word PCI address space, to get at PCI memory and I/O.
  62  *
  63  * However, we will support only the BWX form.
  64  */
  65
  66 /*
  67  * Memory functions.  Polaris allows all accesses (byte/word
  68  * as well as long/quad) to be done through dense space.
  69  *
  70  * We will only support DENSE access via BWX insns.
  71  */
  72
  73 __EXTERN_INLINE void __iomem *polaris_ioportmap(unsigned long addr)
  74 {
  75         return (void __iomem *)(addr + POLARIS_DENSE_IO_BASE);
  76 }
  77
  78 __EXTERN_INLINE void __iomem *polaris_ioremap(unsigned long addr,
  79                                               unsigned long size)
  80 {
  81         return (void __iomem *)(addr + POLARIS_DENSE_MEM_BASE);
  82 }
  83
  84 __EXTERN_INLINE int polaris_is_ioaddr(unsigned long addr)
  85 {
  86         return addr >= POLARIS_SPARSE_MEM_BASE;
  87 }
  88
  89 __EXTERN_INLINE int polaris_is_mmio(const volatile void __iomem *addr)
  90 {
  91         return (unsigned long)addr < POLARIS_SPARSE_IO_BASE;
  92 }
  93
  94 #undef __IO_PREFIX
  95 #define __IO_PREFIX             polaris
  96 #define polaris_trivial_rw_bw   1
  97 #define polaris_trivial_rw_lq   1
  98 #define polaris_trivial_io_bw   1
  99 #define polaris_trivial_io_lq   1
 100 #define polaris_trivial_iounmap 1
 101 #include <asm/io_trivial.h>
 102
 103 #ifdef __IO_EXTERN_INLINE
 104 #undef __EXTERN_INLINE
 105 #undef __IO_EXTERN_INLINE
 106 #endif
 107
 108 #endif /* __KERNEL__ */
 109
 110 #endif /* __ALPHA_POLARIS__H__ */