| blob | 322410be573ca027bd8e03da67e134492423974d |
1 /*
2 * linux/arch/arm/kernel/entry-armv.S
3 *
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Low-level vector interface routines
13 *
14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction
15 * that causes it to save wrong values... Be aware!
16 */
18 #include <asm/memory.h>
19 #include <asm/glue.h>
20 #include <asm/vfpmacros.h>
21 #include <mach/entry-macro.S>
22 #include <asm/thread_notify.h>
23 #include <asm/unwind.h>
25 #include "entry-header.S"
27 /*
28 * Interrupt handling. Preserves r7, r8, r9
29 */
30 .macro irq_handler
31 get_irqnr_preamble r5, lr
32 1: get_irqnr_and_base r0, r6, r5, lr
33 movne r1, sp
34 @
35 @ routine called with r0 = irq number, r1 = struct pt_regs *
36 @
37 adrne lr, BSYM(1b)
38 bne asm_do_IRQ
40 #ifdef CONFIG_SMP
41 /*
42 * XXX
43 *
44 * this macro assumes that irqstat (r6) and base (r5) are
45 * preserved from get_irqnr_and_base above
46 */
47 test_for_ipi r0, r6, r5, lr
48 movne r0, sp
49 adrne lr, BSYM(1b)
50 bne do_IPI
52 #ifdef CONFIG_LOCAL_TIMERS
53 test_for_ltirq r0, r6, r5, lr
54 movne r0, sp
55 adrne lr, BSYM(1b)
56 bne do_local_timer
57 #endif
58 #endif
60 .endm
62 #ifdef CONFIG_KPROBES
63 .section .kprobes.text,"ax",%progbits
64 #else
65 .text
66 #endif
68 /*
69 * Invalid mode handlers
70 */
71 .macro inv_entry, reason
72 sub sp, sp, #S_FRAME_SIZE
73 ARM( stmib sp, {r1 - lr} )
74 THUMB( stmia sp, {r0 - r12} )
75 THUMB( str sp, [sp, #S_SP] )
76 THUMB( str lr, [sp, #S_LR] )
77 mov r1, #\reason
78 .endm
80 __pabt_invalid:
81 inv_entry BAD_PREFETCH
82 b common_invalid
83 ENDPROC(__pabt_invalid)
85 __dabt_invalid:
86 inv_entry BAD_DATA
87 b common_invalid
88 ENDPROC(__dabt_invalid)
90 __irq_invalid:
91 inv_entry BAD_IRQ
92 b common_invalid
93 ENDPROC(__irq_invalid)
95 __und_invalid:
96 inv_entry BAD_UNDEFINSTR
98 @
99 @ XXX fall through to common_invalid
100 @
102 @
103 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
104 @
105 common_invalid:
106 zero_fp
108 ldmia r0, {r4 - r6}
109 add r0, sp, #S_PC @ here for interlock avoidance
110 mov r7, #-1 @ "" "" "" ""
111 str r4, [sp] @ save preserved r0
112 stmia r0, {r5 - r7} @ lr_<exception>,
113 @ cpsr_<exception>, "old_r0"
115 mov r0, sp
116 b bad_mode
117 ENDPROC(__und_invalid)
119 /*
120 * SVC mode handlers
121 */
123 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
124 #define SPFIX(code...) code
125 #else
126 #define SPFIX(code...)
127 #endif
129 .macro svc_entry, stack_hole=0
130 UNWIND(.fnstart )
131 UNWIND(.save {r0 - pc} )
132 sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4)
133 #ifdef CONFIG_THUMB2_KERNEL
134 SPFIX( str r0, [sp] ) @ temporarily saved
135 SPFIX( mov r0, sp )
136 SPFIX( tst r0, #4 ) @ test original stack alignment
137 SPFIX( ldr r0, [sp] ) @ restored
138 #else
139 SPFIX( tst sp, #4 )
140 #endif
141 SPFIX( subeq sp, sp, #4 )
142 stmia sp, {r1 - r12}
144 ldmia r0, {r1 - r3}
145 add r5, sp, #S_SP - 4 @ here for interlock avoidance
146 mov r4, #-1 @ "" "" "" ""
147 add r0, sp, #(S_FRAME_SIZE + \stack_hole - 4)
148 SPFIX( addeq r0, r0, #4 )
149 str r1, [sp, #-4]! @ save the "real" r0 copied
150 @ from the exception stack
152 mov r1, lr
154 @
155 @ We are now ready to fill in the remaining blanks on the stack:
156 @
157 @ r0 - sp_svc
158 @ r1 - lr_svc
159 @ r2 - lr_<exception>, already fixed up for correct return/restart
160 @ r3 - spsr_<exception>
161 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
162 @
163 stmia r5, {r0 - r4}
165 asm_trace_hardirqs_off
166 .endm
168 .align 5
169 __dabt_svc:
170 svc_entry
172 @
173 @ get ready to re-enable interrupts if appropriate
174 @
175 mrs r9, cpsr
176 tst r3, #PSR_I_BIT
177 biceq r9, r9, #PSR_I_BIT
179 @
180 @ Call the processor-specific abort handler:
181 @
182 @ r2 - aborted context pc
183 @ r3 - aborted context cpsr
184 @
185 @ The abort handler must return the aborted address in r0, and
186 @ the fault status register in r1. r9 must be preserved.
187 @
188 #ifdef MULTI_DABORT
189 ldr r4, .LCprocfns
190 mov lr, pc
191 ldr pc, [r4, #PROCESSOR_DABT_FUNC]
192 #else
193 bl CPU_DABORT_HANDLER
194 #endif
196 @
197 @ set desired IRQ state, then call main handler
198 @
199 msr cpsr_c, r9
200 mov r2, sp
201 bl do_DataAbort
203 @
204 @ IRQs off again before pulling preserved data off the stack
205 @
206 disable_irq
208 @
209 @ restore SPSR and restart the instruction
210 @
211 ldr r2, [sp, #S_PSR]
212 svc_exit r2 @ return from exception
213 UNWIND(.fnend )
214 ENDPROC(__dabt_svc)
216 .align 5
217 __irq_svc:
218 svc_entry
220 #ifdef CONFIG_PREEMPT
221 get_thread_info tsk
222 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
223 add r7, r8, #1 @ increment it
224 str r7, [tsk, #TI_PREEMPT]
225 #endif
227 irq_handler
228 #ifdef CONFIG_PREEMPT
229 str r8, [tsk, #TI_PREEMPT] @ restore preempt count
230 ldr r0, [tsk, #TI_FLAGS] @ get flags
231 teq r8, #0 @ if preempt count != 0
232 movne r0, #0 @ force flags to 0
233 tst r0, #_TIF_NEED_RESCHED
234 blne svc_preempt
235 #endif
236 ldr r4, [sp, #S_PSR] @ irqs are already disabled
237 #ifdef CONFIG_TRACE_IRQFLAGS
238 tst r4, #PSR_I_BIT
239 bleq trace_hardirqs_on
240 #endif
241 svc_exit r4 @ return from exception
242 UNWIND(.fnend )
243 ENDPROC(__irq_svc)
245 .ltorg
247 #ifdef CONFIG_PREEMPT
248 svc_preempt:
249 mov r8, lr
250 1: bl preempt_schedule_irq @ irq en/disable is done inside
251 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
252 tst r0, #_TIF_NEED_RESCHED
253 moveq pc, r8 @ go again
254 b 1b
255 #endif
257 .align 5
258 __und_svc:
259 #ifdef CONFIG_KPROBES
260 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
261 @ it obviously needs free stack space which then will belong to
262 @ the saved context.
263 svc_entry 64
264 #else
265 svc_entry
266 #endif
268 @
269 @ call emulation code, which returns using r9 if it has emulated
270 @ the instruction, or the more conventional lr if we are to treat
271 @ this as a real undefined instruction
272 @
273 @ r0 - instruction
274 @
275 #ifndef CONFIG_THUMB2_KERNEL
276 ldr r0, [r2, #-4]
277 #else
278 ldrh r0, [r2, #-2] @ Thumb instruction at LR - 2
279 and r9, r0, #0xf800
280 cmp r9, #0xe800 @ 32-bit instruction if xx >= 0
281 ldrhhs r9, [r2] @ bottom 16 bits
282 orrhs r0, r9, r0, lsl #16
283 #endif
284 adr r9, BSYM(1f)
285 bl call_fpe
287 mov r0, sp @ struct pt_regs *regs
288 bl do_undefinstr
290 @
291 @ IRQs off again before pulling preserved data off the stack
292 @
293 1: disable_irq
295 @
296 @ restore SPSR and restart the instruction
297 @
298 ldr r2, [sp, #S_PSR] @ Get SVC cpsr
299 svc_exit r2 @ return from exception
300 UNWIND(.fnend )
301 ENDPROC(__und_svc)
303 .align 5
304 __pabt_svc:
305 svc_entry
307 @
308 @ re-enable interrupts if appropriate
309 @
310 mrs r9, cpsr
311 tst r3, #PSR_I_BIT
312 biceq r9, r9, #PSR_I_BIT
314 mov r0, r2 @ pass address of aborted instruction.
315 #ifdef MULTI_PABORT
316 ldr r4, .LCprocfns
317 mov lr, pc
318 ldr pc, [r4, #PROCESSOR_PABT_FUNC]
319 #else
320 bl CPU_PABORT_HANDLER
321 #endif
322 msr cpsr_c, r9 @ Maybe enable interrupts
323 mov r2, sp @ regs
324 bl do_PrefetchAbort @ call abort handler
326 @
327 @ IRQs off again before pulling preserved data off the stack
328 @
329 disable_irq
331 @
332 @ restore SPSR and restart the instruction
333 @
334 ldr r2, [sp, #S_PSR]
335 svc_exit r2 @ return from exception
336 UNWIND(.fnend )
337 ENDPROC(__pabt_svc)
339 .align 5
340 .LCcralign:
341 .word cr_alignment
342 #ifdef MULTI_DABORT
343 .LCprocfns:
344 .word processor
345 #endif
346 .LCfp:
347 .word fp_enter
349 /*
350 * User mode handlers
351 *
352 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
353 */
355 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
356 #error "sizeof(struct pt_regs) must be a multiple of 8"
357 #endif
359 .macro usr_entry
360 UNWIND(.fnstart )
361 UNWIND(.cantunwind ) @ don't unwind the user space
362 sub sp, sp, #S_FRAME_SIZE
363 ARM( stmib sp, {r1 - r12} )
364 THUMB( stmia sp, {r0 - r12} )
366 ldmia r0, {r1 - r3}
367 add r0, sp, #S_PC @ here for interlock avoidance
368 mov r4, #-1 @ "" "" "" ""
370 str r1, [sp] @ save the "real" r0 copied
371 @ from the exception stack
373 @
374 @ We are now ready to fill in the remaining blanks on the stack:
375 @
376 @ r2 - lr_<exception>, already fixed up for correct return/restart
377 @ r3 - spsr_<exception>
378 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
379 @
380 @ Also, separately save sp_usr and lr_usr
381 @
382 stmia r0, {r2 - r4}
383 ARM( stmdb r0, {sp, lr}^ )
384 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
386 @
387 @ Enable the alignment trap while in kernel mode
388 @
389 alignment_trap r0
391 @
392 @ Clear FP to mark the first stack frame
393 @
394 zero_fp
396 asm_trace_hardirqs_off
397 .endm
399 .macro kuser_cmpxchg_check
400 #if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
401 #ifndef CONFIG_MMU
402 #warning "NPTL on non MMU needs fixing"
403 #else
404 @ Make sure our user space atomic helper is restarted
405 @ if it was interrupted in a critical region. Here we
406 @ perform a quick test inline since it should be false
407 @ 99.9999% of the time. The rest is done out of line.
408 cmp r2, #TASK_SIZE
409 blhs kuser_cmpxchg_fixup
410 #endif
411 #endif
412 .endm
414 .align 5
415 __dabt_usr:
416 usr_entry
417 kuser_cmpxchg_check
419 @
420 @ Call the processor-specific abort handler:
421 @
422 @ r2 - aborted context pc
423 @ r3 - aborted context cpsr
424 @
425 @ The abort handler must return the aborted address in r0, and
426 @ the fault status register in r1.
427 @
428 #ifdef MULTI_DABORT
429 ldr r4, .LCprocfns
430 mov lr, pc
431 ldr pc, [r4, #PROCESSOR_DABT_FUNC]
432 #else
433 bl CPU_DABORT_HANDLER
434 #endif
436 @
437 @ IRQs on, then call the main handler
438 @
439 enable_irq
440 mov r2, sp
441 adr lr, BSYM(ret_from_exception)
442 b do_DataAbort
443 UNWIND(.fnend )
444 ENDPROC(__dabt_usr)
446 .align 5
447 __irq_usr:
448 usr_entry
449 kuser_cmpxchg_check
451 get_thread_info tsk
452 #ifdef CONFIG_PREEMPT
453 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
454 add r7, r8, #1 @ increment it
455 str r7, [tsk, #TI_PREEMPT]
456 #endif
458 irq_handler
459 #ifdef CONFIG_PREEMPT
460 ldr r0, [tsk, #TI_PREEMPT]
461 str r8, [tsk, #TI_PREEMPT]
462 teq r0, r7
463 ARM( strne r0, [r0, -r0] )
464 THUMB( movne r0, #0 )
465 THUMB( strne r0, [r0] )
466 #endif
467 #ifdef CONFIG_TRACE_IRQFLAGS
468 bl trace_hardirqs_on
469 #endif
471 mov why, #0
472 b ret_to_user
473 UNWIND(.fnend )
474 ENDPROC(__irq_usr)
476 .ltorg
478 .align 5
479 __und_usr:
480 usr_entry
482 @
483 @ fall through to the emulation code, which returns using r9 if
484 @ it has emulated the instruction, or the more conventional lr
485 @ if we are to treat this as a real undefined instruction
486 @
487 @ r0 - instruction
488 @
489 adr r9, BSYM(ret_from_exception)
490 adr lr, BSYM(__und_usr_unknown)
491 tst r3, #PSR_T_BIT @ Thumb mode?
492 itet eq @ explicit IT needed for the 1f label
493 subeq r4, r2, #4 @ ARM instr at LR - 4
494 subne r4, r2, #2 @ Thumb instr at LR - 2
495 1: ldreqt r0, [r4]
496 #ifdef CONFIG_CPU_ENDIAN_BE8
497 reveq r0, r0 @ little endian instruction
498 #endif
499 beq call_fpe
500 @ Thumb instruction
501 #if __LINUX_ARM_ARCH__ >= 7
502 2:
503 ARM( ldrht r5, [r4], #2 )
504 THUMB( ldrht r5, [r4] )
505 THUMB( add r4, r4, #2 )
506 and r0, r5, #0xf800 @ mask bits 111x x... .... ....
507 cmp r0, #0xe800 @ 32bit instruction if xx != 0
508 blo __und_usr_unknown
509 3: ldrht r0, [r4]
510 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
511 orr r0, r0, r5, lsl #16
512 #else
513 b __und_usr_unknown
514 #endif
515 UNWIND(.fnend )
516 ENDPROC(__und_usr)
518 @
519 @ fallthrough to call_fpe
520 @
522 /*
523 * The out of line fixup for the ldrt above.
524 */
525 .section .fixup, "ax"
526 4: mov pc, r9
527 .previous
528 .section __ex_table,"a"
529 .long 1b, 4b
530 #if __LINUX_ARM_ARCH__ >= 7
531 .long 2b, 4b
532 .long 3b, 4b
533 #endif
534 .previous
536 /*
537 * Check whether the instruction is a co-processor instruction.
538 * If yes, we need to call the relevant co-processor handler.
539 *
540 * Note that we don't do a full check here for the co-processor
541 * instructions; all instructions with bit 27 set are well
542 * defined. The only instructions that should fault are the
543 * co-processor instructions. However, we have to watch out
544 * for the ARM6/ARM7 SWI bug.
545 *
546 * NEON is a special case that has to be handled here. Not all
547 * NEON instructions are co-processor instructions, so we have
548 * to make a special case of checking for them. Plus, there's
549 * five groups of them, so we have a table of mask/opcode pairs
550 * to check against, and if any match then we branch off into the
551 * NEON handler code.
552 *
553 * Emulators may wish to make use of the following registers:
554 * r0 = instruction opcode.
555 * r2 = PC+4
556 * r9 = normal "successful" return address
557 * r10 = this threads thread_info structure.
558 * lr = unrecognised instruction return address
559 */
560 @
561 @ Fall-through from Thumb-2 __und_usr
562 @
563 #ifdef CONFIG_NEON
564 adr r6, .LCneon_thumb_opcodes
565 b 2f
566 #endif
567 call_fpe:
568 #ifdef CONFIG_NEON
569 adr r6, .LCneon_arm_opcodes
570 2:
571 ldr r7, [r6], #4 @ mask value
572 cmp r7, #0 @ end mask?
573 beq 1f
574 and r8, r0, r7
575 ldr r7, [r6], #4 @ opcode bits matching in mask
576 cmp r8, r7 @ NEON instruction?
577 bne 2b
578 get_thread_info r10
579 mov r7, #1
580 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
581 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
582 b do_vfp @ let VFP handler handle this
583 1:
584 #endif
585 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
586 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
587 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
588 and r8, r0, #0x0f000000 @ mask out op-code bits
589 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)?
590 #endif
591 moveq pc, lr
592 get_thread_info r10 @ get current thread
593 and r8, r0, #0x00000f00 @ mask out CP number
594 THUMB( lsr r8, r8, #8 )
595 mov r7, #1
596 add r6, r10, #TI_USED_CP
597 ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[]
598 THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[]
599 #ifdef CONFIG_IWMMXT
600 @ Test if we need to give access to iWMMXt coprocessors
601 ldr r5, [r10, #TI_FLAGS]
602 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
603 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
604 bcs iwmmxt_task_enable
605 #endif
606 ARM( add pc, pc, r8, lsr #6 )
607 THUMB( lsl r8, r8, #2 )
608 THUMB( add pc, r8 )
609 nop
611 W(mov) pc, lr @ CP#0
612 W(b) do_fpe @ CP#1 (FPE)
613 W(b) do_fpe @ CP#2 (FPE)
614 W(mov) pc, lr @ CP#3
615 #ifdef CONFIG_CRUNCH
616 b crunch_task_enable @ CP#4 (MaverickCrunch)
617 b crunch_task_enable @ CP#5 (MaverickCrunch)
618 b crunch_task_enable @ CP#6 (MaverickCrunch)
619 #else
620 W(mov) pc, lr @ CP#4
621 W(mov) pc, lr @ CP#5
622 W(mov) pc, lr @ CP#6
623 #endif
624 W(mov) pc, lr @ CP#7
625 W(mov) pc, lr @ CP#8
626 W(mov) pc, lr @ CP#9
627 #ifdef CONFIG_VFP
628 W(b) do_vfp @ CP#10 (VFP)
629 W(b) do_vfp @ CP#11 (VFP)
630 #else
631 W(mov) pc, lr @ CP#10 (VFP)
632 W(mov) pc, lr @ CP#11 (VFP)
633 #endif
634 W(mov) pc, lr @ CP#12
635 W(mov) pc, lr @ CP#13
636 W(mov) pc, lr @ CP#14 (Debug)
637 W(mov) pc, lr @ CP#15 (Control)
639 #ifdef CONFIG_NEON
640 .align 6
642 .LCneon_arm_opcodes:
643 .word 0xfe000000 @ mask
644 .word 0xf2000000 @ opcode
646 .word 0xff100000 @ mask
647 .word 0xf4000000 @ opcode
649 .word 0x00000000 @ mask
650 .word 0x00000000 @ opcode
652 .LCneon_thumb_opcodes:
653 .word 0xef000000 @ mask
654 .word 0xef000000 @ opcode
656 .word 0xff100000 @ mask
657 .word 0xf9000000 @ opcode
659 .word 0x00000000 @ mask
660 .word 0x00000000 @ opcode
661 #endif
663 do_fpe:
664 enable_irq
665 ldr r4, .LCfp
666 add r10, r10, #TI_FPSTATE @ r10 = workspace
667 ldr pc, [r4] @ Call FP module USR entry point
669 /*
670 * The FP module is called with these registers set:
671 * r0 = instruction
672 * r2 = PC+4
673 * r9 = normal "successful" return address
674 * r10 = FP workspace
675 * lr = unrecognised FP instruction return address
676 */
678 .data
679 ENTRY(fp_enter)
680 .word no_fp
681 .previous
683 ENTRY(no_fp)
684 mov pc, lr
685 ENDPROC(no_fp)
687 __und_usr_unknown:
688 enable_irq
689 mov r0, sp
690 adr lr, BSYM(ret_from_exception)
691 b do_undefinstr
692 ENDPROC(__und_usr_unknown)
694 .align 5
695 __pabt_usr:
696 usr_entry
698 mov r0, r2 @ pass address of aborted instruction.
699 #ifdef MULTI_PABORT
700 ldr r4, .LCprocfns
701 mov lr, pc
702 ldr pc, [r4, #PROCESSOR_PABT_FUNC]
703 #else
704 bl CPU_PABORT_HANDLER
705 #endif
706 enable_irq @ Enable interrupts
707 mov r2, sp @ regs
708 bl do_PrefetchAbort @ call abort handler
709 UNWIND(.fnend )
710 /* fall through */
711 /*
712 * This is the return code to user mode for abort handlers
713 */
714 ENTRY(ret_from_exception)
715 UNWIND(.fnstart )
716 UNWIND(.cantunwind )
717 get_thread_info tsk
718 mov why, #0
719 b ret_to_user
720 UNWIND(.fnend )
721 ENDPROC(__pabt_usr)
722 ENDPROC(ret_from_exception)
724 /*
725 * Register switch for ARMv3 and ARMv4 processors
726 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
727 * previous and next are guaranteed not to be the same.
728 */
729 ENTRY(__switch_to)
730 UNWIND(.fnstart )
731 UNWIND(.cantunwind )
732 add ip, r1, #TI_CPU_SAVE
733 ldr r3, [r2, #TI_TP_VALUE]
734 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
735 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
736 THUMB( str sp, [ip], #4 )
737 THUMB( str lr, [ip], #4 )
738 #ifdef CONFIG_MMU
739 ldr r6, [r2, #TI_CPU_DOMAIN]
740 #endif
741 #if defined(CONFIG_HAS_TLS_REG)
742 mcr p15, 0, r3, c13, c0, 3 @ set TLS register
743 #elif !defined(CONFIG_TLS_REG_EMUL)
744 mov r4, #0xffff0fff
745 str r3, [r4, #-15] @ TLS val at 0xffff0ff0
746 #endif
747 #ifdef CONFIG_MMU
748 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
749 #endif
750 mov r5, r0
751 add r4, r2, #TI_CPU_SAVE
752 ldr r0, =thread_notify_head
753 mov r1, #THREAD_NOTIFY_SWITCH
754 bl atomic_notifier_call_chain
755 THUMB( mov ip, r4 )
756 mov r0, r5
757 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
758 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously
759 THUMB( ldr sp, [ip], #4 )
760 THUMB( ldr pc, [ip] )
761 UNWIND(.fnend )
762 ENDPROC(__switch_to)
764 __INIT
766 /*
767 * User helpers.
768 *
769 * These are segment of kernel provided user code reachable from user space
770 * at a fixed address in kernel memory. This is used to provide user space
771 * with some operations which require kernel help because of unimplemented
772 * native feature and/or instructions in many ARM CPUs. The idea is for
773 * this code to be executed directly in user mode for best efficiency but
774 * which is too intimate with the kernel counter part to be left to user
775 * libraries. In fact this code might even differ from one CPU to another
776 * depending on the available instruction set and restrictions like on
777 * SMP systems. In other words, the kernel reserves the right to change
778 * this code as needed without warning. Only the entry points and their
779 * results are guaranteed to be stable.
780 *
781 * Each segment is 32-byte aligned and will be moved to the top of the high
782 * vector page. New segments (if ever needed) must be added in front of
783 * existing ones. This mechanism should be used only for things that are
784 * really small and justified, and not be abused freely.
785 *
786 * User space is expected to implement those things inline when optimizing
787 * for a processor that has the necessary native support, but only if such
788 * resulting binaries are already to be incompatible with earlier ARM
789 * processors due to the use of unsupported instructions other than what
790 * is provided here. In other words don't make binaries unable to run on
791 * earlier processors just for the sake of not using these kernel helpers
792 * if your compiled code is not going to use the new instructions for other
793 * purpose.
794 */
795 THUMB( .arm )
797 .macro usr_ret, reg
798 #ifdef CONFIG_ARM_THUMB
799 bx \reg
800 #else
801 mov pc, \reg
802 #endif
803 .endm
805 .align 5
806 .globl __kuser_helper_start
807 __kuser_helper_start:
809 /*
810 * Reference prototype:
811 *
812 * void __kernel_memory_barrier(void)
813 *
814 * Input:
815 *
816 * lr = return address
817 *
818 * Output:
819 *
820 * none
821 *
822 * Clobbered:
823 *
824 * none
825 *
826 * Definition and user space usage example:
827 *
828 * typedef void (__kernel_dmb_t)(void);
829 * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0)
830 *
831 * Apply any needed memory barrier to preserve consistency with data modified
832 * manually and __kuser_cmpxchg usage.
833 *
834 * This could be used as follows:
835 *
836 * #define __kernel_dmb() \
837 * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \
838 * : : : "r0", "lr","cc" )
839 */
841 __kuser_memory_barrier: @ 0xffff0fa0
842 smp_dmb
843 usr_ret lr
845 .align 5
847 /*
848 * Reference prototype:
849 *
850 * int __kernel_cmpxchg(int oldval, int newval, int *ptr)
851 *
852 * Input:
853 *
854 * r0 = oldval
855 * r1 = newval
856 * r2 = ptr
857 * lr = return address
858 *
859 * Output:
860 *
861 * r0 = returned value (zero or non-zero)
862 * C flag = set if r0 == 0, clear if r0 != 0
863 *
864 * Clobbered:
865 *
866 * r3, ip, flags
867 *
868 * Definition and user space usage example:
869 *
870 * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr);
871 * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0)
872 *
873 * Atomically store newval in *ptr if *ptr is equal to oldval for user space.
874 * Return zero if *ptr was changed or non-zero if no exchange happened.
875 * The C flag is also set if *ptr was changed to allow for assembly
876 * optimization in the calling code.
877 *
878 * Notes:
879 *
880 * - This routine already includes memory barriers as needed.
881 *
882 * For example, a user space atomic_add implementation could look like this:
883 *
884 * #define atomic_add(ptr, val) \
885 * ({ register unsigned int *__ptr asm("r2") = (ptr); \
886 * register unsigned int __result asm("r1"); \
887 * asm volatile ( \
888 * "1: @ atomic_add\n\t" \
889 * "ldr r0, [r2]\n\t" \
890 * "mov r3, #0xffff0fff\n\t" \
891 * "add lr, pc, #4\n\t" \
892 * "add r1, r0, %2\n\t" \
893 * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \
894 * "bcc 1b" \
895 * : "=&r" (__result) \
896 * : "r" (__ptr), "rIL" (val) \
897 * : "r0","r3","ip","lr","cc","memory" ); \
898 * __result; })
899 */
901 __kuser_cmpxchg: @ 0xffff0fc0
903 #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
905 /*
906 * Poor you. No fast solution possible...
907 * The kernel itself must perform the operation.
908 * A special ghost syscall is used for that (see traps.c).
909 */
910 stmfd sp!, {r7, lr}
911 mov r7, #0xff00 @ 0xfff0 into r7 for EABI
912 orr r7, r7, #0xf0
913 swi #0x9ffff0
914 ldmfd sp!, {r7, pc}
916 #elif __LINUX_ARM_ARCH__ < 6
918 #ifdef CONFIG_MMU
920 /*
921 * The only thing that can break atomicity in this cmpxchg
922 * implementation is either an IRQ or a data abort exception
923 * causing another process/thread to be scheduled in the middle
924 * of the critical sequence. To prevent this, code is added to
925 * the IRQ and data abort exception handlers to set the pc back
926 * to the beginning of the critical section if it is found to be
927 * within that critical section (see kuser_cmpxchg_fixup).
928 */
929 1: ldr r3, [r2] @ load current val
930 subs r3, r3, r0 @ compare with oldval
931 2: streq r1, [r2] @ store newval if eq
932 rsbs r0, r3, #0 @ set return val and C flag
933 usr_ret lr
935 .text
936 kuser_cmpxchg_fixup:
937 @ Called from kuser_cmpxchg_check macro.
938 @ r2 = address of interrupted insn (must be preserved).
939 @ sp = saved regs. r7 and r8 are clobbered.
940 @ 1b = first critical insn, 2b = last critical insn.
941 @ If r2 >= 1b and r2 <= 2b then saved pc_usr is set to 1b.
942 mov r7, #0xffff0fff
943 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
944 subs r8, r2, r7
945 rsbcss r8, r8, #(2b - 1b)
946 strcs r7, [sp, #S_PC]
947 mov pc, lr
948 .previous
950 #else
951 #warning "NPTL on non MMU needs fixing"
952 mov r0, #-1
953 adds r0, r0, #0
954 usr_ret lr
955 #endif
957 #else
959 #ifdef CONFIG_SMP
960 mcr p15, 0, r0, c7, c10, 5 @ dmb
961 #endif
962 1: ldrex r3, [r2]
963 subs r3, r3, r0
964 strexeq r3, r1, [r2]
965 teqeq r3, #1
966 beq 1b
967 rsbs r0, r3, #0
968 /* beware -- each __kuser slot must be 8 instructions max */
969 #ifdef CONFIG_SMP
970 b __kuser_memory_barrier
971 #else
972 usr_ret lr
973 #endif
975 #endif
977 .align 5
979 /*
980 * Reference prototype:
981 *
982 * int __kernel_get_tls(void)
983 *
984 * Input:
985 *
986 * lr = return address
987 *
988 * Output:
989 *
990 * r0 = TLS value
991 *
992 * Clobbered:
993 *
994 * none
995 *
996 * Definition and user space usage example:
997 *
998 * typedef int (__kernel_get_tls_t)(void);
999 * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0)
1000 *
1001 * Get the TLS value as previously set via the __ARM_NR_set_tls syscall.
1002 *
1003 * This could be used as follows:
1004 *
1005 * #define __kernel_get_tls() \
1006 * ({ register unsigned int __val asm("r0"); \
1007 * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \
1008 * : "=r" (__val) : : "lr","cc" ); \
1009 * __val; })
1010 */
1012 __kuser_get_tls: @ 0xffff0fe0
1014 #if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL)
1015 ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0
1016 #else
1017 mrc p15, 0, r0, c13, c0, 3 @ read TLS register
1018 #endif
1019 usr_ret lr
1021 .rep 5
1022 .word 0 @ pad up to __kuser_helper_version
1023 .endr
1025 /*
1026 * Reference declaration:
1027 *
1028 * extern unsigned int __kernel_helper_version;
1029 *
1030 * Definition and user space usage example:
1031 *
1032 * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc)
1033 *
1034 * User space may read this to determine the curent number of helpers
1035 * available.
1036 */
1038 __kuser_helper_version: @ 0xffff0ffc
1039 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
1041 .globl __kuser_helper_end
1042 __kuser_helper_end:
1044 THUMB( .thumb )
1046 /*
1047 * Vector stubs.
1048 *
1049 * This code is copied to 0xffff0200 so we can use branches in the
1050 * vectors, rather than ldr's. Note that this code must not
1051 * exceed 0x300 bytes.
1052 *
1053 * Common stub entry macro:
1054 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1055 *
1056 * SP points to a minimal amount of processor-private memory, the address
1057 * of which is copied into r0 for the mode specific abort handler.
1058 */
1059 .macro vector_stub, name, mode, correction=0
1060 .align 5
1062 vector_\name:
1063 .if \correction
1064 sub lr, lr, #\correction
1065 .endif
1067 @
1068 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
1069 @ (parent CPSR)
1070 @
1071 stmia sp, {r0, lr} @ save r0, lr
1072 mrs lr, spsr
1073 str lr, [sp, #8] @ save spsr
1075 @
1076 @ Prepare for SVC32 mode. IRQs remain disabled.
1077 @
1078 mrs r0, cpsr
1079 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
1080 msr spsr_cxsf, r0
1082 @
1083 @ the branch table must immediately follow this code
1084 @
1085 and lr, lr, #0x0f
1086 THUMB( adr r0, 1f )
1087 THUMB( ldr lr, [r0, lr, lsl #2] )
1088 mov r0, sp
1089 ARM( ldr lr, [pc, lr, lsl #2] )
1090 movs pc, lr @ branch to handler in SVC mode
1091 ENDPROC(vector_\name)
1093 .align 2
1094 @ handler addresses follow this label
1095 1:
1096 .endm
1098 .globl __stubs_start
1099 __stubs_start:
1100 /*
1101 * Interrupt dispatcher
1102 */
1103 vector_stub irq, IRQ_MODE, 4
1105 .long __irq_usr @ 0 (USR_26 / USR_32)
1106 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
1107 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
1108 .long __irq_svc @ 3 (SVC_26 / SVC_32)
1109 .long __irq_invalid @ 4
1110 .long __irq_invalid @ 5
1111 .long __irq_invalid @ 6
1112 .long __irq_invalid @ 7
1113 .long __irq_invalid @ 8
1114 .long __irq_invalid @ 9
1115 .long __irq_invalid @ a
1116 .long __irq_invalid @ b
1117 .long __irq_invalid @ c
1118 .long __irq_invalid @ d
1119 .long __irq_invalid @ e
1120 .long __irq_invalid @ f
1122 /*
1123 * Data abort dispatcher
1124 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1125 */
1126 vector_stub dabt, ABT_MODE, 8
1128 .long __dabt_usr @ 0 (USR_26 / USR_32)
1129 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
1130 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
1131 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
1132 .long __dabt_invalid @ 4
1133 .long __dabt_invalid @ 5
1134 .long __dabt_invalid @ 6
1135 .long __dabt_invalid @ 7
1136 .long __dabt_invalid @ 8
1137 .long __dabt_invalid @ 9
1138 .long __dabt_invalid @ a
1139 .long __dabt_invalid @ b
1140 .long __dabt_invalid @ c
1141 .long __dabt_invalid @ d
1142 .long __dabt_invalid @ e
1143 .long __dabt_invalid @ f
1145 /*
1146 * Prefetch abort dispatcher
1147 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1148 */
1149 vector_stub pabt, ABT_MODE, 4
1151 .long __pabt_usr @ 0 (USR_26 / USR_32)
1152 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
1153 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
1154 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
1155 .long __pabt_invalid @ 4
1156 .long __pabt_invalid @ 5
1157 .long __pabt_invalid @ 6
1158 .long __pabt_invalid @ 7
1159 .long __pabt_invalid @ 8
1160 .long __pabt_invalid @ 9
1161 .long __pabt_invalid @ a
1162 .long __pabt_invalid @ b
1163 .long __pabt_invalid @ c
1164 .long __pabt_invalid @ d
1165 .long __pabt_invalid @ e
1166 .long __pabt_invalid @ f
1168 /*
1169 * Undef instr entry dispatcher
1170 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1171 */
1172 vector_stub und, UND_MODE
1174 .long __und_usr @ 0 (USR_26 / USR_32)
1175 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
1176 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
1177 .long __und_svc @ 3 (SVC_26 / SVC_32)
1178 .long __und_invalid @ 4
1179 .long __und_invalid @ 5
1180 .long __und_invalid @ 6
1181 .long __und_invalid @ 7
1182 .long __und_invalid @ 8
1183 .long __und_invalid @ 9
1184 .long __und_invalid @ a
1185 .long __und_invalid @ b
1186 .long __und_invalid @ c
1187 .long __und_invalid @ d
1188 .long __und_invalid @ e
1189 .long __und_invalid @ f
1191 .align 5
1193 /*=============================================================================
1194 * Undefined FIQs
1195 *-----------------------------------------------------------------------------
1196 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
1197 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
1198 * Basically to switch modes, we *HAVE* to clobber one register... brain
1199 * damage alert! I don't think that we can execute any code in here in any
1200 * other mode than FIQ... Ok you can switch to another mode, but you can't
1201 * get out of that mode without clobbering one register.
1202 */
1203 vector_fiq:
1204 disable_fiq
1205 subs pc, lr, #4
1207 /*=============================================================================
1208 * Address exception handler
1209 *-----------------------------------------------------------------------------
1210 * These aren't too critical.
1211 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1212 */
1214 vector_addrexcptn:
1215 b vector_addrexcptn
1217 /*
1218 * We group all the following data together to optimise
1219 * for CPUs with separate I & D caches.
1220 */
1221 .align 5
1223 .LCvswi:
1224 .word vector_swi
1226 .globl __stubs_end
1227 __stubs_end:
1229 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start
1231 .globl __vectors_start
1232 __vectors_start:
1233 ARM( swi SYS_ERROR0 )
1234 THUMB( svc #0 )
1235 THUMB( nop )
1236 W(b) vector_und + stubs_offset
1237 W(ldr) pc, .LCvswi + stubs_offset
1238 W(b) vector_pabt + stubs_offset
1239 W(b) vector_dabt + stubs_offset
1240 W(b) vector_addrexcptn + stubs_offset
1241 W(b) vector_irq + stubs_offset
1242 W(b) vector_fiq + stubs_offset
1244 .globl __vectors_end
1245 __vectors_end:
1247 .data
1249 .globl cr_alignment
1250 .globl cr_no_alignment
1251 cr_alignment:
1252 .space 4
1253 cr_no_alignment:
1254 .space 4