2 * linux/arch/arm/mach-at91/clock.c
4 * Copyright (C) 2005 David Brownell
5 * Copyright (C) 2005 Ivan Kokshaysky
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
17 #include <linux/debugfs.h>
18 #include <linux/seq_file.h>
19 #include <linux/list.h>
20 #include <linux/errno.h>
21 #include <linux/err.h>
22 #include <linux/spinlock.h>
23 #include <linux/delay.h>
24 #include <linux/clk.h>
27 #include <mach/hardware.h>
28 #include <mach/at91_pmc.h>
35 * There's a lot more which can be done with clocks, including cpufreq
36 * integration, slow clock mode support (for system suspend), letting
37 * PLLB be used at other rates (on boards that don't need USB), etc.
40 #define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY)
41 #define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE)
42 #define clk_is_peripheral(x) ((x)->type & CLK_TYPE_PERIPHERAL)
43 #define clk_is_sys(x) ((x)->type & CLK_TYPE_SYSTEM)
47 * Chips have some kind of clocks : group them by functionality
49 #define cpu_has_utmi() ( cpu_is_at91cap9() \
50 || cpu_is_at91sam9rl() \
51 || cpu_is_at91sam9g45())
53 #define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \
54 || cpu_is_at91sam9g45())
56 #define cpu_has_300M_plla() (cpu_is_at91sam9g10())
58 #define cpu_has_pllb() (!(cpu_is_at91sam9rl() \
59 || cpu_is_at91sam9g45()))
61 #define cpu_has_upll() (cpu_is_at91sam9g45())
63 /* USB host HS & FS */
64 #define cpu_has_uhp() (!cpu_is_at91sam9rl())
66 /* USB device FS only */
67 #define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \
68 || cpu_is_at91sam9g45()))
70 static LIST_HEAD(clocks
);
71 static DEFINE_SPINLOCK(clk_lock
);
73 static u32 at91_pllb_usb_init
;
76 * Four primary clock sources: two crystal oscillators (32K, main), and
77 * two PLLs. PLLA usually runs the master clock; and PLLB must run at
78 * 48 MHz (unless no USB function clocks are needed). The main clock and
79 * both PLLs are turned off to run in "slow clock mode" (system suspend).
81 static struct clk clk32k
= {
83 .rate_hz
= AT91_SLOW_CLOCK
,
84 .users
= 1, /* always on */
86 .type
= CLK_TYPE_PRIMARY
,
88 static struct clk main_clk
= {
90 .pmc_mask
= AT91_PMC_MOSCS
, /* in PMC_SR */
92 .type
= CLK_TYPE_PRIMARY
,
94 static struct clk plla
= {
97 .pmc_mask
= AT91_PMC_LOCKA
, /* in PMC_SR */
99 .type
= CLK_TYPE_PRIMARY
| CLK_TYPE_PLL
,
102 static void pllb_mode(struct clk
*clk
, int is_on
)
107 is_on
= AT91_PMC_LOCKB
;
108 value
= at91_pllb_usb_init
;
112 // REVISIT: Add work-around for AT91RM9200 Errata #26 ?
113 at91_sys_write(AT91_CKGR_PLLBR
, value
);
117 } while ((at91_sys_read(AT91_PMC_SR
) & AT91_PMC_LOCKB
) != is_on
);
120 static struct clk pllb
= {
123 .pmc_mask
= AT91_PMC_LOCKB
, /* in PMC_SR */
126 .type
= CLK_TYPE_PRIMARY
| CLK_TYPE_PLL
,
129 static void pmc_sys_mode(struct clk
*clk
, int is_on
)
132 at91_sys_write(AT91_PMC_SCER
, clk
->pmc_mask
);
134 at91_sys_write(AT91_PMC_SCDR
, clk
->pmc_mask
);
137 static void pmc_uckr_mode(struct clk
*clk
, int is_on
)
139 unsigned int uckr
= at91_sys_read(AT91_CKGR_UCKR
);
141 if (cpu_is_at91sam9g45()) {
143 uckr
|= AT91_PMC_BIASEN
;
145 uckr
&= ~AT91_PMC_BIASEN
;
149 is_on
= AT91_PMC_LOCKU
;
150 at91_sys_write(AT91_CKGR_UCKR
, uckr
| clk
->pmc_mask
);
152 at91_sys_write(AT91_CKGR_UCKR
, uckr
& ~(clk
->pmc_mask
));
156 } while ((at91_sys_read(AT91_PMC_SR
) & AT91_PMC_LOCKU
) != is_on
);
159 /* USB function clocks (PLLB must be 48 MHz) */
160 static struct clk udpck
= {
163 .mode
= pmc_sys_mode
,
165 static struct clk utmi_clk
= {
168 .pmc_mask
= AT91_PMC_UPLLEN
, /* in CKGR_UCKR */
169 .mode
= pmc_uckr_mode
,
170 .type
= CLK_TYPE_PLL
,
172 static struct clk uhpck
= {
174 /*.parent = ... we choose parent at runtime */
175 .mode
= pmc_sys_mode
,
180 * The master clock is divided from the CPU clock (by 1-4). It's used for
181 * memory, interfaces to on-chip peripherals, the AIC, and sometimes more
182 * (e.g baud rate generation). It's sourced from one of the primary clocks.
184 static struct clk mck
= {
186 .pmc_mask
= AT91_PMC_MCKRDY
, /* in PMC_SR */
189 static void pmc_periph_mode(struct clk
*clk
, int is_on
)
192 at91_sys_write(AT91_PMC_PCER
, clk
->pmc_mask
);
194 at91_sys_write(AT91_PMC_PCDR
, clk
->pmc_mask
);
197 static struct clk __init
*at91_css_to_clk(unsigned long css
)
200 case AT91_PMC_CSS_SLOW
:
202 case AT91_PMC_CSS_MAIN
:
204 case AT91_PMC_CSS_PLLA
:
206 case AT91_PMC_CSS_PLLB
:
208 /* CSS_PLLB == CSS_UPLL */
210 else if (cpu_has_pllb())
218 * Associate a particular clock with a function (eg, "uart") and device.
219 * The drivers can then request the same 'function' with several different
220 * devices and not care about which clock name to use.
222 void __init
at91_clock_associate(const char *id
, struct device
*dev
, const char *func
)
224 struct clk
*clk
= clk_get(NULL
, id
);
226 if (!dev
|| !clk
|| !IS_ERR(clk_get(dev
, func
)))
229 clk
->function
= func
;
233 /* clocks cannot be de-registered no refcounting necessary */
234 struct clk
*clk_get(struct device
*dev
, const char *id
)
238 list_for_each_entry(clk
, &clocks
, node
) {
239 if (strcmp(id
, clk
->name
) == 0)
241 if (clk
->function
&& (dev
== clk
->dev
) && strcmp(id
, clk
->function
) == 0)
245 return ERR_PTR(-ENOENT
);
247 EXPORT_SYMBOL(clk_get
);
249 void clk_put(struct clk
*clk
)
252 EXPORT_SYMBOL(clk_put
);
254 static void __clk_enable(struct clk
*clk
)
257 __clk_enable(clk
->parent
);
258 if (clk
->users
++ == 0 && clk
->mode
)
262 int clk_enable(struct clk
*clk
)
266 spin_lock_irqsave(&clk_lock
, flags
);
268 spin_unlock_irqrestore(&clk_lock
, flags
);
271 EXPORT_SYMBOL(clk_enable
);
273 static void __clk_disable(struct clk
*clk
)
275 BUG_ON(clk
->users
== 0);
276 if (--clk
->users
== 0 && clk
->mode
)
279 __clk_disable(clk
->parent
);
282 void clk_disable(struct clk
*clk
)
286 spin_lock_irqsave(&clk_lock
, flags
);
288 spin_unlock_irqrestore(&clk_lock
, flags
);
290 EXPORT_SYMBOL(clk_disable
);
292 unsigned long clk_get_rate(struct clk
*clk
)
297 spin_lock_irqsave(&clk_lock
, flags
);
300 if (rate
|| !clk
->parent
)
304 spin_unlock_irqrestore(&clk_lock
, flags
);
307 EXPORT_SYMBOL(clk_get_rate
);
309 /*------------------------------------------------------------------------*/
311 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
314 * For now, only the programmable clocks support reparenting (MCK could
315 * do this too, with care) or rate changing (the PLLs could do this too,
316 * ditto MCK but that's more for cpufreq). Drivers may reparent to get
317 * a better rate match; we don't.
320 long clk_round_rate(struct clk
*clk
, unsigned long rate
)
324 unsigned long actual
;
325 unsigned long prev
= ULONG_MAX
;
327 if (!clk_is_programmable(clk
))
329 spin_lock_irqsave(&clk_lock
, flags
);
331 actual
= clk
->parent
->rate_hz
;
332 for (prescale
= 0; prescale
< 7; prescale
++) {
336 if (actual
&& actual
<= rate
) {
337 if ((prev
- rate
) < (rate
- actual
)) {
346 spin_unlock_irqrestore(&clk_lock
, flags
);
347 return (prescale
< 7) ? actual
: -ENOENT
;
349 EXPORT_SYMBOL(clk_round_rate
);
351 int clk_set_rate(struct clk
*clk
, unsigned long rate
)
355 unsigned long actual
;
357 if (!clk_is_programmable(clk
))
361 spin_lock_irqsave(&clk_lock
, flags
);
363 actual
= clk
->parent
->rate_hz
;
364 for (prescale
= 0; prescale
< 7; prescale
++) {
365 if (actual
&& actual
<= rate
) {
368 pckr
= at91_sys_read(AT91_PMC_PCKR(clk
->id
));
369 pckr
&= AT91_PMC_CSS
; /* clock selection */
370 pckr
|= prescale
<< 2;
371 at91_sys_write(AT91_PMC_PCKR(clk
->id
), pckr
);
372 clk
->rate_hz
= actual
;
378 spin_unlock_irqrestore(&clk_lock
, flags
);
379 return (prescale
< 7) ? actual
: -ENOENT
;
381 EXPORT_SYMBOL(clk_set_rate
);
383 struct clk
*clk_get_parent(struct clk
*clk
)
387 EXPORT_SYMBOL(clk_get_parent
);
389 int clk_set_parent(struct clk
*clk
, struct clk
*parent
)
395 if (!clk_is_primary(parent
) || !clk_is_programmable(clk
))
398 if (cpu_is_at91sam9rl() && parent
->id
== AT91_PMC_CSS_PLLB
)
401 spin_lock_irqsave(&clk_lock
, flags
);
403 clk
->rate_hz
= parent
->rate_hz
;
404 clk
->parent
= parent
;
405 at91_sys_write(AT91_PMC_PCKR(clk
->id
), parent
->id
);
407 spin_unlock_irqrestore(&clk_lock
, flags
);
410 EXPORT_SYMBOL(clk_set_parent
);
412 /* establish PCK0..PCKN parentage and rate */
413 static void __init
init_programmable_clock(struct clk
*clk
)
418 pckr
= at91_sys_read(AT91_PMC_PCKR(clk
->id
));
419 parent
= at91_css_to_clk(pckr
& AT91_PMC_CSS
);
420 clk
->parent
= parent
;
421 clk
->rate_hz
= parent
->rate_hz
/ (1 << ((pckr
& AT91_PMC_PRES
) >> 2));
424 #endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
426 /*------------------------------------------------------------------------*/
428 #ifdef CONFIG_DEBUG_FS
430 static int at91_clk_show(struct seq_file
*s
, void *unused
)
432 u32 scsr
, pcsr
, uckr
= 0, sr
;
435 seq_printf(s
, "SCSR = %8x\n", scsr
= at91_sys_read(AT91_PMC_SCSR
));
436 seq_printf(s
, "PCSR = %8x\n", pcsr
= at91_sys_read(AT91_PMC_PCSR
));
437 seq_printf(s
, "MOR = %8x\n", at91_sys_read(AT91_CKGR_MOR
));
438 seq_printf(s
, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR
));
439 seq_printf(s
, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR
));
441 seq_printf(s
, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR
));
443 seq_printf(s
, "UCKR = %8x\n", uckr
= at91_sys_read(AT91_CKGR_UCKR
));
444 seq_printf(s
, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR
));
446 seq_printf(s
, "USB = %8x\n", at91_sys_read(AT91_PMC_USB
));
447 seq_printf(s
, "SR = %8x\n", sr
= at91_sys_read(AT91_PMC_SR
));
451 list_for_each_entry(clk
, &clocks
, node
) {
454 if (clk
->mode
== pmc_sys_mode
)
455 state
= (scsr
& clk
->pmc_mask
) ? "on" : "off";
456 else if (clk
->mode
== pmc_periph_mode
)
457 state
= (pcsr
& clk
->pmc_mask
) ? "on" : "off";
458 else if (clk
->mode
== pmc_uckr_mode
)
459 state
= (uckr
& clk
->pmc_mask
) ? "on" : "off";
460 else if (clk
->pmc_mask
)
461 state
= (sr
& clk
->pmc_mask
) ? "on" : "off";
462 else if (clk
== &clk32k
|| clk
== &main_clk
)
467 seq_printf(s
, "%-10s users=%2d %-3s %9ld Hz %s\n",
468 clk
->name
, clk
->users
, state
, clk_get_rate(clk
),
469 clk
->parent
? clk
->parent
->name
: "");
474 static int at91_clk_open(struct inode
*inode
, struct file
*file
)
476 return single_open(file
, at91_clk_show
, NULL
);
479 static const struct file_operations at91_clk_operations
= {
480 .open
= at91_clk_open
,
483 .release
= single_release
,
486 static int __init
at91_clk_debugfs_init(void)
488 /* /sys/kernel/debug/at91_clk */
489 (void) debugfs_create_file("at91_clk", S_IFREG
| S_IRUGO
, NULL
, NULL
, &at91_clk_operations
);
493 postcore_initcall(at91_clk_debugfs_init
);
497 /*------------------------------------------------------------------------*/
499 /* Register a new clock */
500 int __init
clk_register(struct clk
*clk
)
502 if (clk_is_peripheral(clk
)) {
504 clk
->mode
= pmc_periph_mode
;
505 list_add_tail(&clk
->node
, &clocks
);
507 else if (clk_is_sys(clk
)) {
509 clk
->mode
= pmc_sys_mode
;
511 list_add_tail(&clk
->node
, &clocks
);
513 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
514 else if (clk_is_programmable(clk
)) {
515 clk
->mode
= pmc_sys_mode
;
516 init_programmable_clock(clk
);
517 list_add_tail(&clk
->node
, &clocks
);
525 /*------------------------------------------------------------------------*/
527 static u32 __init
at91_pll_rate(struct clk
*pll
, u32 freq
, u32 reg
)
532 mul
= (reg
>> 16) & 0x7ff;
542 static u32 __init
at91_usb_rate(struct clk
*pll
, u32 freq
, u32 reg
)
544 if (pll
== &pllb
&& (reg
& AT91_PMC_USB96M
))
550 static unsigned __init
at91_pll_calc(unsigned main_freq
, unsigned out_freq
)
552 unsigned i
, div
= 0, mul
= 0, diff
= 1 << 30;
553 unsigned ret
= (out_freq
> 155000000) ? 0xbe00 : 0x3e00;
555 /* PLL output max 240 MHz (or 180 MHz per errata) */
556 if (out_freq
> 240000000)
559 for (i
= 1; i
< 256; i
++) {
561 unsigned input
, mul1
;
564 * PLL input between 1MHz and 32MHz per spec, but lower
565 * frequences seem necessary in some cases so allow 100K.
566 * Warning: some newer products need 2MHz min.
568 input
= main_freq
/ i
;
569 if (cpu_is_at91sam9g20() && input
< 2000000)
573 if (input
> 32000000)
576 mul1
= out_freq
/ input
;
577 if (cpu_is_at91sam9g20() && mul
> 63)
584 diff1
= out_freq
- input
* mul1
;
595 if (i
== 256 && diff
> (out_freq
>> 5))
597 return ret
| ((mul
- 1) << 16) | div
;
602 static struct clk
*const standard_pmc_clocks
[] __initdata
= {
603 /* four primary clocks */
612 /* PLLB generated USB full speed clock init */
613 static void __init
at91_pllb_usbfs_clock_init(unsigned long main_clock
)
616 * USB clock init: choose 48 MHz PLLB value,
617 * disable 48MHz clock during usb peripheral suspend.
619 * REVISIT: assumes MCK doesn't derive from PLLB!
621 uhpck
.parent
= &pllb
;
623 at91_pllb_usb_init
= at91_pll_calc(main_clock
, 48000000 * 2) | AT91_PMC_USB96M
;
624 pllb
.rate_hz
= at91_pll_rate(&pllb
, main_clock
, at91_pllb_usb_init
);
625 if (cpu_is_at91rm9200()) {
626 uhpck
.pmc_mask
= AT91RM9200_PMC_UHP
;
627 udpck
.pmc_mask
= AT91RM9200_PMC_UDP
;
628 at91_sys_write(AT91_PMC_SCER
, AT91RM9200_PMC_MCKUDP
);
629 } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
630 cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
631 cpu_is_at91sam9g10()) {
632 uhpck
.pmc_mask
= AT91SAM926x_PMC_UHP
;
633 udpck
.pmc_mask
= AT91SAM926x_PMC_UDP
;
634 } else if (cpu_is_at91cap9()) {
635 uhpck
.pmc_mask
= AT91CAP9_PMC_UHP
;
637 at91_sys_write(AT91_CKGR_PLLBR
, 0);
639 udpck
.rate_hz
= at91_usb_rate(&pllb
, pllb
.rate_hz
, at91_pllb_usb_init
);
640 uhpck
.rate_hz
= at91_usb_rate(&pllb
, pllb
.rate_hz
, at91_pllb_usb_init
);
643 /* UPLL generated USB full speed clock init */
644 static void __init
at91_upll_usbfs_clock_init(unsigned long main_clock
)
647 * USB clock init: choose 480 MHz from UPLL,
649 unsigned int usbr
= AT91_PMC_USBS_UPLL
;
651 /* Setup divider by 10 to reach 48 MHz */
652 usbr
|= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV
;
654 at91_sys_write(AT91_PMC_USB
, usbr
);
656 /* Now set uhpck values */
657 uhpck
.parent
= &utmi_clk
;
658 uhpck
.pmc_mask
= AT91SAM926x_PMC_UHP
;
659 uhpck
.rate_hz
= utmi_clk
.parent
->rate_hz
;
660 uhpck
.rate_hz
/= 1 + ((at91_sys_read(AT91_PMC_USB
) & AT91_PMC_OHCIUSBDIV
) >> 8);
663 int __init
at91_clock_init(unsigned long main_clock
)
665 unsigned tmp
, freq
, mckr
;
667 int pll_overclock
= false;
670 * When the bootloader initialized the main oscillator correctly,
671 * there's no problem using the cycle counter. But if it didn't,
672 * or when using oscillator bypass mode, we must be told the speed
677 tmp
= at91_sys_read(AT91_CKGR_MCFR
);
678 } while (!(tmp
& AT91_PMC_MAINRDY
));
679 main_clock
= (tmp
& AT91_PMC_MAINF
) * (AT91_SLOW_CLOCK
/ 16);
681 main_clk
.rate_hz
= main_clock
;
683 /* report if PLLA is more than mildly overclocked */
684 plla
.rate_hz
= at91_pll_rate(&plla
, main_clock
, at91_sys_read(AT91_CKGR_PLLAR
));
685 if (cpu_has_300M_plla()) {
686 if (plla
.rate_hz
> 300000000)
687 pll_overclock
= true;
688 } else if (cpu_has_800M_plla()) {
689 if (plla
.rate_hz
> 800000000)
690 pll_overclock
= true;
692 if (plla
.rate_hz
> 209000000)
693 pll_overclock
= true;
696 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla
.rate_hz
/ 1000000);
698 if (cpu_is_at91sam9g45()) {
699 mckr
= at91_sys_read(AT91_PMC_MCKR
);
700 plla
.rate_hz
/= (1 << ((mckr
& AT91_PMC_PLLADIV2
) >> 12)); /* plla divisor by 2 */
703 if (!cpu_has_pllb() && cpu_has_upll()) {
704 /* setup UTMI clock as the fourth primary clock
705 * (instead of pllb) */
706 utmi_clk
.type
|= CLK_TYPE_PRIMARY
;
716 * multiplier is hard-wired to 40
717 * (obtain the USB High Speed 480 MHz when input is 12 MHz)
719 utmi_clk
.rate_hz
= 40 * utmi_clk
.parent
->rate_hz
;
725 at91_pllb_usbfs_clock_init(main_clock
);
727 /* assumes that we choose UPLL for USB and not PLLA */
728 at91_upll_usbfs_clock_init(main_clock
);
731 * MCK and CPU derive from one of those primary clocks.
732 * For now, assume this parentage won't change.
734 mckr
= at91_sys_read(AT91_PMC_MCKR
);
735 mck
.parent
= at91_css_to_clk(mckr
& AT91_PMC_CSS
);
736 freq
= mck
.parent
->rate_hz
;
737 freq
/= (1 << ((mckr
& AT91_PMC_PRES
) >> 2)); /* prescale */
738 if (cpu_is_at91rm9200()) {
739 mck
.rate_hz
= freq
/ (1 + ((mckr
& AT91_PMC_MDIV
) >> 8)); /* mdiv */
740 } else if (cpu_is_at91sam9g20()) {
741 mck
.rate_hz
= (mckr
& AT91_PMC_MDIV
) ?
742 freq
/ ((mckr
& AT91_PMC_MDIV
) >> 7) : freq
; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
743 if (mckr
& AT91_PMC_PDIV
)
744 freq
/= 2; /* processor clock division */
745 } else if (cpu_is_at91sam9g45()) {
746 mck
.rate_hz
= (mckr
& AT91_PMC_MDIV
) == AT91SAM9_PMC_MDIV_3
?
747 freq
/ 3 : freq
/ (1 << ((mckr
& AT91_PMC_MDIV
) >> 8)); /* mdiv */
749 mck
.rate_hz
= freq
/ (1 << ((mckr
& AT91_PMC_MDIV
) >> 8)); /* mdiv */
752 /* Register the PMC's standard clocks */
753 for (i
= 0; i
< ARRAY_SIZE(standard_pmc_clocks
); i
++)
754 list_add_tail(&standard_pmc_clocks
[i
]->node
, &clocks
);
757 list_add_tail(&pllb
.node
, &clocks
);
760 list_add_tail(&uhpck
.node
, &clocks
);
763 list_add_tail(&udpck
.node
, &clocks
);
766 list_add_tail(&utmi_clk
.node
, &clocks
);
768 /* MCK and CPU clock are "always on" */
771 printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
772 freq
/ 1000000, (unsigned) mck
.rate_hz
/ 1000000,
773 (unsigned) main_clock
/ 1000000,
774 ((unsigned) main_clock
% 1000000) / 1000);
780 * Several unused clocks may be active. Turn them off.
782 static int __init
at91_clock_reset(void)
784 unsigned long pcdr
= 0;
785 unsigned long scdr
= 0;
788 list_for_each_entry(clk
, &clocks
, node
) {
792 if (clk
->mode
== pmc_periph_mode
)
793 pcdr
|= clk
->pmc_mask
;
795 if (clk
->mode
== pmc_sys_mode
)
796 scdr
|= clk
->pmc_mask
;
798 pr_debug("Clocks: disable unused %s\n", clk
->name
);
801 at91_sys_write(AT91_PMC_PCDR
, pcdr
);
802 at91_sys_write(AT91_PMC_SCDR
, scdr
);
806 late_initcall(at91_clock_reset
);