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Full support for Ginger Console
[linux-ginger.git] / arch / arm / mach-omap2 / board-am3517evm.c
blobd1d5ef36855defdefc7b1651a274a08a22c8cea4
1 /*
2 * linux/arch/arm/mach-omap2/board-am3517evm.c
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated
5 * Authot: Ranjith Lohithakshan <ranjithl@ti.com>
6 *
7 * Based on mach-omap2/board-omap3evm.c
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation version 2.
12 *
13 * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
14 * whether express or implied; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 */
18
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
22 #include <linux/gpio.h>
23 #include <linux/davinci_emac.h>
24 #include <linux/irq.h>
25 #include <linux/i2c/tsc2004.h>
26
27 #include <linux/mtd/mtd.h>
28 #include <linux/mtd/partitions.h>
29 #include <linux/mtd/nand.h>
30
31
32 #include <mach/hardware.h>
33 #include <asm/mach-types.h>
34 #include <asm/mach/arch.h>
35 #include <asm/mach/map.h>
36
37 #include <plat/board.h>
38 #include <plat/mux.h>
39 #include <plat/common.h>
40 #include <plat/control.h>
41 #include <plat/display.h>
42 #include <plat/usb.h>
43 #include <plat/mux.h>
44 #include <plat/am3517.h>
45 #include <plat/gpmc.h>
46 #include <plat/nand.h>
47
48
49 #include <media/ti-media/vpfe_capture.h>
50 #include <media/tvp514x.h>
51 #include <linux/can/platform/ti_hecc.h>
52
53 #include "mmc-am3517evm.h"
54 #include "board-omap35x-pmic.h"
55
56 #define GPMC_CS0_BASE 0x60
57 #define GPMC_CS_SIZE 0x30
58
59 #define NAND_BLOCK_SIZE SZ_128K
60
61 static struct mtd_partition am3517evm_nand_partitions[] = {
62 /* All the partition sizes are listed in terms of NAND block size */
63 {
64 .name = "xloader-nand",
65 .offset = 0,
66 .size = 4*(SZ_128K),
67 .mask_flags = MTD_WRITEABLE
68 },
69 {
70 .name = "uboot-nand",
71 .offset = MTDPART_OFS_APPEND,
72 .size = 14*(SZ_128K),
73 .mask_flags = MTD_WRITEABLE
74 },
75 {
76 .name = "params-nand",
77 .offset = MTDPART_OFS_APPEND,
78 .size = 2*(SZ_128K)
79 },
80 {
81 .name = "linux-nand",
82 .offset = MTDPART_OFS_APPEND,
83 .size = 40*(SZ_128K)
84 },
85 {
86 .name = "jffs2-nand",
87 .size = MTDPART_SIZ_FULL,
88 .offset = MTDPART_OFS_APPEND,
89 },
90 };
91
92 static struct omap_nand_platform_data am3517evm_nand_data = {
93 .parts = am3517evm_nand_partitions,
94 .nr_parts = ARRAY_SIZE(am3517evm_nand_partitions),
95 .nand_setup = NULL,
96 .dma_channel = -1, /* disable DMA in OMAP NAND driver */
97 .dev_ready = NULL,
98 };
99
100 static struct resource am3517evm_nand_resource = {
101 .flags = IORESOURCE_MEM,
102 };
103
104 static struct platform_device am3517evm_nand_device = {
105 .name = "omap2-nand",
106 .id = 0,
107 .dev = {
108 .platform_data = &am3517evm_nand_data,
109 },
110 .num_resources = 1,
111 .resource = &am3517evm_nand_resource,
112 };
113
114 void __init am3517evm_flash_init(void)
115 {
116 u8 cs = 0;
117 u8 nandcs = GPMC_CS_NUM + 1;
118 u32 gpmc_base_add = OMAP34XX_GPMC_VIRT;
119
120 while (cs < GPMC_CS_NUM) {
121 u32 ret = 0;
122 ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
123
124 if ((ret & 0xC00) == 0x800) {
125 /* Found it!! */
126 if (nandcs > GPMC_CS_NUM)
127 nandcs = cs;
128 }
129 cs++;
130 }
131 if (nandcs > GPMC_CS_NUM) {
132 printk(KERN_INFO "NAND: Unable to find configuration "
133 " in GPMC\n ");
134 return;
135 }
136
137 if (nandcs < GPMC_CS_NUM) {
138 am3517evm_nand_data.cs = nandcs;
139 am3517evm_nand_data.gpmc_cs_baseaddr = (void *)(gpmc_base_add +
140 GPMC_CS0_BASE + nandcs*GPMC_CS_SIZE);
141 am3517evm_nand_data.gpmc_baseaddr = (void *) (gpmc_base_add);
142
143 if (platform_device_register(&am3517evm_nand_device) < 0)
144 printk(KERN_ERR "Unable to register NAND device\n");
145
146 }
147 }
148
149 #define AM3517_EVM_PHY_MASK (0xF)
150 #define AM3517_EVM_MDIO_FREQUENCY (1000000) /*PHY bus frequency */
151
152 static struct emac_platform_data am3517_evm_emac_pdata = {
153 .phy_mask = AM3517_EVM_PHY_MASK,
154 .mdio_max_freq = AM3517_EVM_MDIO_FREQUENCY,
155 .rmii_en = 1,
156 };
157
158 static int __init eth_addr_setup(char *str)
159 {
160 int i;
161
162 if(str == NULL)
163 return 0;
164 for(i = 0; i < ETH_ALEN; i++)
165 am3517_evm_emac_pdata.mac_addr[i] = simple_strtol(&str[i*3],
166 (char **)NULL, 16);
167 return 1;
168 }
169
170 /* Get MAC address from kernel boot parameter eth=AA:BB:CC:DD:EE:FF */
171 __setup("eth=", eth_addr_setup);
172
173 static struct resource am3517_emac_resources[] = {
174 {
175 .start = AM3517_IPSS_EMAC_BASE,
176 .end = AM3517_IPSS_EMAC_BASE + 0x3FFFF,
177 .flags = IORESOURCE_MEM,
178 },
179 {
180 .start = INT_3517_EMAC_RXTHRESH_IRQ,
181 .end = INT_3517_EMAC_RXTHRESH_IRQ,
182 .flags = IORESOURCE_IRQ,
183 },
184 {
185 .start = INT_3517_EMAC_RX_IRQ,
186 .end = INT_3517_EMAC_RX_IRQ,
187 .flags = IORESOURCE_IRQ,
188 },
189 {
190 .start = INT_3517_EMAC_TX_IRQ,
191 .end = INT_3517_EMAC_TX_IRQ,
192 .flags = IORESOURCE_IRQ,
193 },
194 {
195 .start = INT_3517_EMAC_MISC_IRQ,
196 .end = INT_3517_EMAC_MISC_IRQ,
197 .flags = IORESOURCE_IRQ,
198 },
199 };
200
201 static struct platform_device am3517_emac_device = {
202 .name = "davinci_emac",
203 .id = 1,
204 .num_resources = ARRAY_SIZE(am3517_emac_resources),
205 .resource = am3517_emac_resources,
206 };
207
208 static void am3517_enable_ethernet_int(void)
209 {
210 u32 regval;
211
212 regval = omap_ctrl_readl(OMAP3517_CONTROL_LVL_INTR_CLEAR);
213 regval = (regval | AM3517_CPGMAC_RX_PULSE_CLR |
214 AM3517_CPGMAC_TX_PULSE_CLR | AM3517_CPGMAC_MISC_PULSE_CLR |
215 AM3517_CPGMAC_RX_THRESH_CLR);
216 omap_ctrl_writel(regval,OMAP3517_CONTROL_LVL_INTR_CLEAR);
217 regval = omap_ctrl_readl(OMAP3517_CONTROL_LVL_INTR_CLEAR);
218
219 }
220
221 static void am3517_disable_ethernet_int(void)
222 {
223 u32 regval;
224
225 regval = omap_ctrl_readl(OMAP3517_CONTROL_LVL_INTR_CLEAR);
226 regval = (regval | AM3517_CPGMAC_RX_PULSE_CLR |
227 AM3517_CPGMAC_TX_PULSE_CLR);
228 omap_ctrl_writel(regval,OMAP3517_CONTROL_LVL_INTR_CLEAR);
229 regval = omap_ctrl_readl(OMAP3517_CONTROL_LVL_INTR_CLEAR);
230
231 }
232
233 void am3517_evm_ethernet_init(struct emac_platform_data *pdata)
234 {
235 unsigned int regval;
236
237 pdata->ctrl_reg_offset = AM3517_EMAC_CNTRL_OFFSET;
238 pdata->ctrl_mod_reg_offset = AM3517_EMAC_CNTRL_MOD_OFFSET;
239 pdata->ctrl_ram_offset = AM3517_EMAC_CNTRL_RAM_OFFSET;
240 pdata->mdio_reg_offset = AM3517_EMAC_MDIO_OFFSET;
241 pdata->ctrl_ram_size = AM3517_EMAC_CNTRL_RAM_SIZE;
242 pdata->version = EMAC_VERSION_2;
243 pdata->hw_ram_addr = AM3517_EMAC_HW_RAM_ADDR;
244 pdata->wrapper_interrupt_enable = am3517_enable_ethernet_int;
245 pdata->wrapper_interrupt_disable= am3517_disable_ethernet_int;
246 am3517_emac_device.dev.platform_data = pdata;
247 platform_device_register(&am3517_emac_device);
248
249 regval = omap_ctrl_readl(OMAP3517_CONTROL_IP_SW_RESET);
250 regval = regval & (~(AM3517_CPGMAC_SW_RST));
251 omap_ctrl_writel(regval,OMAP3517_CONTROL_IP_SW_RESET);
252 regval = omap_ctrl_readl(OMAP3517_CONTROL_IP_SW_RESET);
253
254 regval = omap_ctrl_readl(OMAP3517_CONTROL_IP_CLK_CTRL);
255 regval = regval |(1 << OMAP3517_CPGMAC_VBUSP_CLK_SHIFT) |
256 (1 << OMAP3517_CPGMAC_FCLK_SHIFT);
257 omap_ctrl_writel(regval,OMAP3517_CONTROL_IP_CLK_CTRL);
258 regval = omap_ctrl_readl(OMAP3517_CONTROL_IP_CLK_CTRL);
259 return ;
260 }
261
262
263 /*
264 * TSC 2004 Support
265 */
266 #define GPIO_TSC2004_IRQ 65
267
268 static int tsc2004_init_irq(void)
269 {
270 int ret = 0;
271
272 ret = gpio_request(GPIO_TSC2004_IRQ, "tsc2004-irq");
273 if (ret < 0) {
274 printk(KERN_WARNING "failed to request GPIO#%d: %d\n",
275 GPIO_TSC2004_IRQ, ret);
276 return ret;
277 }
278
279 if (gpio_direction_input(GPIO_TSC2004_IRQ)) {
280 printk(KERN_WARNING "GPIO#%d cannot be configured as "
281 "input\n", GPIO_TSC2004_IRQ);
282 return -ENXIO;
283 }
284
285 omap_set_gpio_debounce(GPIO_TSC2004_IRQ, 1);
286 omap_set_gpio_debounce_time(GPIO_TSC2004_IRQ, 0xa);
287 return ret;
288 }
289
290 static void tsc2004_exit_irq(void)
291 {
292 gpio_free(GPIO_TSC2004_IRQ);
293 }
294
295 static int tsc2004_get_irq_level(void)
296 {
297 return gpio_get_value(GPIO_TSC2004_IRQ) ? 0 : 1;
298 }
299
300 struct tsc2004_platform_data am3517evm_tsc2004data = {
301 .model = 2004,
302 .x_plate_ohms = 180,
303 .get_pendown_state = tsc2004_get_irq_level,
304 .init_platform_hw = tsc2004_init_irq,
305 .exit_platform_hw = tsc2004_exit_irq,
306 };
307
308 /*
309 * RTC - S35390A
310 */
311 #define GPIO_RTCS35390A_IRQ 55
312
313 static struct i2c_board_info __initdata am3517evm_i2c_boardinfo[] = {
314 {
315 I2C_BOARD_INFO("tsc2004", 0x4B),
316 .type = "tsc2004",
317 .platform_data = &am3517evm_tsc2004data,
318 },
319 {
320 I2C_BOARD_INFO("s35390a", 0x30),
321 .type = "s35390a",
322 },
323 };
324
325 /*
326 * VPFE - Video Decoder interface
327 */
328 #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
329 /* Inputs available at the TVP5146 */
330 static struct v4l2_input tvp5146_inputs[] = {
331 {
332 .index = 0,
333 .name = "Composite",
334 .type = V4L2_INPUT_TYPE_CAMERA,
335 .std = TVP514X_STD_ALL,
336 },
337 {
338 .index = 1,
339 .name = "S-Video",
340 .type = V4L2_INPUT_TYPE_CAMERA,
341 .std = TVP514X_STD_ALL,
342 },
343 };
344
345 static struct vpfe_route tvp5146_routes[] = {
346 {
347 .input = INPUT_CVBS_VI1A,
348 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
349 },
350 {
351 .input = INPUT_SVIDEO_VI2C_VI1C,
352 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
353 },
354 };
355
356 static struct tvp514x_platform_data tvp5146_pdata = {
357 .clk_polarity = 0,
358 .hs_polarity = 1,
359 .vs_polarity = 1
360 };
361
362 static struct vpfe_subdev_info vpfe_sub_devs[] = {
363 {
364 .module_name = TVP514X_MODULE_NAME,
365 .grp_id = VPFE_SUBDEV_TVP5146,
366 .num_inputs = ARRAY_SIZE(tvp5146_inputs),
367 .inputs = tvp5146_inputs,
368 .routes = tvp5146_routes,
369 .can_route = 1,
370 .ccdc_if_params = {
371 .if_type = VPFE_BT656_10BIT,
372 .hdpol = VPFE_PINPOL_POSITIVE,
373 .vdpol = VPFE_PINPOL_POSITIVE,
374 },
375 .board_info = {
376 I2C_BOARD_INFO("tvp5146", 0x5C),
377 .platform_data = &tvp5146_pdata,
378 },
379 },
380 };
381
382 static void am3517_evm_clear_vpfe_intr(int vdint)
383 {
384 unsigned int vpfe_int_clr;
385
386 vpfe_int_clr = omap_ctrl_readl(OMAP3517_CONTROL_LVL_INTR_CLEAR);
387
388 switch (vdint) {
389 /* VD0 interrrupt */
390 case INT_3517_CCDC_VD0_IRQ:
391 vpfe_int_clr &= ~AM3517_VPFE_VD0_INT_CLR;
392 vpfe_int_clr |= AM3517_VPFE_VD0_INT_CLR;
393 break;
394 /* VD1 interrrupt */
395 case INT_3517_CCDC_VD1_IRQ:
396 vpfe_int_clr &= ~AM3517_VPFE_VD1_INT_CLR;
397 vpfe_int_clr |= AM3517_VPFE_VD1_INT_CLR;
398 break;
399 /* VD2 interrrupt */
400 case INT_3517_CCDC_VD2_IRQ:
401 vpfe_int_clr &= ~AM3517_VPFE_VD2_INT_CLR;
402 vpfe_int_clr |= AM3517_VPFE_VD2_INT_CLR;
403 break;
404 /* Clear all interrrupts */
405 default:
406 vpfe_int_clr &= ~(AM3517_VPFE_VD0_INT_CLR |
407 AM3517_VPFE_VD1_INT_CLR |
408 AM3517_VPFE_VD2_INT_CLR);
409 vpfe_int_clr |= (AM3517_VPFE_VD0_INT_CLR |
410 AM3517_VPFE_VD1_INT_CLR |
411 AM3517_VPFE_VD2_INT_CLR);
412 break;
413 }
414
415 omap_ctrl_writel(vpfe_int_clr, OMAP3517_CONTROL_LVL_INTR_CLEAR);
416 vpfe_int_clr = omap_ctrl_readl(OMAP3517_CONTROL_LVL_INTR_CLEAR);
417 }
418
419 static struct resource vpfe_resources[] = {
420 {
421 .start = INT_3517_CCDC_VD0_IRQ,
422 .end = INT_3517_CCDC_VD0_IRQ,
423 .flags = IORESOURCE_IRQ,
424 },
425 {
426 .start = INT_3517_CCDC_VD1_IRQ,
427 .end = INT_3517_CCDC_VD1_IRQ,
428 .flags = IORESOURCE_IRQ,
429 },
430 {
431 .start = AM3517_IPSS_VPFE_BASE,
432 .end = AM3517_IPSS_VPFE_BASE + 0xffff,
433 .flags = IORESOURCE_MEM,
434 },
435
436 {
437 .start = OMAP3517_CONTROL_LVL_INTR_CLEAR,
438 .end = OMAP3517_CONTROL_LVL_INTR_CLEAR + 0x4,
439 .flags = IORESOURCE_MEM,
440 },
441 };
442
443 static struct vpfe_config vpfe_cfg = {
444 .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
445 .sub_devs = vpfe_sub_devs,
446 .card_name = "AM3517 EVM",
447 .ccdc = "DM6446 CCDC",
448 .clr_intr = am3517_evm_clear_vpfe_intr,
449 .num_clocks = 2,
450 .clocks = {"vpfe_ck", "vpfe_pck"},
451 .i2c_adapter_id = 3,
452 };
453
454
455 static u64 vpfe_dma_mask = DMA_BIT_MASK(32);
456
457 static struct platform_device vpfe_capture_dev = {
458 .name = CAPTURE_DRV_NAME,
459 .id = -1,
460 .num_resources = ARRAY_SIZE(vpfe_resources),
461 .resource = vpfe_resources,
462 .dev = {
463 .dma_mask = &vpfe_dma_mask,
464 .coherent_dma_mask = DMA_BIT_MASK(32),
465 .platform_data = &vpfe_cfg,
466 },
467 };
468
469 #define LCD_PANEL_PWR 176
470 #define LCD_PANEL_BKLIGHT_PWR 182
471 #define LCD_PANEL_PWM 181
472
473 static int lcd_enabled;
474 static int dvi_enabled;
475
476 static void __init am3517_evm_display_init(void)
477 {
478 int r;
479
480 /*
481 * Enable GPIO 182 = LCD Backlight Power
482 */
483 r = gpio_request(LCD_PANEL_BKLIGHT_PWR, "lcd_backlight_pwr");
484 if (r) {
485 printk(KERN_ERR "failed to get lcd_backlight_pwr\n");
486 return;
487 }
488 gpio_direction_output(LCD_PANEL_BKLIGHT_PWR, 1);
489 /*
490 * Enable GPIO 181 = LCD Panel PWM
491 */
492 r = gpio_request(LCD_PANEL_PWM, "lcd_pwm");
493 if (r) {
494 printk(KERN_ERR "failed to get lcd_pwm\n");
495 goto err_1;
496 }
497 gpio_direction_output(LCD_PANEL_PWM, 1);
498 /*
499 * Enable GPIO 176 = LCD Panel Power enable pin
500 */
501 r = gpio_request(LCD_PANEL_PWR, "lcd_panel_pwr");
502 if (r) {
503 printk(KERN_ERR "failed to get lcd_panel_pwr\n");
504 goto err_2;
505 }
506 gpio_direction_output(LCD_PANEL_PWR, 1);
507
508 printk(KERN_INFO "Display initialized successfully\n");
509 return;
510
511 err_2:
512 gpio_free(LCD_PANEL_PWM);
513 err_1:
514 gpio_free(LCD_PANEL_BKLIGHT_PWR);
515 }
516
517 static int am3517_evm_panel_enable_lcd(struct omap_dss_device *dssdev)
518 {
519 if (dvi_enabled) {
520 printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
521 return -EINVAL;
522 }
523 gpio_set_value(LCD_PANEL_PWR, 1);
524 lcd_enabled = 1;
525
526 return 0;
527 }
528
529 static void am3517_evm_panel_disable_lcd(struct omap_dss_device *dssdev)
530 {
531 gpio_set_value(LCD_PANEL_PWR, 0);
532 lcd_enabled = 0;
533 }
534
535 static struct omap_dss_device am3517_evm_lcd_device = {
536 .type = OMAP_DISPLAY_TYPE_DPI,
537 .name = "lcd",
538 .driver_name = "sharp_lq_panel",
539 .phy.dpi.data_lines = 16,
540 .platform_enable = am3517_evm_panel_enable_lcd,
541 .platform_disable = am3517_evm_panel_disable_lcd,
542 };
543
544 static int am3517_evm_panel_enable_tv(struct omap_dss_device *dssdev)
545 {
546 return 0;
547 }
548
549 static void am3517_evm_panel_disable_tv(struct omap_dss_device *dssdev)
550 {
551 }
552
553 static struct omap_dss_device am3517_evm_tv_device = {
554 .type = OMAP_DISPLAY_TYPE_VENC,
555 .name = "tv",
556 .driver_name = "venc",
557 .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
558 .platform_enable = am3517_evm_panel_enable_tv,
559 .platform_disable = am3517_evm_panel_disable_tv,
560 };
561
562 static int am3517_evm_panel_enable_dvi(struct omap_dss_device *dssdev)
563 {
564 if (lcd_enabled) {
565 printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
566 return -EINVAL;
567 }
568 dvi_enabled = 1;
569
570 return 0;
571 }
572
573 static void am3517_evm_panel_disable_dvi(struct omap_dss_device *dssdev)
574 {
575 dvi_enabled = 0;
576 }
577
578 static struct omap_dss_device am3517_evm_dvi_device = {
579 .type = OMAP_DISPLAY_TYPE_DPI,
580 .name = "dvi",
581 .driver_name = "generic_panel",
582 .phy.dpi.data_lines = 24,
583 .platform_enable = am3517_evm_panel_enable_dvi,
584 .platform_disable = am3517_evm_panel_disable_dvi,
585 };
586
587 static struct omap_dss_device *am3517_evm_dss_devices[] = {
588 &am3517_evm_lcd_device,
589 &am3517_evm_tv_device,
590 &am3517_evm_dvi_device,
591 };
592
593 static struct omap_dss_board_info am3517_evm_dss_data = {
594 .num_devices = ARRAY_SIZE(am3517_evm_dss_devices),
595 .devices = am3517_evm_dss_devices,
596 .default_device = &am3517_evm_lcd_device,
597 };
598
599 struct platform_device am3517_evm_dss_device = {
600 .name = "omapdss",
601 .id = -1,
602 .dev = {
603 .platform_data = &am3517_evm_dss_data,
604 },
605 };
606
607 /* PMIC specific initialization */
608 /* Consumers -> Supplies mapping */
609 /* VDCDC1 -> VDD_CORE */
610 REGULATOR_CONSUMER_SINGLE_SUPPLY(vdcdc1, vdd_core, NULL);
611 /* VDCDC2 -> VDDSHV */
612 REGULATOR_CONSUMER_SINGLE_SUPPLY(vdcdc2, vddshv, NULL);
613 /* VDCDC2 |-> VDDS
614 |-> VDDS_SRAM_CORE_BG
615 |-> VDDS_SRAM_MPU */
616 REGULATOR_COMSUMER_START(vdcdc3) = {
617 REGULATOR_COMSUMER_DEFINE(vdds, NULL),
618 REGULATOR_COMSUMER_DEFINE(vdds_sram_core_bg, NULL),
619 REGULATOR_COMSUMER_DEFINE(vdds_sram_mpu, NULL),
620 };
621 /* LDO1 |-> VDDA1P8V_USBPHY
622 |-> VDDA_DAC */
623 REGULATOR_COMSUMER_START(vldo1) = {
624 REGULATOR_COMSUMER_DEFINE(vdda1p8v_usbphy, NULL),
625 REGULATOR_COMSUMER_DEFINE(vdda_dac, NULL),
626 };
627 /* LDO2 -> VDDA3P3V_USBPHY */
628 REGULATOR_CONSUMER_SINGLE_SUPPLY(vldo2, vdda3p3v_usbphy, NULL);
629
630 /* Regulator initialization data */
631 REGULATOR_INIT_DATA_START(tps65023) = {
632 /* VDCDC1 */
633 REGULATOR_INIT_DATA_DEFINE(vdcdc1, VDD_CORE, 1200000, 1200000,
634 REGULATOR_MODE_NORMAL, REGULATOR_CHANGE_STATUS,
635 true, false),
636 /* VDCDC2 */
637 REGULATOR_INIT_DATA_DEFINE(vdcdc2, VDDSHV, 3300000, 3300000,
638 REGULATOR_MODE_NORMAL, REGULATOR_CHANGE_STATUS,
639 true, false),
640 /* VDCDC3 */
641 REGULATOR_INIT_DATA_DEFINE(vdcdc3, VDDS, 1800000, 1800000,
642 REGULATOR_MODE_NORMAL, REGULATOR_CHANGE_STATUS,
643 true, false),
644 /* LDO1 */
645 REGULATOR_INIT_DATA_DEFINE(vldo1, VDAC/VUSBPHY, 1800000, 1800000,
646 REGULATOR_MODE_NORMAL, REGULATOR_CHANGE_STATUS,
647 false, false),
648 /* LDO2 */
649 REGULATOR_INIT_DATA_DEFINE(vldo2, VUSBPHY, 3300000, 3300000,
650 REGULATOR_MODE_NORMAL, REGULATOR_CHANGE_STATUS,
651 false, false),
652 };
653
654 /* I2C1 */
655 static struct i2c_board_info __initdata am3517evm_i2c1_boardinfo[] = {
656 {
657 I2C_BOARD_INFO("tps65023", 0x48),
658 .flags = I2C_CLIENT_WAKE,
659 .platform_data = &tps65023_data[0],
660 },
661 };
662 /* I2C2 */
663 static struct i2c_board_info __initdata am3517evm_i2c2_boardinfo[] = {
664 {
665 I2C_BOARD_INFO("tlv320aic23", 0x1A),
666 },
667 };
668
669 static int __init am3517_evm_i2c_init(void)
670 {
671 omap_register_i2c_bus(1, 400, am3517evm_i2c1_boardinfo,
672 ARRAY_SIZE(am3517evm_i2c1_boardinfo));
673 omap_register_i2c_bus(2, 400, am3517evm_i2c2_boardinfo,
674 ARRAY_SIZE(am3517evm_i2c2_boardinfo));
675 omap_register_i2c_bus(3, 400, NULL, 0);
676
677 return 0;
678 }
679
680 /*
681 * HECC information
682 */
683
684 static struct resource am3517_hecc_resources[] = {
685 {
686 .start = AM3517_IPSS_HECC_BASE,
687 .end = AM3517_IPSS_HECC_BASE + 0x3FFF,
688 .flags = IORESOURCE_MEM,
689 },
690 {
691 .start = INT_3517_HECC0_IRQ,
692 .end = INT_3517_HECC0_IRQ,
693 .flags = IORESOURCE_IRQ,
694 },
695 };
696
697 static struct platform_device am3517_hecc_device = {
698 .name = "ti_hecc",
699 .id = 1,
700 .num_resources = ARRAY_SIZE(am3517_hecc_resources),
701 .resource = am3517_hecc_resources,
702 };
703
704 static struct ti_hecc_platform_data am3517_evm_hecc_pdata = {
705 .scc_hecc_offset = AM3517_HECC_SCC_HECC_OFFSET,
706 .scc_ram_offset = AM3517_HECC_SCC_RAM_OFFSET,
707 .hecc_ram_offset = AM3517_HECC_RAM_OFFSET,
708 .mbx_offset = AM3517_HECC_MBOX_OFFSET,
709 .int_line = AM3517_HECC_INT_LINE,
710 .version = AM3517_HECC_VERSION,
711 };
712
713 static void am3517_evm_hecc_init(struct ti_hecc_platform_data *pdata)
714 {
715 am3517_hecc_device.dev.platform_data = pdata;
716 platform_device_register(&am3517_hecc_device);
717 }
718
719
720 /*
721 * Board initialization
722 */
723 static struct omap_board_config_kernel am3517_evm_config[] __initdata = {
724 };
725
726 static struct platform_device *am3517_evm_devices[] __initdata = {
727 &am3517_evm_dss_device,
728 &vpfe_capture_dev,
729 };
730
731 static void __init am3517_evm_init_irq(void)
732 {
733 omap_board_config = am3517_evm_config;
734 omap_board_config_size = ARRAY_SIZE(am3517_evm_config);
735
736 omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL);
737 omap_init_irq();
738 omap_gpio_init();
739 }
740
741 static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = {
742
743 .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
744 #if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \
745 defined(CONFIG_PANEL_SHARP_LQ043T1DG01_MODULE)
746 .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN,
747 #else
748 .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
749 #endif
750 .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
751
752 .phy_reset = true,
753 .reset_gpio_port[0] = 57,
754 .reset_gpio_port[1] = -EINVAL,
755 .reset_gpio_port[2] = -EINVAL
756 };
757
758 static struct am3517_hsmmc_info mmc[] = {
759 {
760 .mmc = 1,
761 .wires = 4,
762 /*TODO: Need to change*/
763 .gpio_cd = 127,
764 .gpio_wp = 126,
765 },
766 {
767 .mmc = 2,
768 .wires = 4,
769 /*TODO: Need to change*/
770 .gpio_cd = 128,
771 .gpio_wp = 129,
772 },
773 {} /* Terminator */
774 };
775
776 static void __init am3517_evm_init(void)
777 {
778 am3517_evm_i2c_init();
779
780 regulator_has_full_constraints();
781
782 platform_add_devices(am3517_evm_devices,
783 ARRAY_SIZE(am3517_evm_devices));
784 omap_serial_init();
785 am3517evm_flash_init();
786
787 am3517_evm_display_init();
788
789 usb_musb_init();
790 /* Setup EHCI phy reset padconfig for port1 using GPIO57 */
791 omap_cfg_reg(N5_3517_GPIO57_OUT);
792 usb_ehci_init(&ehci_pdata);
793
794 /* MMC init function */
795 am3517_mmc_init(mmc);
796
797 am3517_evm_ethernet_init(&am3517_evm_emac_pdata);
798 am3517_evm_hecc_init(&am3517_evm_hecc_pdata);
799
800 /* TSC 2004 */
801 omap_cfg_reg(U1_34XX_GPIO65);
802 am3517evm_i2c_boardinfo[0].irq = gpio_to_irq(GPIO_TSC2004_IRQ);
803 /* RTC - S35390A */
804 omap_cfg_reg(M2_34XX_GPIO55);
805 if (gpio_request(GPIO_RTCS35390A_IRQ, "rtcs35390a-irq") < 0)
806 printk(KERN_WARNING "failed to request GPIO#%d\n",
807 GPIO_RTCS35390A_IRQ);
808 if (gpio_direction_input(GPIO_RTCS35390A_IRQ))
809 printk(KERN_WARNING "GPIO#%d cannot be configured as "
810 "input\n", GPIO_RTCS35390A_IRQ);
811 am3517evm_i2c_boardinfo[1].irq = gpio_to_irq(GPIO_RTCS35390A_IRQ);
812
813 i2c_register_board_info(1, am3517evm_i2c_boardinfo,
814 ARRAY_SIZE(am3517evm_i2c_boardinfo));
815
816
817 }
818
819 static void __init am3517_evm_map_io(void)
820 {
821 omap2_set_globals_343x();
822 omap2_map_common_io();
823 }
824
825 MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
826 .phys_io = 0x48000000,
827 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
828 .boot_params = 0x80000100,
829 .map_io = am3517_evm_map_io,
830 .init_irq = am3517_evm_init_irq,
831 .init_machine = am3517_evm_init,
832 .timer = &omap_timer,
833 MACHINE_END
Linux for Ginger Game Console