arch/arm/mach-omap2/control.c

   1 /*
   2  * OMAP2/3 System Control Module register access
   3  *
   4  * Copyright (C) 2007 Texas Instruments, Inc.
   5  * Copyright (C) 2007 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13 #undef DEBUG
  14
  15 #include <linux/kernel.h>
  16 #include <linux/io.h>
  17
  18 #include <plat/common.h>
  19 #include <plat/control.h>
  20 #include <plat/sdrc.h>
  21 #include "cm-regbits-34xx.h"
  22 #include "prm-regbits-34xx.h"
  23 #include "cm.h"
  24 #include "prm.h"
  25 #include "sdrc.h"
  26
  27 static void __iomem *omap2_ctrl_base;
  28
  29 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
  30 struct omap3_scratchpad {
  31         u32 boot_config_ptr;
  32         u32 public_restore_ptr;
  33         u32 secure_ram_restore_ptr;
  34         u32 sdrc_module_semaphore;
  35         u32 prcm_block_offset;
  36         u32 sdrc_block_offset;
  37 };
  38
  39 struct omap3_scratchpad_prcm_block {
  40         u32 prm_clksrc_ctrl;
  41         u32 prm_clksel;
  42         u32 cm_clksel_core;
  43         u32 cm_clksel_wkup;
  44         u32 cm_clken_pll;
  45         u32 cm_autoidle_pll;
  46         u32 cm_clksel1_pll;
  47         u32 cm_clksel2_pll;
  48         u32 cm_clksel3_pll;
  49         u32 cm_clken_pll_mpu;
  50         u32 cm_autoidle_pll_mpu;
  51         u32 cm_clksel1_pll_mpu;
  52         u32 cm_clksel2_pll_mpu;
  53         u32 prcm_block_size;
  54 };
  55
  56 struct omap3_scratchpad_sdrc_block {
  57         u16 sysconfig;
  58         u16 cs_cfg;
  59         u16 sharing;
  60         u16 err_type;
  61         u32 dll_a_ctrl;
  62         u32 dll_b_ctrl;
  63         u32 power;
  64         u32 cs_0;
  65         u32 mcfg_0;
  66         u16 mr_0;
  67         u16 emr_1_0;
  68         u16 emr_2_0;
  69         u16 emr_3_0;
  70         u32 actim_ctrla_0;
  71         u32 actim_ctrlb_0;
  72         u32 rfr_ctrl_0;
  73         u32 cs_1;
  74         u32 mcfg_1;
  75         u16 mr_1;
  76         u16 emr_1_1;
  77         u16 emr_2_1;
  78         u16 emr_3_1;
  79         u32 actim_ctrla_1;
  80         u32 actim_ctrlb_1;
  81         u32 rfr_ctrl_1;
  82         u16 dcdl_1_ctrl;
  83         u16 dcdl_2_ctrl;
  84         u32 flags;
  85         u32 block_size;
  86 };
  87
  88 void *omap3_secure_ram_storage;
  89
  90 /*
  91  * This is used to store ARM registers in SDRAM before attempting
  92  * an MPU OFF. The save and restore happens from the SRAM sleep code.
  93  * The address is stored in scratchpad, so that it can be used
  94  * during the restore path.
  95  */
  96 u32 omap3_arm_context[128];
  97
  98 struct omap3_control_regs {
  99         u32 sysconfig;
 100         u32 devconf0;
 101         u32 mem_dftrw0;
 102         u32 mem_dftrw1;
 103         u32 msuspendmux_0;
 104         u32 msuspendmux_1;
 105         u32 msuspendmux_2;
 106         u32 msuspendmux_3;
 107         u32 msuspendmux_4;
 108         u32 msuspendmux_5;
 109         u32 sec_ctrl;
 110         u32 devconf1;
 111         u32 csirxfe;
 112         u32 iva2_bootaddr;
 113         u32 iva2_bootmod;
 114         u32 debobs_0;
 115         u32 debobs_1;
 116         u32 debobs_2;
 117         u32 debobs_3;
 118         u32 debobs_4;
 119         u32 debobs_5;
 120         u32 debobs_6;
 121         u32 debobs_7;
 122         u32 debobs_8;
 123         u32 prog_io0;
 124         u32 prog_io1;
 125         u32 dss_dpll_spreading;
 126         u32 core_dpll_spreading;
 127         u32 per_dpll_spreading;
 128         u32 usbhost_dpll_spreading;
 129         u32 pbias_lite;
 130         u32 temp_sensor;
 131         u32 sramldo4;
 132         u32 sramldo5;
 133         u32 csi;
 134 };
 135
 136 static struct omap3_control_regs control_context;
 137 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
 138
 139 #define OMAP_CTRL_REGADDR(reg)          (omap2_ctrl_base + (reg))
 140
 141 void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
 142 {
 143         omap2_ctrl_base = omap2_globals->ctrl;
 144 }
 145
 146 void __iomem *omap_ctrl_base_get(void)
 147 {
 148         return omap2_ctrl_base;
 149 }
 150
 151 u8 omap_ctrl_readb(u16 offset)
 152 {
 153         return __raw_readb(OMAP_CTRL_REGADDR(offset));
 154 }
 155 EXPORT_SYMBOL(omap_ctrl_readb);
 156
 157 u16 omap_ctrl_readw(u16 offset)
 158 {
 159         return __raw_readw(OMAP_CTRL_REGADDR(offset));
 160 }
 161 EXPORT_SYMBOL(omap_ctrl_readw);
 162
 163 u32 omap_ctrl_readl(u16 offset)
 164 {
 165         return __raw_readl(OMAP_CTRL_REGADDR(offset));
 166 }
 167 EXPORT_SYMBOL(omap_ctrl_readl);
 168
 169 void omap_ctrl_writeb(u8 val, u16 offset)
 170 {
 171         __raw_writeb(val, OMAP_CTRL_REGADDR(offset));
 172 }
 173 EXPORT_SYMBOL(omap_ctrl_writeb);
 174
 175 void omap_ctrl_writew(u16 val, u16 offset)
 176 {
 177         __raw_writew(val, OMAP_CTRL_REGADDR(offset));
 178 }
 179 EXPORT_SYMBOL(omap_ctrl_writew);
 180
 181 void omap_ctrl_writel(u32 val, u16 offset)
 182 {
 183         __raw_writel(val, OMAP_CTRL_REGADDR(offset));
 184 }
 185 EXPORT_SYMBOL(omap_ctrl_writel);
 186
 187 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
 188 /*
 189  * Clears the scratchpad contents in case of cold boot-
 190  * called during bootup
 191  */
 192 void omap3_clear_scratchpad_contents(void)
 193 {
 194         u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;
 195         u32 *v_addr;
 196         u32 offset = 0;
 197         v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
 198         if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
 199                 OMAP3430_GLOBAL_COLD_RST) {
 200                 for ( ; offset <= max_offset; offset += 0x4)
 201                         __raw_writel(0x0, (v_addr + offset));
 202                 prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST, OMAP3430_GR_MOD,
 203                         OMAP3_PRM_RSTST_OFFSET);
 204         }
 205 }
 206
 207 /* Populate the scratchpad structure with restore structure */
 208 void omap3_save_scratchpad_contents(void)
 209 {
 210         void * __iomem scratchpad_address;
 211         u32 arm_context_addr;
 212         struct omap3_scratchpad scratchpad_contents;
 213         struct omap3_scratchpad_prcm_block prcm_block_contents;
 214         struct omap3_scratchpad_sdrc_block sdrc_block_contents;
 215
 216         /* Populate the Scratchpad contents */
 217         scratchpad_contents.boot_config_ptr = 0x0;
 218         if (cpu_is_omap34xx()
 219                 && !omap_rev_is_3_0() && !omap_rev_is_3_1())
 220                 scratchpad_contents.public_restore_ptr =
 221                         virt_to_phys(get_restore_pointer());
 222         else
 223                 scratchpad_contents.public_restore_ptr =
 224                         virt_to_phys(get_es3_restore_pointer());
 225         if (omap_type() == OMAP2_DEVICE_TYPE_GP)
 226                 scratchpad_contents.secure_ram_restore_ptr = 0x0;
 227         else
 228                 scratchpad_contents.secure_ram_restore_ptr =
 229                         (u32) __pa(omap3_secure_ram_storage);
 230         scratchpad_contents.sdrc_module_semaphore = 0x0;
 231         scratchpad_contents.prcm_block_offset = 0x2C;
 232         scratchpad_contents.sdrc_block_offset = 0x64;
 233
 234         /* Populate the PRCM block contents */
 235         prcm_block_contents.prm_clksrc_ctrl = prm_read_mod_reg(OMAP3430_GR_MOD,
 236                         OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 237         prcm_block_contents.prm_clksel = prm_read_mod_reg(OMAP3430_CCR_MOD,
 238                         OMAP3_PRM_CLKSEL_OFFSET);
 239         prcm_block_contents.cm_clksel_core =
 240                         cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
 241         prcm_block_contents.cm_clksel_wkup =
 242                         cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
 243         prcm_block_contents.cm_clken_pll =
 244                         cm_read_mod_reg(PLL_MOD, CM_CLKEN);
 245         prcm_block_contents.cm_autoidle_pll =
 246                         cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL);
 247         prcm_block_contents.cm_clksel1_pll =
 248                         cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
 249         prcm_block_contents.cm_clksel2_pll =
 250                         cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
 251         prcm_block_contents.cm_clksel3_pll =
 252                         cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
 253         prcm_block_contents.cm_clken_pll_mpu =
 254                         cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
 255         prcm_block_contents.cm_autoidle_pll_mpu =
 256                         cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
 257         prcm_block_contents.cm_clksel1_pll_mpu =
 258                         cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
 259         prcm_block_contents.cm_clksel2_pll_mpu =
 260                         cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
 261         prcm_block_contents.prcm_block_size = 0x0;
 262
 263         /* Populate the SDRC block contents */
 264         sdrc_block_contents.sysconfig =
 265                         (sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF);
 266         sdrc_block_contents.cs_cfg =
 267                         (sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF);
 268         sdrc_block_contents.sharing =
 269                         (sdrc_read_reg(SDRC_SHARING) & 0xFFFF);
 270         sdrc_block_contents.err_type =
 271                         (sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF);
 272         sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL);
 273         sdrc_block_contents.dll_b_ctrl = 0x0;
 274         /*
 275          * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should
 276          * be programed to issue automatic self refresh on timeout
 277          * of AUTO_CNT = 1 prior to any transition to OFF mode.
 278          */
 279         if ((omap_type() != OMAP2_DEVICE_TYPE_GP)
 280                 && cpu_is_omap34xx() && omap_rev_ge_3_0())
 281                 sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) &
 282                                 ~(SDRC_POWER_AUTOCOUNT_MASK|
 283                                 SDRC_POWER_CLKCTRL_MASK)) |
 284                                 (1 << SDRC_POWER_AUTOCOUNT_SHIFT) |
 285                                 SDRC_SELF_REFRESH_ON_AUTOCOUNT;
 286         else
 287                 sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER);
 288
 289         sdrc_block_contents.cs_0 = 0x0;
 290         sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0);
 291         sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF);
 292         sdrc_block_contents.emr_1_0 = 0x0;
 293         sdrc_block_contents.emr_2_0 = 0x0;
 294         sdrc_block_contents.emr_3_0 = 0x0;
 295         sdrc_block_contents.actim_ctrla_0 =
 296                         sdrc_read_reg(SDRC_ACTIM_CTRL_A_0);
 297         sdrc_block_contents.actim_ctrlb_0 =
 298                         sdrc_read_reg(SDRC_ACTIM_CTRL_B_0);
 299         sdrc_block_contents.rfr_ctrl_0 =
 300                         sdrc_read_reg(SDRC_RFR_CTRL_0);
 301         sdrc_block_contents.cs_1 = 0x0;
 302         sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1);
 303         sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF;
 304         sdrc_block_contents.emr_1_1 = 0x0;
 305         sdrc_block_contents.emr_2_1 = 0x0;
 306         sdrc_block_contents.emr_3_1 = 0x0;
 307         sdrc_block_contents.actim_ctrla_1 =
 308                         sdrc_read_reg(SDRC_ACTIM_CTRL_A_1);
 309         sdrc_block_contents.actim_ctrlb_1 =
 310                         sdrc_read_reg(SDRC_ACTIM_CTRL_B_1);
 311         sdrc_block_contents.rfr_ctrl_1 =
 312                         sdrc_read_reg(SDRC_RFR_CTRL_1);
 313         sdrc_block_contents.dcdl_1_ctrl = 0x0;
 314         sdrc_block_contents.dcdl_2_ctrl = 0x0;
 315         sdrc_block_contents.flags = 0x0;
 316         sdrc_block_contents.block_size = 0x0;
 317
 318         arm_context_addr = virt_to_phys(omap3_arm_context);
 319
 320         /* Copy all the contents to the scratchpad location */
 321         scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
 322         memcpy_toio(scratchpad_address, &scratchpad_contents,
 323                  sizeof(scratchpad_contents));
 324         /* Scratchpad contents being 32 bits, a divide by 4 done here */
 325         memcpy_toio(scratchpad_address +
 326                 scratchpad_contents.prcm_block_offset,
 327                 &prcm_block_contents, sizeof(prcm_block_contents));
 328         memcpy_toio(scratchpad_address +
 329                 scratchpad_contents.sdrc_block_offset,
 330                 &sdrc_block_contents, sizeof(sdrc_block_contents));
 331         /*
 332          * Copies the address of the location in SDRAM where ARM
 333          * registers get saved during a MPU OFF transition.
 334          */
 335         memcpy_toio(scratchpad_address +
 336                 scratchpad_contents.sdrc_block_offset +
 337                 sizeof(sdrc_block_contents), &arm_context_addr, 4);
 338 }
 339
 340 void omap3_control_save_context(void)
 341 {
 342         control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG);
 343         control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
 344         control_context.mem_dftrw0 =
 345                         omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0);
 346         control_context.mem_dftrw1 =
 347                         omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1);
 348         control_context.msuspendmux_0 =
 349                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0);
 350         control_context.msuspendmux_1 =
 351                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1);
 352         control_context.msuspendmux_2 =
 353                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2);
 354         control_context.msuspendmux_3 =
 355                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3);
 356         control_context.msuspendmux_4 =
 357                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4);
 358         control_context.msuspendmux_5 =
 359                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5);
 360         control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL);
 361         control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1);
 362         control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE);
 363         control_context.iva2_bootaddr =
 364                         omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR);
 365         control_context.iva2_bootmod =
 366                         omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD);
 367         control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0));
 368         control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1));
 369         control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2));
 370         control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3));
 371         control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4));
 372         control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5));
 373         control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6));
 374         control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7));
 375         control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8));
 376         control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0);
 377         control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
 378         control_context.dss_dpll_spreading =
 379                         omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING);
 380         control_context.core_dpll_spreading =
 381                         omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING);
 382         control_context.per_dpll_spreading =
 383                         omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING);
 384         control_context.usbhost_dpll_spreading =
 385                 omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
 386         control_context.pbias_lite =
 387                         omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE);
 388         control_context.temp_sensor =
 389                         omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR);
 390         control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4);
 391         control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5);
 392         control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI);
 393         return;
 394 }
 395
 396 void omap3_control_restore_context(void)
 397 {
 398         omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG);
 399         omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0);
 400         omap_ctrl_writel(control_context.mem_dftrw0,
 401                                         OMAP343X_CONTROL_MEM_DFTRW0);
 402         omap_ctrl_writel(control_context.mem_dftrw1,
 403                                         OMAP343X_CONTROL_MEM_DFTRW1);
 404         omap_ctrl_writel(control_context.msuspendmux_0,
 405                                         OMAP2_CONTROL_MSUSPENDMUX_0);
 406         omap_ctrl_writel(control_context.msuspendmux_1,
 407                                         OMAP2_CONTROL_MSUSPENDMUX_1);
 408         omap_ctrl_writel(control_context.msuspendmux_2,
 409                                         OMAP2_CONTROL_MSUSPENDMUX_2);
 410         omap_ctrl_writel(control_context.msuspendmux_3,
 411                                         OMAP2_CONTROL_MSUSPENDMUX_3);
 412         omap_ctrl_writel(control_context.msuspendmux_4,
 413                                         OMAP2_CONTROL_MSUSPENDMUX_4);
 414         omap_ctrl_writel(control_context.msuspendmux_5,
 415                                         OMAP2_CONTROL_MSUSPENDMUX_5);
 416         omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL);
 417         omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1);
 418         omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE);
 419         omap_ctrl_writel(control_context.iva2_bootaddr,
 420                                         OMAP343X_CONTROL_IVA2_BOOTADDR);
 421         omap_ctrl_writel(control_context.iva2_bootmod,
 422                                         OMAP343X_CONTROL_IVA2_BOOTMOD);
 423         omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0));
 424         omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1));
 425         omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2));
 426         omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3));
 427         omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4));
 428         omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5));
 429         omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6));
 430         omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7));
 431         omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8));
 432         omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0);
 433         omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1);
 434         omap_ctrl_writel(control_context.dss_dpll_spreading,
 435                                         OMAP343X_CONTROL_DSS_DPLL_SPREADING);
 436         omap_ctrl_writel(control_context.core_dpll_spreading,
 437                                         OMAP343X_CONTROL_CORE_DPLL_SPREADING);
 438         omap_ctrl_writel(control_context.per_dpll_spreading,
 439                                         OMAP343X_CONTROL_PER_DPLL_SPREADING);
 440         omap_ctrl_writel(control_context.usbhost_dpll_spreading,
 441                                 OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
 442         omap_ctrl_writel(control_context.pbias_lite,
 443                                         OMAP343X_CONTROL_PBIAS_LITE);
 444         omap_ctrl_writel(control_context.temp_sensor,
 445                                         OMAP343X_CONTROL_TEMP_SENSOR);
 446         omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4);
 447         omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5);
 448         omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
 449         return;
 450 }
 451 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */