| blob | 4707ba8a253b1cae94c5a52b88305d45f05b763b |
1 /*
2 * linux/arch/arm/mach-omap2/sleep.S
3 *
4 * (C) Copyright 2007
5 * Texas Instruments
6 * Karthik Dasu <karthik-dp@ti.com>
7 *
8 * (C) Copyright 2004
9 * Texas Instruments, <www.ti.com>
10 * Richard Woodruff <r-woodruff2@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27 #include <linux/linkage.h>
28 #include <asm/assembler.h>
29 #include <mach/io.h>
30 #include <plat/control.h>
32 #include "cm.h"
33 #include "prm.h"
34 #include "sdrc.h"
36 #define SDRC_SCRATCHPAD_SEM_V 0xfa00291c
38 #define PM_PREPWSTST_CORE_V OMAP34XX_PRM_REGADDR(CORE_MOD, \
39 OMAP3430_PM_PREPWSTST)
40 #define PM_PREPWSTST_CORE_P 0x48306AE8
41 #define PM_PREPWSTST_MPU_V OMAP34XX_PRM_REGADDR(MPU_MOD, \
42 OMAP3430_PM_PREPWSTST)
43 #define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + PM_PWSTCTRL
44 #define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
45 #define SRAM_BASE_P 0x40200000
46 #define CONTROL_STAT 0x480022F0
47 #define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is
48 * available */
49 #define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE + OMAP343X_CONTROL_MEM_WKUP\
50 + SCRATCHPAD_MEM_OFFS)
51 #define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER)
52 #define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG)
53 #define SDRC_MR_0_P (OMAP343X_SDRC_BASE + SDRC_MR_0)
54 #define SDRC_EMR2_0_P (OMAP343X_SDRC_BASE + SDRC_EMR2_0)
55 #define SDRC_MANUAL_0_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_0)
56 #define SDRC_MR_1_P (OMAP343X_SDRC_BASE + SDRC_MR_1)
57 #define SDRC_EMR2_1_P (OMAP343X_SDRC_BASE + SDRC_EMR2_1)
58 #define SDRC_MANUAL_1_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_1)
59 #define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
60 #define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
62 .text
63 /* Function to aquire the semaphore in scratchpad */
64 ENTRY(lock_scratchpad_sem)
65 stmfd sp!, {lr} @ save registers on stack
66 wait_sem:
67 mov r0,#1
68 ldr r1, sdrc_scratchpad_sem
69 wait_loop:
70 ldr r2, [r1] @ load the lock value
71 cmp r2, r0 @ is the lock free ?
72 beq wait_loop @ not free...
73 swp r2, r0, [r1] @ semaphore free so lock it and proceed
74 cmp r2, r0 @ did we succeed ?
75 beq wait_sem @ no - try again
76 ldmfd sp!, {pc} @ restore regs and return
77 sdrc_scratchpad_sem:
78 .word SDRC_SCRATCHPAD_SEM_V
79 ENTRY(lock_scratchpad_sem_sz)
80 .word . - lock_scratchpad_sem
82 .text
83 /* Function to release the scratchpad semaphore */
84 ENTRY(unlock_scratchpad_sem)
85 stmfd sp!, {lr} @ save registers on stack
86 ldr r3, sdrc_scratchpad_sem
87 mov r2,#0
88 str r2,[r3]
89 ldmfd sp!, {pc} @ restore regs and return
90 ENTRY(unlock_scratchpad_sem_sz)
91 .word . - unlock_scratchpad_sem
93 .text
94 /* Function call to get the restore pointer for resume from OFF */
95 ENTRY(get_restore_pointer)
96 stmfd sp!, {lr} @ save registers on stack
97 adr r0, restore
98 ldmfd sp!, {pc} @ restore regs and return
99 ENTRY(get_restore_pointer_sz)
100 .word . - get_restore_pointer
102 .text
103 /* Function call to get the restore pointer for for ES3 to resume from OFF */
104 ENTRY(get_es3_restore_pointer)
105 stmfd sp!, {lr} @ save registers on stack
106 adr r0, restore_es3
107 ldmfd sp!, {pc} @ restore regs and return
108 ENTRY(get_es3_restore_pointer_sz)
109 .word . - get_es3_restore_pointer
111 ENTRY(es3_sdrc_fix)
112 ldr r4, sdrc_syscfg @ get config addr
113 ldr r5, [r4] @ get value
114 tst r5, #0x100 @ is part access blocked
115 it eq
116 biceq r5, r5, #0x100 @ clear bit if set
117 str r5, [r4] @ write back change
118 ldr r4, sdrc_mr_0 @ get config addr
119 ldr r5, [r4] @ get value
120 str r5, [r4] @ write back change
121 ldr r4, sdrc_emr2_0 @ get config addr
122 ldr r5, [r4] @ get value
123 str r5, [r4] @ write back change
124 ldr r4, sdrc_manual_0 @ get config addr
125 mov r5, #0x2 @ autorefresh command
126 str r5, [r4] @ kick off refreshes
127 ldr r4, sdrc_mr_1 @ get config addr
128 ldr r5, [r4] @ get value
129 str r5, [r4] @ write back change
130 ldr r4, sdrc_emr2_1 @ get config addr
131 ldr r5, [r4] @ get value
132 str r5, [r4] @ write back change
133 ldr r4, sdrc_manual_1 @ get config addr
134 mov r5, #0x2 @ autorefresh command
135 str r5, [r4] @ kick off refreshes
136 bx lr
137 sdrc_syscfg:
138 .word SDRC_SYSCONFIG_P
139 sdrc_mr_0:
140 .word SDRC_MR_0_P
141 sdrc_emr2_0:
142 .word SDRC_EMR2_0_P
143 sdrc_manual_0:
144 .word SDRC_MANUAL_0_P
145 sdrc_mr_1:
146 .word SDRC_MR_1_P
147 sdrc_emr2_1:
148 .word SDRC_EMR2_1_P
149 sdrc_manual_1:
150 .word SDRC_MANUAL_1_P
151 ENTRY(es3_sdrc_fix_sz)
152 .word . - es3_sdrc_fix
154 /* Function to call rom code to save secure ram context */
155 ENTRY(save_secure_ram_context)
156 stmfd sp!, {r1-r12, lr} @ save registers on stack
157 save_secure_ram_debug:
158 /* b save_secure_ram_debug */ @ enable to debug save code
159 adr r3, api_params @ r3 points to parameters
160 str r0, [r3,#0x4] @ r0 has sdram address
161 ldr r12, high_mask
162 and r3, r3, r12
163 ldr r12, sram_phy_addr_mask
164 orr r3, r3, r12
165 mov r0, #25 @ set service ID for PPA
166 mov r12, r0 @ copy secure service ID in r12
167 mov r1, #0 @ set task id for ROM code in r1
168 mov r2, #4 @ set some flags in r2, r6
169 mov r6, #0xff
170 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
171 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
172 .word 0xE1600071 @ call SMI monitor (smi #1)
173 nop
174 nop
175 nop
176 nop
177 ldmfd sp!, {r1-r12, pc}
178 sram_phy_addr_mask:
179 .word SRAM_BASE_P
180 high_mask:
181 .word 0xffff
182 api_params:
183 .word 0x4, 0x0, 0x0, 0x1, 0x1
184 ENTRY(save_secure_ram_context_sz)
185 .word . - save_secure_ram_context
187 /*
188 * Forces OMAP into idle state
189 *
190 * omap34xx_suspend() - This bit of code just executes the WFI
191 * for normal idles.
192 *
193 * Note: This code get's copied to internal SRAM at boot. When the OMAP
194 * wakes up it continues execution at the point it went to sleep.
195 */
196 ENTRY(omap34xx_cpu_suspend)
197 stmfd sp!, {r0-r12, lr} @ save registers on stack
198 loop:
199 /*b loop*/ @Enable to debug by stepping through code
200 /* r0 contains restore pointer in sdram */
201 /* r1 contains information about saving context */
202 ldr r4, sdrc_power @ read the SDRC_POWER register
203 ldr r5, [r4] @ read the contents of SDRC_POWER
204 orr r5, r5, #0x40 @ enable self refresh on idle req
205 str r5, [r4] @ write back to SDRC_POWER register
207 cmp r1, #0x0
208 /* If context save is required, do that and execute wfi */
209 bne save_context_wfi
210 /* Data memory barrier and Data sync barrier */
211 mov r1, #0
212 mcr p15, 0, r1, c7, c10, 4
213 mcr p15, 0, r1, c7, c10, 5
215 wfi @ wait for interrupt
217 nop
218 nop
219 nop
220 nop
221 nop
222 nop
223 nop
224 nop
225 nop
226 nop
227 bl wait_sdrc_ok
229 ldmfd sp!, {r0-r12, pc} @ restore regs and return
230 restore_es3:
231 /*b restore_es3*/ @ Enable to debug restore code
232 ldr r5, pm_prepwstst_core_p
233 ldr r4, [r5]
234 and r4, r4, #0x3
235 cmp r4, #0x0 @ Check if previous power state of CORE is OFF
236 bne restore
237 adr r0, es3_sdrc_fix
238 ldr r1, sram_base
239 ldr r2, es3_sdrc_fix_sz
240 mov r2, r2, ror #2
241 copy_to_sram:
242 ldmia r0!, {r3} @ val = *src
243 stmia r1!, {r3} @ *dst = val
244 subs r2, r2, #0x1 @ num_words--
245 bne copy_to_sram
246 ldr r1, sram_base
247 blx r1
248 restore:
249 /* b restore*/ @ Enable to debug restore code
250 /* Check what was the reason for mpu reset and store the reason in r9*/
251 /* 1 - Only L1 and logic lost */
252 /* 2 - Only L2 lost - In this case, we wont be here */
253 /* 3 - Both L1 and L2 lost */
254 ldr r1, pm_pwstctrl_mpu
255 ldr r2, [r1]
256 and r2, r2, #0x3
257 cmp r2, #0x0 @ Check if target power state was OFF or RET
258 moveq r9, #0x3 @ MPU OFF => L1 and L2 lost
259 movne r9, #0x1 @ Only L1 and L2 lost => avoid L2 invalidation
260 bne logic_l1_restore
261 ldr r0, control_stat
262 ldr r1, [r0]
263 and r1, #0x700
264 cmp r1, #0x300
265 beq l2_inv_gp
266 mov r0, #40 @ set service ID for PPA
267 mov r12, r0 @ copy secure Service ID in r12
268 mov r1, #0 @ set task id for ROM code in r1
269 mov r2, #4 @ set some flags in r2, r6
270 mov r6, #0xff
271 adr r3, l2_inv_api_params @ r3 points to dummy parameters
272 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
273 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
274 .word 0xE1600071 @ call SMI monitor (smi #1)
275 /* Write to Aux control register to set some bits */
276 mov r0, #42 @ set service ID for PPA
277 mov r12, r0 @ copy secure Service ID in r12
278 mov r1, #0 @ set task id for ROM code in r1
279 mov r2, #4 @ set some flags in r2, r6
280 mov r6, #0xff
281 adr r3, write_aux_control_params @ r3 points to parameters
282 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
283 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
284 .word 0xE1600071 @ call SMI monitor (smi #1)
286 b logic_l1_restore
287 l2_inv_api_params:
288 .word 0x1, 0x00
289 write_aux_control_params:
290 .word 0x1, 0x72
291 l2_inv_gp:
292 /* Execute smi to invalidate L2 cache */
293 mov r12, #0x1 @ set up to invalide L2
294 smi: .word 0xE1600070 @ Call SMI monitor (smieq)
295 /* Write to Aux control register to set some bits */
296 mov r0, #0x72
297 mov r12, #0x3
298 .word 0xE1600070 @ Call SMI monitor (smieq)
299 logic_l1_restore:
300 mov r1, #0
301 /* Invalidate all instruction caches to PoU
302 * and flush branch target cache */
303 mcr p15, 0, r1, c7, c5, 0
305 ldr r4, scratchpad_base
306 ldr r3, [r4,#0xBC]
307 ldmia r3!, {r4-r6}
308 mov sp, r4
309 msr spsr_cxsf, r5
310 mov lr, r6
312 ldmia r3!, {r4-r9}
313 /* Coprocessor access Control Register */
314 mcr p15, 0, r4, c1, c0, 2
316 /* TTBR0 */
317 MCR p15, 0, r5, c2, c0, 0
318 /* TTBR1 */
319 MCR p15, 0, r6, c2, c0, 1
320 /* Translation table base control register */
321 MCR p15, 0, r7, c2, c0, 2
322 /*domain access Control Register */
323 MCR p15, 0, r8, c3, c0, 0
324 /* data fault status Register */
325 MCR p15, 0, r9, c5, c0, 0
327 ldmia r3!,{r4-r8}
328 /* instruction fault status Register */
329 MCR p15, 0, r4, c5, c0, 1
330 /*Data Auxiliary Fault Status Register */
331 MCR p15, 0, r5, c5, c1, 0
332 /*Instruction Auxiliary Fault Status Register*/
333 MCR p15, 0, r6, c5, c1, 1
334 /*Data Fault Address Register */
335 MCR p15, 0, r7, c6, c0, 0
336 /*Instruction Fault Address Register*/
337 MCR p15, 0, r8, c6, c0, 2
338 ldmia r3!,{r4-r7}
340 /* user r/w thread and process ID */
341 MCR p15, 0, r4, c13, c0, 2
342 /* user ro thread and process ID */
343 MCR p15, 0, r5, c13, c0, 3
344 /*Privileged only thread and process ID */
345 MCR p15, 0, r6, c13, c0, 4
346 /* cache size selection */
347 MCR p15, 2, r7, c0, c0, 0
348 ldmia r3!,{r4-r8}
349 /* Data TLB lockdown registers */
350 MCR p15, 0, r4, c10, c0, 0
351 /* Instruction TLB lockdown registers */
352 MCR p15, 0, r5, c10, c0, 1
353 /* Secure or Nonsecure Vector Base Address */
354 MCR p15, 0, r6, c12, c0, 0
355 /* FCSE PID */
356 MCR p15, 0, r7, c13, c0, 0
357 /* Context PID */
358 MCR p15, 0, r8, c13, c0, 1
360 ldmia r3!,{r4-r5}
361 /* primary memory remap register */
362 MCR p15, 0, r4, c10, c2, 0
363 /*normal memory remap register */
364 MCR p15, 0, r5, c10, c2, 1
366 /* Restore cpsr */
367 ldmia r3!,{r4} /*load CPSR from SDRAM*/
368 msr cpsr, r4 /*store cpsr */
370 /* Enabling MMU here */
371 mrc p15, 0, r7, c2, c0, 2 /* Read TTBRControl */
372 /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1*/
373 and r7, #0x7
374 cmp r7, #0x0
375 beq usettbr0
376 ttbr_error:
377 /* More work needs to be done to support N[0:2] value other than 0
378 * So looping here so that the error can be detected
379 */
380 b ttbr_error
381 usettbr0:
382 mrc p15, 0, r2, c2, c0, 0
383 ldr r5, ttbrbit_mask
384 and r2, r5
385 mov r4, pc
386 ldr r5, table_index_mask
387 and r4, r5 /* r4 = 31 to 20 bits of pc */
388 /* Extract the value to be written to table entry */
389 ldr r1, table_entry
390 add r1, r1, r4 /* r1 has value to be written to table entry*/
391 /* Getting the address of table entry to modify */
392 lsr r4, #18
393 add r2, r4 /* r2 has the location which needs to be modified */
394 /* Storing previous entry of location being modified */
395 ldr r5, scratchpad_base
396 ldr r4, [r2]
397 str r4, [r5, #0xC0]
398 /* Modify the table entry */
399 str r1, [r2]
400 /* Storing address of entry being modified
401 * - will be restored after enabling MMU */
402 ldr r5, scratchpad_base
403 str r2, [r5, #0xC4]
405 mov r0, #0
406 mcr p15, 0, r0, c7, c5, 4 @ Flush prefetch buffer
407 mcr p15, 0, r0, c7, c5, 6 @ Invalidate branch predictor array
408 mcr p15, 0, r0, c8, c5, 0 @ Invalidate instruction TLB
409 mcr p15, 0, r0, c8, c6, 0 @ Invalidate data TLB
410 /* Restore control register but dont enable caches here*/
411 /* Caches will be enabled after restoring MMU table entry */
412 ldmia r3!, {r4}
413 /* Store previous value of control register in scratchpad */
414 str r4, [r5, #0xC8]
415 ldr r2, cache_pred_disable_mask
416 and r4, r2
417 mcr p15, 0, r4, c1, c0, 0
419 ldmfd sp!, {r0-r12, pc} @ restore regs and return
420 save_context_wfi:
421 /*b save_context_wfi*/ @ enable to debug save code
422 mov r8, r0 /* Store SDRAM address in r8 */
423 /* Check what that target sleep state is:stored in r1*/
424 /* 1 - Only L1 and logic lost */
425 /* 2 - Only L2 lost */
426 /* 3 - Both L1 and L2 lost */
427 cmp r1, #0x2 /* Only L2 lost */
428 beq clean_l2
429 cmp r1, #0x1 /* L2 retained */
430 /* r9 stores whether to clean L2 or not*/
431 moveq r9, #0x0 /* Dont Clean L2 */
432 movne r9, #0x1 /* Clean L2 */
433 l1_logic_lost:
434 /* Store sp and spsr to SDRAM */
435 mov r4, sp
436 mrs r5, spsr
437 mov r6, lr
438 stmia r8!, {r4-r6}
439 /* Save all ARM registers */
440 /* Coprocessor access control register */
441 mrc p15, 0, r6, c1, c0, 2
442 stmia r8!, {r6}
443 /* TTBR0, TTBR1 and Translation table base control */
444 mrc p15, 0, r4, c2, c0, 0
445 mrc p15, 0, r5, c2, c0, 1
446 mrc p15, 0, r6, c2, c0, 2
447 stmia r8!, {r4-r6}
448 /* Domain access control register, data fault status register,
449 and instruction fault status register */
450 mrc p15, 0, r4, c3, c0, 0
451 mrc p15, 0, r5, c5, c0, 0
452 mrc p15, 0, r6, c5, c0, 1
453 stmia r8!, {r4-r6}
454 /* Data aux fault status register, instruction aux fault status,
455 datat fault address register and instruction fault address register*/
456 mrc p15, 0, r4, c5, c1, 0
457 mrc p15, 0, r5, c5, c1, 1
458 mrc p15, 0, r6, c6, c0, 0
459 mrc p15, 0, r7, c6, c0, 2
460 stmia r8!, {r4-r7}
461 /* user r/w thread and process ID, user r/o thread and process ID,
462 priv only thread and process ID, cache size selection */
463 mrc p15, 0, r4, c13, c0, 2
464 mrc p15, 0, r5, c13, c0, 3
465 mrc p15, 0, r6, c13, c0, 4
466 mrc p15, 2, r7, c0, c0, 0
467 stmia r8!, {r4-r7}
468 /* Data TLB lockdown, instruction TLB lockdown registers */
469 mrc p15, 0, r5, c10, c0, 0
470 mrc p15, 0, r6, c10, c0, 1
471 stmia r8!, {r5-r6}
472 /* Secure or non secure vector base address, FCSE PID, Context PID*/
473 mrc p15, 0, r4, c12, c0, 0
474 mrc p15, 0, r5, c13, c0, 0
475 mrc p15, 0, r6, c13, c0, 1
476 stmia r8!, {r4-r6}
477 /* Primary remap, normal remap registers */
478 mrc p15, 0, r4, c10, c2, 0
479 mrc p15, 0, r5, c10, c2, 1
480 stmia r8!,{r4-r5}
482 /* Store current cpsr*/
483 mrs r2, cpsr
484 stmia r8!, {r2}
486 mrc p15, 0, r4, c1, c0, 0
487 /* save control register */
488 stmia r8!, {r4}
489 clean_caches:
490 /* Clean Data or unified cache to POU*/
491 /* How to invalidate only L1 cache???? - #FIX_ME# */
492 /* mcr p15, 0, r11, c7, c11, 1 */
493 cmp r9, #1 /* Check whether L2 inval is required or not*/
494 bne skip_l2_inval
495 clean_l2:
496 /* read clidr */
497 mrc p15, 1, r0, c0, c0, 1
498 /* extract loc from clidr */
499 ands r3, r0, #0x7000000
500 /* left align loc bit field */
501 mov r3, r3, lsr #23
502 /* if loc is 0, then no need to clean */
503 beq finished
504 /* start clean at cache level 0 */
505 mov r10, #0
506 loop1:
507 /* work out 3x current cache level */
508 add r2, r10, r10, lsr #1
509 /* extract cache type bits from clidr*/
510 mov r1, r0, lsr r2
511 /* mask of the bits for current cache only */
512 and r1, r1, #7
513 /* see what cache we have at this level */
514 cmp r1, #2
515 /* skip if no cache, or just i-cache */
516 blt skip
517 /* select current cache level in cssr */
518 mcr p15, 2, r10, c0, c0, 0
519 /* isb to sych the new cssr&csidr */
520 isb
521 /* read the new csidr */
522 mrc p15, 1, r1, c0, c0, 0
523 /* extract the length of the cache lines */
524 and r2, r1, #7
525 /* add 4 (line length offset) */
526 add r2, r2, #4
527 ldr r4, assoc_mask
528 /* find maximum number on the way size */
529 ands r4, r4, r1, lsr #3
530 /* find bit position of way size increment */
531 clz r5, r4
532 ldr r7, numset_mask
533 /* extract max number of the index size*/
534 ands r7, r7, r1, lsr #13
535 loop2:
536 mov r9, r4
537 /* create working copy of max way size*/
538 loop3:
539 /* factor way and cache number into r11 */
540 orr r11, r10, r9, lsl r5
541 /* factor index number into r11 */
542 orr r11, r11, r7, lsl r2
543 /*clean & invalidate by set/way */
544 mcr p15, 0, r11, c7, c10, 2
545 /* decrement the way*/
546 subs r9, r9, #1
547 bge loop3
548 /*decrement the index */
549 subs r7, r7, #1
550 bge loop2
551 skip:
552 add r10, r10, #2
553 /* increment cache number */
554 cmp r3, r10
555 bgt loop1
556 finished:
557 /*swith back to cache level 0 */
558 mov r10, #0
559 /* select current cache level in cssr */
560 mcr p15, 2, r10, c0, c0, 0
561 isb
562 skip_l2_inval:
563 /* Data memory barrier and Data sync barrier */
564 mov r1, #0
565 mcr p15, 0, r1, c7, c10, 4
566 mcr p15, 0, r1, c7, c10, 5
568 wfi @ wait for interrupt
569 nop
570 nop
571 nop
572 nop
573 nop
574 nop
575 nop
576 nop
577 nop
578 nop
579 bl wait_sdrc_ok
580 /* restore regs and return */
581 ldmfd sp!, {r0-r12, pc}
583 /* Make sure SDRC accesses are ok */
584 wait_sdrc_ok:
585 ldr r4, cm_idlest1_core
586 ldr r5, [r4]
587 and r5, r5, #0x2
588 cmp r5, #0
589 bne wait_sdrc_ok
590 ldr r4, sdrc_power
591 ldr r5, [r4]
592 bic r5, r5, #0x40
593 str r5, [r4]
594 wait_dll_lock:
595 /* Is dll in lock mode? */
596 ldr r4, sdrc_dlla_ctrl
597 ldr r5, [r4]
598 tst r5, #0x4
599 bxne lr
600 /* wait till dll locks */
601 ldr r4, sdrc_dlla_status
602 ldr r5, [r4]
603 and r5, r5, #0x4
604 cmp r5, #0x4
605 bne wait_dll_lock
606 bx lr
608 cm_idlest1_core:
609 .word CM_IDLEST1_CORE_V
610 sdrc_dlla_status:
611 .word SDRC_DLLA_STATUS_V
612 sdrc_dlla_ctrl:
613 .word SDRC_DLLA_CTRL_V
614 pm_prepwstst_core:
615 .word PM_PREPWSTST_CORE_V
616 pm_prepwstst_core_p:
617 .word PM_PREPWSTST_CORE_P
618 pm_prepwstst_mpu:
619 .word PM_PREPWSTST_MPU_V
620 pm_pwstctrl_mpu:
621 .word PM_PWSTCTRL_MPU_P
622 scratchpad_base:
623 .word SCRATCHPAD_BASE_P
624 sram_base:
625 .word SRAM_BASE_P + 0x8000
626 sdrc_power:
627 .word SDRC_POWER_V
628 clk_stabilize_delay:
629 .word 0x000001FF
630 assoc_mask:
631 .word 0x3ff
632 numset_mask:
633 .word 0x7fff
634 ttbrbit_mask:
635 .word 0xFFFFC000
636 table_index_mask:
637 .word 0xFFF00000
638 table_entry:
639 .word 0x00000C02
640 cache_pred_disable_mask:
641 .word 0xFFFFE7FB
642 control_stat:
643 .word CONTROL_STAT
644 ENTRY(omap34xx_cpu_suspend_sz)
645 .word . - omap34xx_cpu_suspend