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Full support for Ginger Console
[linux-ginger.git] / arch / arm / plat-omap / gpio.c
blob4c35f9f39c5bbffa943986628ce7afa4338be906
1 /*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
8 *
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/interrupt.h>
20 #include <linux/sysdev.h>
21 #include <linux/err.h>
22 #include <linux/clk.h>
23 #include <linux/io.h>
24
25 #include <mach/hardware.h>
26 #include <plat/control.h>
27 #include <asm/irq.h>
28 #include <mach/irqs.h>
29 #include <mach/gpio.h>
30 #include <asm/mach/irq.h>
31 #include <plat/powerdomain.h>
32 #include <plat/mux.h>
33
34 /*
35 * OMAP1510 GPIO registers
36 */
37 #define OMAP1510_GPIO_BASE 0xfffce000
38 #define OMAP1510_GPIO_DATA_INPUT 0x00
39 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
40 #define OMAP1510_GPIO_DIR_CONTROL 0x08
41 #define OMAP1510_GPIO_INT_CONTROL 0x0c
42 #define OMAP1510_GPIO_INT_MASK 0x10
43 #define OMAP1510_GPIO_INT_STATUS 0x14
44 #define OMAP1510_GPIO_PIN_CONTROL 0x18
45
46 #define OMAP1510_IH_GPIO_BASE 64
47
48 /*
49 * OMAP1610 specific GPIO registers
50 */
51 #define OMAP1610_GPIO1_BASE 0xfffbe400
52 #define OMAP1610_GPIO2_BASE 0xfffbec00
53 #define OMAP1610_GPIO3_BASE 0xfffbb400
54 #define OMAP1610_GPIO4_BASE 0xfffbbc00
55 #define OMAP1610_GPIO_REVISION 0x0000
56 #define OMAP1610_GPIO_SYSCONFIG 0x0010
57 #define OMAP1610_GPIO_SYSSTATUS 0x0014
58 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
59 #define OMAP1610_GPIO_IRQENABLE1 0x001c
60 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
61 #define OMAP1610_GPIO_DATAIN 0x002c
62 #define OMAP1610_GPIO_DATAOUT 0x0030
63 #define OMAP1610_GPIO_DIRECTION 0x0034
64 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
65 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
66 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
67 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
68 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
69 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
70 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
71 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
72
73 /*
74 * OMAP7XX specific GPIO registers
75 */
76 #define OMAP7XX_GPIO1_BASE 0xfffbc000
77 #define OMAP7XX_GPIO2_BASE 0xfffbc800
78 #define OMAP7XX_GPIO3_BASE 0xfffbd000
79 #define OMAP7XX_GPIO4_BASE 0xfffbd800
80 #define OMAP7XX_GPIO5_BASE 0xfffbe000
81 #define OMAP7XX_GPIO6_BASE 0xfffbe800
82 #define OMAP7XX_GPIO_DATA_INPUT 0x00
83 #define OMAP7XX_GPIO_DATA_OUTPUT 0x04
84 #define OMAP7XX_GPIO_DIR_CONTROL 0x08
85 #define OMAP7XX_GPIO_INT_CONTROL 0x0c
86 #define OMAP7XX_GPIO_INT_MASK 0x10
87 #define OMAP7XX_GPIO_INT_STATUS 0x14
88
89 #define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
90
91 /*
92 * omap24xx specific GPIO registers
93 */
94 #define OMAP242X_GPIO1_BASE 0x48018000
95 #define OMAP242X_GPIO2_BASE 0x4801a000
96 #define OMAP242X_GPIO3_BASE 0x4801c000
97 #define OMAP242X_GPIO4_BASE 0x4801e000
98
99 #define OMAP243X_GPIO1_BASE 0x4900C000
100 #define OMAP243X_GPIO2_BASE 0x4900E000
101 #define OMAP243X_GPIO3_BASE 0x49010000
102 #define OMAP243X_GPIO4_BASE 0x49012000
103 #define OMAP243X_GPIO5_BASE 0x480B6000
104
105 #define OMAP24XX_GPIO_REVISION 0x0000
106 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
107 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
108 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
109 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
110 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
111 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
112 #define OMAP24XX_GPIO_WAKE_EN 0x0020
113 #define OMAP24XX_GPIO_CTRL 0x0030
114 #define OMAP24XX_GPIO_OE 0x0034
115 #define OMAP24XX_GPIO_DATAIN 0x0038
116 #define OMAP24XX_GPIO_DATAOUT 0x003c
117 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
118 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
119 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
120 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
121 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
122 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
123 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
124 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
125 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
126 #define OMAP24XX_GPIO_SETWKUENA 0x0084
127 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
128 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
129
130 #define OMAP4_GPIO_REVISION 0x0000
131 #define OMAP4_GPIO_SYSCONFIG 0x0010
132 #define OMAP4_GPIO_EOI 0x0020
133 #define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
134 #define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
135 #define OMAP4_GPIO_IRQSTATUS0 0x002c
136 #define OMAP4_GPIO_IRQSTATUS1 0x0030
137 #define OMAP4_GPIO_IRQSTATUSSET0 0x0034
138 #define OMAP4_GPIO_IRQSTATUSSET1 0x0038
139 #define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
140 #define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
141 #define OMAP4_GPIO_IRQWAKEN0 0x0044
142 #define OMAP4_GPIO_IRQWAKEN1 0x0048
143 #define OMAP4_GPIO_SYSSTATUS 0x0104
144 #define OMAP4_GPIO_CTRL 0x0130
145 #define OMAP4_GPIO_OE 0x0134
146 #define OMAP4_GPIO_DATAIN 0x0138
147 #define OMAP4_GPIO_DATAOUT 0x013c
148 #define OMAP4_GPIO_LEVELDETECT0 0x0140
149 #define OMAP4_GPIO_LEVELDETECT1 0x0144
150 #define OMAP4_GPIO_RISINGDETECT 0x0148
151 #define OMAP4_GPIO_FALLINGDETECT 0x014c
152 #define OMAP4_GPIO_DEBOUNCENABLE 0x0150
153 #define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
154 #define OMAP4_GPIO_CLEARDATAOUT 0x0190
155 #define OMAP4_GPIO_SETDATAOUT 0x0194
156 /*
157 * omap34xx specific GPIO registers
158 */
159
160 #define OMAP34XX_GPIO1_BASE 0x48310000
161 #define OMAP34XX_GPIO2_BASE 0x49050000
162 #define OMAP34XX_GPIO3_BASE 0x49052000
163 #define OMAP34XX_GPIO4_BASE 0x49054000
164 #define OMAP34XX_GPIO5_BASE 0x49056000
165 #define OMAP34XX_GPIO6_BASE 0x49058000
166
167 /*
168 * OMAP44XX specific GPIO registers
169 */
170 #define OMAP44XX_GPIO1_BASE 0x4a310000
171 #define OMAP44XX_GPIO2_BASE 0x48055000
172 #define OMAP44XX_GPIO3_BASE 0x48057000
173 #define OMAP44XX_GPIO4_BASE 0x48059000
174 #define OMAP44XX_GPIO5_BASE 0x4805B000
175 #define OMAP44XX_GPIO6_BASE 0x4805D000
176
177 struct gpio_bank {
178 unsigned long pbase;
179 void __iomem *base;
180 u16 irq;
181 u16 virtual_irq_start;
182 int method;
183 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
184 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
185 u32 suspend_wakeup;
186 u32 saved_wakeup;
187 #endif
188 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
189 defined(CONFIG_ARCH_OMAP4)
190 u32 non_wakeup_gpios;
191 u32 enabled_non_wakeup_gpios;
192
193 u32 saved_datain;
194 u32 saved_fallingdetect;
195 u32 saved_risingdetect;
196 #endif
197 u32 level_mask;
198 spinlock_t lock;
199 struct gpio_chip chip;
200 struct clk *dbck;
201 u32 dbck_enable_mask;
202 };
203
204 #define METHOD_MPUIO 0
205 #define METHOD_GPIO_1510 1
206 #define METHOD_GPIO_1610 2
207 #define METHOD_GPIO_7XX 3
208 #define METHOD_GPIO_24XX 5
209
210 #ifdef CONFIG_ARCH_OMAP16XX
211 static struct gpio_bank gpio_bank_1610[5] = {
212 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
213 METHOD_MPUIO },
214 { OMAP1610_GPIO1_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
215 METHOD_GPIO_1610 },
216 { OMAP1610_GPIO2_BASE, NULL, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16,
217 METHOD_GPIO_1610 },
218 { OMAP1610_GPIO3_BASE, NULL, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32,
219 METHOD_GPIO_1610 },
220 { OMAP1610_GPIO4_BASE, NULL, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48,
221 METHOD_GPIO_1610 },
222 };
223 #endif
224
225 #ifdef CONFIG_ARCH_OMAP15XX
226 static struct gpio_bank gpio_bank_1510[2] = {
227 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
228 METHOD_MPUIO },
229 { OMAP1510_GPIO_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
230 METHOD_GPIO_1510 }
231 };
232 #endif
233
234 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
235 static struct gpio_bank gpio_bank_7xx[7] = {
236 { OMAP1_MPUIO_VBASE, NULL, INT_7XX_MPUIO, IH_MPUIO_BASE,
237 METHOD_MPUIO },
238 { OMAP7XX_GPIO1_BASE, NULL, INT_7XX_GPIO_BANK1, IH_GPIO_BASE,
239 METHOD_GPIO_7XX },
240 { OMAP7XX_GPIO2_BASE, NULL, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32,
241 METHOD_GPIO_7XX },
242 { OMAP7XX_GPIO3_BASE, NULL, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64,
243 METHOD_GPIO_7XX },
244 { OMAP7XX_GPIO4_BASE, NULL, INT_7XX_GPIO_BANK4, IH_GPIO_BASE + 96,
245 METHOD_GPIO_7XX },
246 { OMAP7XX_GPIO5_BASE, NULL, INT_7XX_GPIO_BANK5, IH_GPIO_BASE + 128,
247 METHOD_GPIO_7XX },
248 { OMAP7XX_GPIO6_BASE, NULL, INT_7XX_GPIO_BANK6, IH_GPIO_BASE + 160,
249 METHOD_GPIO_7XX },
250 };
251 #endif
252
253 #ifdef CONFIG_ARCH_OMAP24XX
254
255 static struct gpio_bank gpio_bank_242x[4] = {
256 { OMAP242X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
257 METHOD_GPIO_24XX },
258 { OMAP242X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
259 METHOD_GPIO_24XX },
260 { OMAP242X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
261 METHOD_GPIO_24XX },
262 { OMAP242X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
263 METHOD_GPIO_24XX },
264 };
265
266 static struct gpio_bank gpio_bank_243x[5] = {
267 { OMAP243X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
268 METHOD_GPIO_24XX },
269 { OMAP243X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
270 METHOD_GPIO_24XX },
271 { OMAP243X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
272 METHOD_GPIO_24XX },
273 { OMAP243X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
274 METHOD_GPIO_24XX },
275 { OMAP243X_GPIO5_BASE, NULL, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128,
276 METHOD_GPIO_24XX },
277 };
278
279 #endif
280
281 #ifdef CONFIG_ARCH_OMAP34XX
282 static struct gpio_bank gpio_bank_34xx[6] = {
283 { OMAP34XX_GPIO1_BASE, NULL, INT_34XX_GPIO_BANK1, IH_GPIO_BASE,
284 METHOD_GPIO_24XX },
285 { OMAP34XX_GPIO2_BASE, NULL, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32,
286 METHOD_GPIO_24XX },
287 { OMAP34XX_GPIO3_BASE, NULL, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64,
288 METHOD_GPIO_24XX },
289 { OMAP34XX_GPIO4_BASE, NULL, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96,
290 METHOD_GPIO_24XX },
291 { OMAP34XX_GPIO5_BASE, NULL, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128,
292 METHOD_GPIO_24XX },
293 { OMAP34XX_GPIO6_BASE, NULL, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160,
294 METHOD_GPIO_24XX },
295 };
296
297 #define OMAP34XX_PAD_SAFE_MODE 0x7
298 #define OMAP34XX_PAD_IN_PU_GPIO 0x11c
299 #define OMAP34XX_PAD_IN_PD_GPIO 0x10c
300
301 struct omap3_gpio_regs {
302 u32 sysconfig;
303 u32 irqenable1;
304 u32 irqenable2;
305 u32 wake_en;
306 u32 ctrl;
307 u32 oe;
308 u32 leveldetect0;
309 u32 leveldetect1;
310 u32 risingdetect;
311 u32 fallingdetect;
312 u32 dataout;
313 };
314
315 static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
316
317 /* GPIO -> PAD init configuration struct */
318 struct gpio_pad_range {
319 /* Range start GPIO # */
320 u16 min;
321 /* Range end GPIO # */
322 u16 max;
323 /* Start pad config offset */
324 u16 offset;
325 };
326
327 /*
328 * Defines GPIO to padconfig mapping. For example first definition tells
329 * us that there is a range of GPIOs 34...43 which have their padconfigs
330 * starting from offset 0x7a, i.e. gpio 34->0x7a, 35->0x7c, 36->0x7e ... etc.
331 */
332 static const struct gpio_pad_range gpio_pads_config[] = {
333 { 34, 43, 0x7a },
334 { 44, 51, 0x9e },
335 { 52, 59, 0xb0 },
336 { 60, 62, 0xc6 },
337 { 63, 111, 0xce },
338 { 167, 167, 0x130 },
339 { 126, 126, 0x132 },
340 { 112, 166, 0x134 },
341 { 120, 122, 0x1a2 },
342 { 124, 125, 0x1a8 },
343 { 130, 131, 0x1ac },
344 { 169, 169, 0x1b0 },
345 { 188, 191, 0x1b2 },
346 { 168, 168, 0x1be },
347 { 183, 185, 0x1c0 },
348 { 170, 182, 0x1c6 },
349 { 0, 0, 0x1e0 },
350 { 186, 186, 0x1e2 },
351 { 187, 187, 0x238 },
352 { 32, 32, 0x23a },
353 { 12, 29, 0x5d8 },
354 { 1, 1, 0xa06 },
355 { 30, 30, 0xa08 },
356 { 2, 10, 0xa0a },
357 { 11, 11, 0xa24 },
358 { 31, 31, 0xa26 },
359 };
360
361 /* GPIO -> PAD config mapping for OMAP3 */
362 struct gpio_pad {
363 s16 gpio;
364 u16 offset;
365 u16 save;
366 };
367
368 #define OMAP34XX_GPIO_AMT (32 * OMAP34XX_NR_GPIOS)
369
370 static struct gpio_pad *gpio_pads;
371 static u16 gpio_pad_map[OMAP34XX_GPIO_AMT];
372 #endif
373
374 #ifdef CONFIG_ARCH_OMAP4
375 static struct gpio_bank gpio_bank_44xx[6] = {
376 { OMAP44XX_GPIO1_BASE, NULL, INT_44XX_GPIO_BANK1, IH_GPIO_BASE,
377 METHOD_GPIO_24XX },
378 { OMAP44XX_GPIO2_BASE, NULL, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32,
379 METHOD_GPIO_24XX },
380 { OMAP44XX_GPIO3_BASE, NULL, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64,
381 METHOD_GPIO_24XX },
382 { OMAP44XX_GPIO4_BASE, NULL, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96,
383 METHOD_GPIO_24XX },
384 { OMAP44XX_GPIO5_BASE, NULL, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128,
385 METHOD_GPIO_24XX },
386 { OMAP44XX_GPIO6_BASE, NULL, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160,
387 METHOD_GPIO_24XX },
388 };
389
390 #endif
391
392 static struct gpio_bank *gpio_bank;
393 static int gpio_bank_count;
394
395 static inline struct gpio_bank *get_gpio_bank(int gpio)
396 {
397 if (cpu_is_omap15xx()) {
398 if (OMAP_GPIO_IS_MPUIO(gpio))
399 return &gpio_bank[0];
400 return &gpio_bank[1];
401 }
402 if (cpu_is_omap16xx()) {
403 if (OMAP_GPIO_IS_MPUIO(gpio))
404 return &gpio_bank[0];
405 return &gpio_bank[1 + (gpio >> 4)];
406 }
407 if (cpu_is_omap7xx()) {
408 if (OMAP_GPIO_IS_MPUIO(gpio))
409 return &gpio_bank[0];
410 return &gpio_bank[1 + (gpio >> 5)];
411 }
412 if (cpu_is_omap24xx())
413 return &gpio_bank[gpio >> 5];
414 if (cpu_is_omap34xx() || cpu_is_omap44xx())
415 return &gpio_bank[gpio >> 5];
416 BUG();
417 return NULL;
418 }
419
420 static inline int get_gpio_index(int gpio)
421 {
422 if (cpu_is_omap7xx())
423 return gpio & 0x1f;
424 if (cpu_is_omap24xx())
425 return gpio & 0x1f;
426 if (cpu_is_omap34xx() || cpu_is_omap44xx())
427 return gpio & 0x1f;
428 return gpio & 0x0f;
429 }
430
431 static inline int gpio_valid(int gpio)
432 {
433 if (gpio < 0)
434 return -1;
435 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
436 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
437 return -1;
438 return 0;
439 }
440 if (cpu_is_omap15xx() && gpio < 16)
441 return 0;
442 if ((cpu_is_omap16xx()) && gpio < 64)
443 return 0;
444 if (cpu_is_omap7xx() && gpio < 192)
445 return 0;
446 if (cpu_is_omap24xx() && gpio < 128)
447 return 0;
448 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
449 return 0;
450 return -1;
451 }
452
453 static int check_gpio(int gpio)
454 {
455 if (unlikely(gpio_valid(gpio) < 0)) {
456 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
457 dump_stack();
458 return -1;
459 }
460 return 0;
461 }
462
463 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
464 {
465 void __iomem *reg = bank->base;
466 u32 l;
467
468 switch (bank->method) {
469 #ifdef CONFIG_ARCH_OMAP1
470 case METHOD_MPUIO:
471 reg += OMAP_MPUIO_IO_CNTL;
472 break;
473 #endif
474 #ifdef CONFIG_ARCH_OMAP15XX
475 case METHOD_GPIO_1510:
476 reg += OMAP1510_GPIO_DIR_CONTROL;
477 break;
478 #endif
479 #ifdef CONFIG_ARCH_OMAP16XX
480 case METHOD_GPIO_1610:
481 reg += OMAP1610_GPIO_DIRECTION;
482 break;
483 #endif
484 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
485 case METHOD_GPIO_7XX:
486 reg += OMAP7XX_GPIO_DIR_CONTROL;
487 break;
488 #endif
489 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
490 case METHOD_GPIO_24XX:
491 reg += OMAP24XX_GPIO_OE;
492 break;
493 #endif
494 #if defined(CONFIG_ARCH_OMAP4)
495 case METHOD_GPIO_24XX:
496 reg += OMAP4_GPIO_OE;
497 break;
498 #endif
499 default:
500 WARN_ON(1);
501 return;
502 }
503 l = __raw_readl(reg);
504 if (is_input)
505 l |= 1 << gpio;
506 else
507 l &= ~(1 << gpio);
508 __raw_writel(l, reg);
509 }
510
511 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
512 {
513 void __iomem *reg = bank->base;
514 u32 l = 0;
515
516 switch (bank->method) {
517 #ifdef CONFIG_ARCH_OMAP1
518 case METHOD_MPUIO:
519 reg += OMAP_MPUIO_OUTPUT;
520 l = __raw_readl(reg);
521 if (enable)
522 l |= 1 << gpio;
523 else
524 l &= ~(1 << gpio);
525 break;
526 #endif
527 #ifdef CONFIG_ARCH_OMAP15XX
528 case METHOD_GPIO_1510:
529 reg += OMAP1510_GPIO_DATA_OUTPUT;
530 l = __raw_readl(reg);
531 if (enable)
532 l |= 1 << gpio;
533 else
534 l &= ~(1 << gpio);
535 break;
536 #endif
537 #ifdef CONFIG_ARCH_OMAP16XX
538 case METHOD_GPIO_1610:
539 if (enable)
540 reg += OMAP1610_GPIO_SET_DATAOUT;
541 else
542 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
543 l = 1 << gpio;
544 break;
545 #endif
546 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
547 case METHOD_GPIO_7XX:
548 reg += OMAP7XX_GPIO_DATA_OUTPUT;
549 l = __raw_readl(reg);
550 if (enable)
551 l |= 1 << gpio;
552 else
553 l &= ~(1 << gpio);
554 break;
555 #endif
556 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
557 case METHOD_GPIO_24XX:
558 if (enable)
559 reg += OMAP24XX_GPIO_SETDATAOUT;
560 else
561 reg += OMAP24XX_GPIO_CLEARDATAOUT;
562 l = 1 << gpio;
563 break;
564 #endif
565 #ifdef CONFIG_ARCH_OMAP4
566 case METHOD_GPIO_24XX:
567 if (enable)
568 reg += OMAP4_GPIO_SETDATAOUT;
569 else
570 reg += OMAP4_GPIO_CLEARDATAOUT;
571 l = 1 << gpio;
572 break;
573 #endif
574 default:
575 WARN_ON(1);
576 return;
577 }
578 __raw_writel(l, reg);
579 }
580
581 static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
582 {
583 void __iomem *reg;
584
585 if (check_gpio(gpio) < 0)
586 return -EINVAL;
587 reg = bank->base;
588 switch (bank->method) {
589 #ifdef CONFIG_ARCH_OMAP1
590 case METHOD_MPUIO:
591 reg += OMAP_MPUIO_INPUT_LATCH;
592 break;
593 #endif
594 #ifdef CONFIG_ARCH_OMAP15XX
595 case METHOD_GPIO_1510:
596 reg += OMAP1510_GPIO_DATA_INPUT;
597 break;
598 #endif
599 #ifdef CONFIG_ARCH_OMAP16XX
600 case METHOD_GPIO_1610:
601 reg += OMAP1610_GPIO_DATAIN;
602 break;
603 #endif
604 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
605 case METHOD_GPIO_7XX:
606 reg += OMAP7XX_GPIO_DATA_INPUT;
607 break;
608 #endif
609 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
610 case METHOD_GPIO_24XX:
611 reg += OMAP24XX_GPIO_DATAIN;
612 break;
613 #endif
614 #ifdef CONFIG_ARCH_OMAP4
615 case METHOD_GPIO_24XX:
616 reg += OMAP4_GPIO_DATAIN;
617 break;
618 #endif
619 default:
620 return -EINVAL;
621 }
622 return (__raw_readl(reg)
623 & (1 << get_gpio_index(gpio))) != 0;
624 }
625
626 static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
627 {
628 void __iomem *reg;
629
630 if (check_gpio(gpio) < 0)
631 return -EINVAL;
632 reg = bank->base;
633
634 switch (bank->method) {
635 #ifdef CONFIG_ARCH_OMAP1
636 case METHOD_MPUIO:
637 reg += OMAP_MPUIO_OUTPUT;
638 break;
639 #endif
640 #ifdef CONFIG_ARCH_OMAP15XX
641 case METHOD_GPIO_1510:
642 reg += OMAP1510_GPIO_DATA_OUTPUT;
643 break;
644 #endif
645 #ifdef CONFIG_ARCH_OMAP16XX
646 case METHOD_GPIO_1610:
647 reg += OMAP1610_GPIO_DATAOUT;
648 break;
649 #endif
650 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
651 case METHOD_GPIO_7XX:
652 reg += OMAP7XX_GPIO_DATA_OUTPUT;
653 break;
654 #endif
655 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
656 defined(CONFIG_ARCH_OMAP4)
657 case METHOD_GPIO_24XX:
658 reg += OMAP24XX_GPIO_DATAOUT;
659 break;
660 #endif
661 default:
662 return -EINVAL;
663 }
664
665 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
666 }
667
668 #define MOD_REG_BIT(reg, bit_mask, set) \
669 do { \
670 int l = __raw_readl(base + reg); \
671 if (set) l |= bit_mask; \
672 else l &= ~bit_mask; \
673 __raw_writel(l, base + reg); \
674 } while(0)
675
676 void omap_set_gpio_debounce(int gpio, int enable)
677 {
678 struct gpio_bank *bank;
679 void __iomem *reg;
680 unsigned long flags;
681 u32 val, l = 1 << get_gpio_index(gpio);
682
683 if (cpu_class_is_omap1())
684 return;
685
686 bank = get_gpio_bank(gpio);
687 reg = bank->base;
688 #ifdef CONFIG_ARCH_OMAP4
689 reg += OMAP4_GPIO_DEBOUNCENABLE;
690 #else
691 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
692 #endif
693
694 spin_lock_irqsave(&bank->lock, flags);
695 val = __raw_readl(reg);
696
697 if (enable && !(val & l))
698 val |= l;
699 else if (!enable && (val & l))
700 val &= ~l;
701 else
702 goto done;
703
704 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
705 bank->dbck_enable_mask = val;
706 if (enable)
707 clk_enable(bank->dbck);
708 else
709 clk_disable(bank->dbck);
710 }
711
712 __raw_writel(val, reg);
713 done:
714 spin_unlock_irqrestore(&bank->lock, flags);
715 }
716 EXPORT_SYMBOL(omap_set_gpio_debounce);
717
718 void omap_set_gpio_debounce_time(int gpio, int enc_time)
719 {
720 struct gpio_bank *bank;
721 void __iomem *reg;
722
723 if (cpu_class_is_omap1())
724 return;
725
726 bank = get_gpio_bank(gpio);
727 reg = bank->base;
728
729 enc_time &= 0xff;
730 #ifdef CONFIG_ARCH_OMAP4
731 reg += OMAP4_GPIO_DEBOUNCINGTIME;
732 #else
733 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
734 #endif
735 __raw_writel(enc_time, reg);
736 }
737 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
738
739 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
740 defined(CONFIG_ARCH_OMAP4)
741 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
742 int trigger)
743 {
744 void __iomem *base = bank->base;
745 u32 gpio_bit = 1 << gpio;
746 u32 val;
747
748 if (cpu_is_omap44xx()) {
749 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
750 trigger & IRQ_TYPE_LEVEL_LOW);
751 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
752 trigger & IRQ_TYPE_LEVEL_HIGH);
753 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
754 trigger & IRQ_TYPE_EDGE_RISING);
755 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
756 trigger & IRQ_TYPE_EDGE_FALLING);
757 } else {
758 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
759 trigger & IRQ_TYPE_LEVEL_LOW);
760 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
761 trigger & IRQ_TYPE_LEVEL_HIGH);
762 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
763 trigger & IRQ_TYPE_EDGE_RISING);
764 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
765 trigger & IRQ_TYPE_EDGE_FALLING);
766 }
767 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
768 if (cpu_is_omap44xx()) {
769 if (trigger != 0)
770 __raw_writel(1 << gpio, bank->base+
771 OMAP4_GPIO_IRQWAKEN0);
772 else {
773 val = __raw_readl(bank->base +
774 OMAP4_GPIO_IRQWAKEN0);
775 __raw_writel(val & (~(1 << gpio)), bank->base +
776 OMAP4_GPIO_IRQWAKEN0);
777 }
778 } else {
779 /*
780 * GPIO wakeup request can only be generated on edge
781 * transitions
782 */
783 if (trigger & IRQ_TYPE_EDGE_BOTH)
784 __raw_writel(1 << gpio, bank->base
785 + OMAP24XX_GPIO_SETWKUENA);
786 else
787 __raw_writel(1 << gpio, bank->base
788 + OMAP24XX_GPIO_CLEARWKUENA);
789 }
790 }
791 /* This part needs to be executed always for OMAP34xx */
792 if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) {
793 /*
794 * Log the edge gpio and manually trigger the IRQ
795 * after resume if the input level changes
796 * to avoid irq lost during PER RET/OFF mode
797 * Applies for omap2 non-wakeup gpio and all omap3 gpios
798 */
799 if (trigger & IRQ_TYPE_EDGE_BOTH)
800 bank->enabled_non_wakeup_gpios |= gpio_bit;
801 else
802 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
803 }
804
805 if (cpu_is_omap44xx()) {
806 bank->level_mask =
807 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
808 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
809 } else {
810 bank->level_mask =
811 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
812 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
813 }
814 }
815 #endif
816
817 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
818 {
819 void __iomem *reg = bank->base;
820 u32 l = 0;
821
822 switch (bank->method) {
823 #ifdef CONFIG_ARCH_OMAP1
824 case METHOD_MPUIO:
825 reg += OMAP_MPUIO_GPIO_INT_EDGE;
826 l = __raw_readl(reg);
827 if (trigger & IRQ_TYPE_EDGE_RISING)
828 l |= 1 << gpio;
829 else if (trigger & IRQ_TYPE_EDGE_FALLING)
830 l &= ~(1 << gpio);
831 else
832 goto bad;
833 break;
834 #endif
835 #ifdef CONFIG_ARCH_OMAP15XX
836 case METHOD_GPIO_1510:
837 reg += OMAP1510_GPIO_INT_CONTROL;
838 l = __raw_readl(reg);
839 if (trigger & IRQ_TYPE_EDGE_RISING)
840 l |= 1 << gpio;
841 else if (trigger & IRQ_TYPE_EDGE_FALLING)
842 l &= ~(1 << gpio);
843 else
844 goto bad;
845 break;
846 #endif
847 #ifdef CONFIG_ARCH_OMAP16XX
848 case METHOD_GPIO_1610:
849 if (gpio & 0x08)
850 reg += OMAP1610_GPIO_EDGE_CTRL2;
851 else
852 reg += OMAP1610_GPIO_EDGE_CTRL1;
853 gpio &= 0x07;
854 l = __raw_readl(reg);
855 l &= ~(3 << (gpio << 1));
856 if (trigger & IRQ_TYPE_EDGE_RISING)
857 l |= 2 << (gpio << 1);
858 if (trigger & IRQ_TYPE_EDGE_FALLING)
859 l |= 1 << (gpio << 1);
860 if (trigger)
861 /* Enable wake-up during idle for dynamic tick */
862 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
863 else
864 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
865 break;
866 #endif
867 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
868 case METHOD_GPIO_7XX:
869 reg += OMAP7XX_GPIO_INT_CONTROL;
870 l = __raw_readl(reg);
871 if (trigger & IRQ_TYPE_EDGE_RISING)
872 l |= 1 << gpio;
873 else if (trigger & IRQ_TYPE_EDGE_FALLING)
874 l &= ~(1 << gpio);
875 else
876 goto bad;
877 break;
878 #endif
879 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
880 defined(CONFIG_ARCH_OMAP4)
881 case METHOD_GPIO_24XX:
882 set_24xx_gpio_triggering(bank, gpio, trigger);
883 break;
884 #endif
885 default:
886 goto bad;
887 }
888 __raw_writel(l, reg);
889 return 0;
890 bad:
891 return -EINVAL;
892 }
893
894 static int gpio_irq_type(unsigned irq, unsigned type)
895 {
896 struct gpio_bank *bank;
897 unsigned gpio;
898 int retval;
899 unsigned long flags;
900
901 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
902 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
903 else
904 gpio = irq - IH_GPIO_BASE;
905
906 if (check_gpio(gpio) < 0)
907 return -EINVAL;
908
909 if (type & ~IRQ_TYPE_SENSE_MASK)
910 return -EINVAL;
911
912 /* OMAP1 allows only only edge triggering */
913 if (!cpu_class_is_omap2()
914 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
915 return -EINVAL;
916
917 bank = get_irq_chip_data(irq);
918 spin_lock_irqsave(&bank->lock, flags);
919 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
920 if (retval == 0) {
921 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
922 irq_desc[irq].status |= type;
923 }
924 spin_unlock_irqrestore(&bank->lock, flags);
925
926 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
927 __set_irq_handler_unlocked(irq, handle_level_irq);
928 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
929 __set_irq_handler_unlocked(irq, handle_edge_irq);
930
931 return retval;
932 }
933
934 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
935 {
936 void __iomem *reg = bank->base;
937
938 switch (bank->method) {
939 #ifdef CONFIG_ARCH_OMAP1
940 case METHOD_MPUIO:
941 /* MPUIO irqstatus is reset by reading the status register,
942 * so do nothing here */
943 return;
944 #endif
945 #ifdef CONFIG_ARCH_OMAP15XX
946 case METHOD_GPIO_1510:
947 reg += OMAP1510_GPIO_INT_STATUS;
948 break;
949 #endif
950 #ifdef CONFIG_ARCH_OMAP16XX
951 case METHOD_GPIO_1610:
952 reg += OMAP1610_GPIO_IRQSTATUS1;
953 break;
954 #endif
955 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
956 case METHOD_GPIO_7XX:
957 reg += OMAP7XX_GPIO_INT_STATUS;
958 break;
959 #endif
960 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
961 case METHOD_GPIO_24XX:
962 reg += OMAP24XX_GPIO_IRQSTATUS1;
963 break;
964 #endif
965 #if defined(CONFIG_ARCH_OMAP4)
966 case METHOD_GPIO_24XX:
967 reg += OMAP4_GPIO_IRQSTATUS0;
968 break;
969 #endif
970 default:
971 WARN_ON(1);
972 return;
973 }
974 __raw_writel(gpio_mask, reg);
975
976 /* Workaround for clearing DSP GPIO interrupts to allow retention */
977 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
978 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
979 #endif
980 #if defined(CONFIG_ARCH_OMAP4)
981 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
982 #endif
983 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
984 __raw_writel(gpio_mask, reg);
985
986 /* Flush posted write for the irq status to avoid spurious interrupts */
987 __raw_readl(reg);
988 }
989 }
990
991 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
992 {
993 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
994 }
995
996 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
997 {
998 void __iomem *reg = bank->base;
999 int inv = 0;
1000 u32 l;
1001 u32 mask;
1002
1003 switch (bank->method) {
1004 #ifdef CONFIG_ARCH_OMAP1
1005 case METHOD_MPUIO:
1006 reg += OMAP_MPUIO_GPIO_MASKIT;
1007 mask = 0xffff;
1008 inv = 1;
1009 break;
1010 #endif
1011 #ifdef CONFIG_ARCH_OMAP15XX
1012 case METHOD_GPIO_1510:
1013 reg += OMAP1510_GPIO_INT_MASK;
1014 mask = 0xffff;
1015 inv = 1;
1016 break;
1017 #endif
1018 #ifdef CONFIG_ARCH_OMAP16XX
1019 case METHOD_GPIO_1610:
1020 reg += OMAP1610_GPIO_IRQENABLE1;
1021 mask = 0xffff;
1022 break;
1023 #endif
1024 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1025 case METHOD_GPIO_7XX:
1026 reg += OMAP7XX_GPIO_INT_MASK;
1027 mask = 0xffffffff;
1028 inv = 1;
1029 break;
1030 #endif
1031 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1032 case METHOD_GPIO_24XX:
1033 reg += OMAP24XX_GPIO_IRQENABLE1;
1034 mask = 0xffffffff;
1035 break;
1036 #endif
1037 #if defined(CONFIG_ARCH_OMAP4)
1038 case METHOD_GPIO_24XX:
1039 reg += OMAP4_GPIO_IRQSTATUSSET0;
1040 mask = 0xffffffff;
1041 break;
1042 #endif
1043 default:
1044 WARN_ON(1);
1045 return 0;
1046 }
1047
1048 l = __raw_readl(reg);
1049 if (inv)
1050 l = ~l;
1051 l &= mask;
1052 return l;
1053 }
1054
1055 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
1056 {
1057 void __iomem *reg = bank->base;
1058 u32 l;
1059
1060 switch (bank->method) {
1061 #ifdef CONFIG_ARCH_OMAP1
1062 case METHOD_MPUIO:
1063 reg += OMAP_MPUIO_GPIO_MASKIT;
1064 l = __raw_readl(reg);
1065 if (enable)
1066 l &= ~(gpio_mask);
1067 else
1068 l |= gpio_mask;
1069 break;
1070 #endif
1071 #ifdef CONFIG_ARCH_OMAP15XX
1072 case METHOD_GPIO_1510:
1073 reg += OMAP1510_GPIO_INT_MASK;
1074 l = __raw_readl(reg);
1075 if (enable)
1076 l &= ~(gpio_mask);
1077 else
1078 l |= gpio_mask;
1079 break;
1080 #endif
1081 #ifdef CONFIG_ARCH_OMAP16XX
1082 case METHOD_GPIO_1610:
1083 if (enable)
1084 reg += OMAP1610_GPIO_SET_IRQENABLE1;
1085 else
1086 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
1087 l = gpio_mask;
1088 break;
1089 #endif
1090 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1091 case METHOD_GPIO_7XX:
1092 reg += OMAP7XX_GPIO_INT_MASK;
1093 l = __raw_readl(reg);
1094 if (enable)
1095 l &= ~(gpio_mask);
1096 else
1097 l |= gpio_mask;
1098 break;
1099 #endif
1100 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1101 case METHOD_GPIO_24XX:
1102 if (enable)
1103 reg += OMAP24XX_GPIO_SETIRQENABLE1;
1104 else
1105 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
1106 l = gpio_mask;
1107 break;
1108 #endif
1109 #ifdef CONFIG_ARCH_OMAP4
1110 case METHOD_GPIO_24XX:
1111 if (enable)
1112 reg += OMAP4_GPIO_IRQSTATUSSET0;
1113 else
1114 reg += OMAP4_GPIO_IRQSTATUSCLR0;
1115 l = gpio_mask;
1116 break;
1117 #endif
1118 default:
1119 WARN_ON(1);
1120 return;
1121 }
1122 __raw_writel(l, reg);
1123 }
1124
1125 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
1126 {
1127 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
1128 }
1129
1130 /*
1131 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
1132 * 1510 does not seem to have a wake-up register. If JTAG is connected
1133 * to the target, system will wake up always on GPIO events. While
1134 * system is running all registered GPIO interrupts need to have wake-up
1135 * enabled. When system is suspended, only selected GPIO interrupts need
1136 * to have wake-up enabled.
1137 */
1138 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
1139 {
1140 unsigned long flags;
1141
1142 switch (bank->method) {
1143 #ifdef CONFIG_ARCH_OMAP16XX
1144 case METHOD_MPUIO:
1145 case METHOD_GPIO_1610:
1146 spin_lock_irqsave(&bank->lock, flags);
1147 if (enable)
1148 bank->suspend_wakeup |= (1 << gpio);
1149 else
1150 bank->suspend_wakeup &= ~(1 << gpio);
1151 spin_unlock_irqrestore(&bank->lock, flags);
1152 return 0;
1153 #endif
1154 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1155 defined(CONFIG_ARCH_OMAP4)
1156 case METHOD_GPIO_24XX:
1157 if (bank->non_wakeup_gpios & (1 << gpio)) {
1158 printk(KERN_ERR "Unable to modify wakeup on "
1159 "non-wakeup GPIO%d\n",
1160 (bank - gpio_bank) * 32 + gpio);
1161 return -EINVAL;
1162 }
1163 spin_lock_irqsave(&bank->lock, flags);
1164 if (enable)
1165 bank->suspend_wakeup |= (1 << gpio);
1166 else
1167 bank->suspend_wakeup &= ~(1 << gpio);
1168 spin_unlock_irqrestore(&bank->lock, flags);
1169 return 0;
1170 #endif
1171 default:
1172 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
1173 bank->method);
1174 return -EINVAL;
1175 }
1176 }
1177
1178 static void _reset_gpio(struct gpio_bank *bank, int gpio)
1179 {
1180 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
1181 _set_gpio_irqenable(bank, gpio, 0);
1182 _clear_gpio_irqstatus(bank, gpio);
1183 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1184 }
1185
1186 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
1187 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
1188 {
1189 unsigned int gpio = irq - IH_GPIO_BASE;
1190 struct gpio_bank *bank;
1191 int retval;
1192
1193 if (check_gpio(gpio) < 0)
1194 return -ENODEV;
1195 bank = get_irq_chip_data(irq);
1196 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
1197
1198 return retval;
1199 }
1200
1201 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
1202 {
1203 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1204 unsigned long flags;
1205
1206 spin_lock_irqsave(&bank->lock, flags);
1207
1208 /* Set trigger to none. You need to enable the desired trigger with
1209 * request_irq() or set_irq_type().
1210 */
1211 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
1212
1213 #ifdef CONFIG_ARCH_OMAP15XX
1214 if (bank->method == METHOD_GPIO_1510) {
1215 void __iomem *reg;
1216
1217 /* Claim the pin for MPU */
1218 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
1219 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
1220 }
1221 #endif
1222 spin_unlock_irqrestore(&bank->lock, flags);
1223
1224 return 0;
1225 }
1226
1227 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
1228 {
1229 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1230 unsigned long flags;
1231
1232 spin_lock_irqsave(&bank->lock, flags);
1233 #ifdef CONFIG_ARCH_OMAP16XX
1234 if (bank->method == METHOD_GPIO_1610) {
1235 /* Disable wake-up during idle for dynamic tick */
1236 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1237 __raw_writel(1 << offset, reg);
1238 }
1239 #endif
1240 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1241 defined(CONFIG_ARCH_OMAP4)
1242 if (bank->method == METHOD_GPIO_24XX) {
1243 /* Disable wake-up during idle for dynamic tick */
1244 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1245 __raw_writel(1 << offset, reg);
1246 }
1247 #endif
1248 _reset_gpio(bank, bank->chip.base + offset);
1249 spin_unlock_irqrestore(&bank->lock, flags);
1250 }
1251
1252 /*
1253 * We need to unmask the GPIO bank interrupt as soon as possible to
1254 * avoid missing GPIO interrupts for other lines in the bank.
1255 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1256 * in the bank to avoid missing nested interrupts for a GPIO line.
1257 * If we wait to unmask individual GPIO lines in the bank after the
1258 * line's interrupt handler has been run, we may miss some nested
1259 * interrupts.
1260 */
1261 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1262 {
1263 void __iomem *isr_reg = NULL;
1264 u32 isr;
1265 unsigned int gpio_irq;
1266 struct gpio_bank *bank;
1267 u32 retrigger = 0;
1268 int unmasked = 0;
1269
1270 desc->chip->ack(irq);
1271
1272 bank = get_irq_data(irq);
1273 #ifdef CONFIG_ARCH_OMAP1
1274 if (bank->method == METHOD_MPUIO)
1275 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
1276 #endif
1277 #ifdef CONFIG_ARCH_OMAP15XX
1278 if (bank->method == METHOD_GPIO_1510)
1279 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1280 #endif
1281 #if defined(CONFIG_ARCH_OMAP16XX)
1282 if (bank->method == METHOD_GPIO_1610)
1283 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1284 #endif
1285 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1286 if (bank->method == METHOD_GPIO_7XX)
1287 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
1288 #endif
1289 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1290 if (bank->method == METHOD_GPIO_24XX)
1291 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1292 #endif
1293 #if defined(CONFIG_ARCH_OMAP4)
1294 if (bank->method == METHOD_GPIO_24XX)
1295 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
1296 #endif
1297 while(1) {
1298 u32 isr_saved, level_mask = 0;
1299 u32 enabled;
1300
1301 enabled = _get_gpio_irqbank_mask(bank);
1302 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1303
1304 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1305 isr &= 0x0000ffff;
1306
1307 if (cpu_class_is_omap2()) {
1308 level_mask = bank->level_mask & enabled;
1309 }
1310
1311 /* clear edge sensitive interrupts before handler(s) are
1312 called so that we don't miss any interrupt occurred while
1313 executing them */
1314 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1315 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1316 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1317
1318 /* if there is only edge sensitive GPIO pin interrupts
1319 configured, we could unmask GPIO bank interrupt immediately */
1320 if (!level_mask && !unmasked) {
1321 unmasked = 1;
1322 desc->chip->unmask(irq);
1323 }
1324
1325 isr |= retrigger;
1326 retrigger = 0;
1327 if (!isr)
1328 break;
1329
1330 gpio_irq = bank->virtual_irq_start;
1331 for (; isr != 0; isr >>= 1, gpio_irq++) {
1332 if (!(isr & 1))
1333 continue;
1334
1335 generic_handle_irq(gpio_irq);
1336 }
1337 }
1338 /* if bank has any level sensitive GPIO pin interrupt
1339 configured, we must unmask the bank interrupt only after
1340 handler(s) are executed in order to avoid spurious bank
1341 interrupt */
1342 if (!unmasked)
1343 desc->chip->unmask(irq);
1344
1345 }
1346
1347 static void gpio_irq_shutdown(unsigned int irq)
1348 {
1349 unsigned int gpio = irq - IH_GPIO_BASE;
1350 struct gpio_bank *bank = get_irq_chip_data(irq);
1351
1352 _reset_gpio(bank, gpio);
1353 }
1354
1355 static void gpio_ack_irq(unsigned int irq)
1356 {
1357 unsigned int gpio = irq - IH_GPIO_BASE;
1358 struct gpio_bank *bank = get_irq_chip_data(irq);
1359
1360 _clear_gpio_irqstatus(bank, gpio);
1361 }
1362
1363 static void gpio_mask_irq(unsigned int irq)
1364 {
1365 unsigned int gpio = irq - IH_GPIO_BASE;
1366 struct gpio_bank *bank = get_irq_chip_data(irq);
1367
1368 _set_gpio_irqenable(bank, gpio, 0);
1369 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1370 }
1371
1372 static void gpio_unmask_irq(unsigned int irq)
1373 {
1374 unsigned int gpio = irq - IH_GPIO_BASE;
1375 struct gpio_bank *bank = get_irq_chip_data(irq);
1376 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1377 struct irq_desc *desc = irq_to_desc(irq);
1378 u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
1379
1380 if (trigger)
1381 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
1382
1383 /* For level-triggered GPIOs, the clearing must be done after
1384 * the HW source is cleared, thus after the handler has run */
1385 if (bank->level_mask & irq_mask) {
1386 _set_gpio_irqenable(bank, gpio, 0);
1387 _clear_gpio_irqstatus(bank, gpio);
1388 }
1389
1390 _set_gpio_irqenable(bank, gpio, 1);
1391 }
1392
1393 static struct irq_chip gpio_irq_chip = {
1394 .name = "GPIO",
1395 .shutdown = gpio_irq_shutdown,
1396 .ack = gpio_ack_irq,
1397 .mask = gpio_mask_irq,
1398 .unmask = gpio_unmask_irq,
1399 .set_type = gpio_irq_type,
1400 .set_wake = gpio_wake_enable,
1401 };
1402
1403 /*---------------------------------------------------------------------*/
1404
1405 #ifdef CONFIG_ARCH_OMAP1
1406
1407 /* MPUIO uses the always-on 32k clock */
1408
1409 static void mpuio_ack_irq(unsigned int irq)
1410 {
1411 /* The ISR is reset automatically, so do nothing here. */
1412 }
1413
1414 static void mpuio_mask_irq(unsigned int irq)
1415 {
1416 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1417 struct gpio_bank *bank = get_irq_chip_data(irq);
1418
1419 _set_gpio_irqenable(bank, gpio, 0);
1420 }
1421
1422 static void mpuio_unmask_irq(unsigned int irq)
1423 {
1424 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1425 struct gpio_bank *bank = get_irq_chip_data(irq);
1426
1427 _set_gpio_irqenable(bank, gpio, 1);
1428 }
1429
1430 static struct irq_chip mpuio_irq_chip = {
1431 .name = "MPUIO",
1432 .ack = mpuio_ack_irq,
1433 .mask = mpuio_mask_irq,
1434 .unmask = mpuio_unmask_irq,
1435 .set_type = gpio_irq_type,
1436 #ifdef CONFIG_ARCH_OMAP16XX
1437 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1438 .set_wake = gpio_wake_enable,
1439 #endif
1440 };
1441
1442
1443 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1444
1445
1446 #ifdef CONFIG_ARCH_OMAP16XX
1447
1448 #include <linux/platform_device.h>
1449
1450 static int omap_mpuio_suspend_noirq(struct device *dev)
1451 {
1452 struct platform_device *pdev = to_platform_device(dev);
1453 struct gpio_bank *bank = platform_get_drvdata(pdev);
1454 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1455 unsigned long flags;
1456
1457 spin_lock_irqsave(&bank->lock, flags);
1458 bank->saved_wakeup = __raw_readl(mask_reg);
1459 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1460 spin_unlock_irqrestore(&bank->lock, flags);
1461
1462 return 0;
1463 }
1464
1465 static int omap_mpuio_resume_noirq(struct device *dev)
1466 {
1467 struct platform_device *pdev = to_platform_device(dev);
1468 struct gpio_bank *bank = platform_get_drvdata(pdev);
1469 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1470 unsigned long flags;
1471
1472 spin_lock_irqsave(&bank->lock, flags);
1473 __raw_writel(bank->saved_wakeup, mask_reg);
1474 spin_unlock_irqrestore(&bank->lock, flags);
1475
1476 return 0;
1477 }
1478
1479 static struct dev_pm_ops omap_mpuio_dev_pm_ops = {
1480 .suspend_noirq = omap_mpuio_suspend_noirq,
1481 .resume_noirq = omap_mpuio_resume_noirq,
1482 };
1483
1484 /* use platform_driver for this, now that there's no longer any
1485 * point to sys_device (other than not disturbing old code).
1486 */
1487 static struct platform_driver omap_mpuio_driver = {
1488 .driver = {
1489 .name = "mpuio",
1490 .pm = &omap_mpuio_dev_pm_ops,
1491 },
1492 };
1493
1494 static struct platform_device omap_mpuio_device = {
1495 .name = "mpuio",
1496 .id = -1,
1497 .dev = {
1498 .driver = &omap_mpuio_driver.driver,
1499 }
1500 /* could list the /proc/iomem resources */
1501 };
1502
1503 static inline void mpuio_init(void)
1504 {
1505 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1506
1507 if (platform_driver_register(&omap_mpuio_driver) == 0)
1508 (void) platform_device_register(&omap_mpuio_device);
1509 }
1510
1511 #else
1512 static inline void mpuio_init(void) {}
1513 #endif /* 16xx */
1514
1515 #else
1516
1517 extern struct irq_chip mpuio_irq_chip;
1518
1519 #define bank_is_mpuio(bank) 0
1520 static inline void mpuio_init(void) {}
1521
1522 #endif
1523
1524 /*---------------------------------------------------------------------*/
1525
1526 /* REVISIT these are stupid implementations! replace by ones that
1527 * don't switch on METHOD_* and which mostly avoid spinlocks
1528 */
1529
1530 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1531 {
1532 struct gpio_bank *bank;
1533 unsigned long flags;
1534
1535 bank = container_of(chip, struct gpio_bank, chip);
1536 spin_lock_irqsave(&bank->lock, flags);
1537 _set_gpio_direction(bank, offset, 1);
1538 spin_unlock_irqrestore(&bank->lock, flags);
1539 return 0;
1540 }
1541
1542 static int gpio_is_input(struct gpio_bank *bank, int mask)
1543 {
1544 void __iomem *reg = bank->base;
1545
1546 switch (bank->method) {
1547 case METHOD_MPUIO:
1548 reg += OMAP_MPUIO_IO_CNTL;
1549 break;
1550 case METHOD_GPIO_1510:
1551 reg += OMAP1510_GPIO_DIR_CONTROL;
1552 break;
1553 case METHOD_GPIO_1610:
1554 reg += OMAP1610_GPIO_DIRECTION;
1555 break;
1556 case METHOD_GPIO_7XX:
1557 reg += OMAP7XX_GPIO_DIR_CONTROL;
1558 break;
1559 case METHOD_GPIO_24XX:
1560 reg += OMAP24XX_GPIO_OE;
1561 break;
1562 }
1563 return __raw_readl(reg) & mask;
1564 }
1565
1566 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1567 {
1568 struct gpio_bank *bank;
1569 void __iomem *reg;
1570 int gpio;
1571 u32 mask;
1572
1573 gpio = chip->base + offset;
1574 bank = get_gpio_bank(gpio);
1575 reg = bank->base;
1576 mask = 1 << get_gpio_index(gpio);
1577
1578 if (gpio_is_input(bank, mask))
1579 return _get_gpio_datain(bank, gpio);
1580 else
1581 return _get_gpio_dataout(bank, gpio);
1582 }
1583
1584 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1585 {
1586 struct gpio_bank *bank;
1587 unsigned long flags;
1588
1589 bank = container_of(chip, struct gpio_bank, chip);
1590 spin_lock_irqsave(&bank->lock, flags);
1591 _set_gpio_dataout(bank, offset, value);
1592 _set_gpio_direction(bank, offset, 0);
1593 spin_unlock_irqrestore(&bank->lock, flags);
1594 return 0;
1595 }
1596
1597 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1598 {
1599 struct gpio_bank *bank;
1600 unsigned long flags;
1601
1602 bank = container_of(chip, struct gpio_bank, chip);
1603 spin_lock_irqsave(&bank->lock, flags);
1604 _set_gpio_dataout(bank, offset, value);
1605 spin_unlock_irqrestore(&bank->lock, flags);
1606 }
1607
1608 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1609 {
1610 struct gpio_bank *bank;
1611
1612 bank = container_of(chip, struct gpio_bank, chip);
1613 return bank->virtual_irq_start + offset;
1614 }
1615
1616 /*---------------------------------------------------------------------*/
1617
1618 static int initialized;
1619 #if !(defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4))
1620 static struct clk * gpio_ick;
1621 #endif
1622
1623 #if defined(CONFIG_ARCH_OMAP2)
1624 static struct clk * gpio_fck;
1625 #endif
1626
1627 #if defined(CONFIG_ARCH_OMAP2430)
1628 static struct clk * gpio5_ick;
1629 static struct clk * gpio5_fck;
1630 #endif
1631
1632 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1633 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1634
1635 /*
1636 * Following pad init code in addition to the context / restore hooks are
1637 * needed to fix glitches in GPIO outputs during off-mode. See OMAP3
1638 * errate section 1.158
1639 */
1640 static int __init omap3_gpio_pads_init(void)
1641 {
1642 int i, j, min, max, gpio_amt;
1643 u16 offset;
1644
1645 gpio_amt = 0;
1646
1647 for (i = 0; i < ARRAY_SIZE(gpio_pads_config); i++) {
1648 min = gpio_pads_config[i].min;
1649 max = gpio_pads_config[i].max;
1650 offset = gpio_pads_config[i].offset;
1651
1652 for (j = min; j <= max; j++) {
1653 /* Check if pad has been configured as GPIO. */
1654 if ((omap_ctrl_readw(offset) &
1655 OMAP34XX_MUX_MODE7) == OMAP34XX_MUX_MODE4) {
1656 gpio_pad_map[j] = offset;
1657 if (j > 31)
1658 gpio_amt++;
1659 }
1660 offset += 2;
1661 }
1662 }
1663 gpio_pads = kmalloc(sizeof(struct gpio_pad) * (gpio_amt + 1),
1664 GFP_KERNEL);
1665
1666 if (gpio_pads == NULL) {
1667 printk(KERN_ERR "FATAL: Failed to allocate gpio_pads\n");
1668 return -ENOMEM;
1669 }
1670
1671 gpio_amt = 0;
1672 for (i = 0; i < OMAP34XX_GPIO_AMT; i++) {
1673 /*
1674 * First module (gpio 0...31) is ignored as it is
1675 * in wakeup domain and does not need special
1676 * handling during off mode.
1677 */
1678 if (gpio_pad_map[i] && i > 31) {
1679 gpio_pads[gpio_amt].gpio = i;
1680 gpio_pads[gpio_amt].offset = gpio_pad_map[i];
1681 gpio_amt++;
1682 }
1683 }
1684 gpio_pads[gpio_amt].gpio = -1;
1685 return 0;
1686 }
1687 late_initcall(omap3_gpio_pads_init);
1688 #endif
1689
1690 static void __init omap_gpio_show_rev(void)
1691 {
1692 u32 rev;
1693
1694 if (cpu_is_omap16xx())
1695 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1696 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1697 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1698 else if (cpu_is_omap44xx())
1699 rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
1700 else
1701 return;
1702
1703 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1704 (rev >> 4) & 0x0f, rev & 0x0f);
1705 }
1706
1707 /* This lock class tells lockdep that GPIO irqs are in a different
1708 * category than their parents, so it won't report false recursion.
1709 */
1710 static struct lock_class_key gpio_lock_class;
1711
1712 static int __init _omap_gpio_init(void)
1713 {
1714 int i;
1715 int gpio = 0;
1716 struct gpio_bank *bank;
1717 int bank_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */
1718 char clk_name[11];
1719
1720 initialized = 1;
1721
1722 #if defined(CONFIG_ARCH_OMAP1)
1723 if (cpu_is_omap15xx()) {
1724 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1725 if (IS_ERR(gpio_ick))
1726 printk("Could not get arm_gpio_ck\n");
1727 else
1728 clk_enable(gpio_ick);
1729 }
1730 #endif
1731 #if defined(CONFIG_ARCH_OMAP2)
1732 if (cpu_class_is_omap2()) {
1733 gpio_ick = clk_get(NULL, "gpios_ick");
1734 if (IS_ERR(gpio_ick))
1735 printk("Could not get gpios_ick\n");
1736 else
1737 clk_enable(gpio_ick);
1738 gpio_fck = clk_get(NULL, "gpios_fck");
1739 if (IS_ERR(gpio_fck))
1740 printk("Could not get gpios_fck\n");
1741 else
1742 clk_enable(gpio_fck);
1743
1744 /*
1745 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1746 */
1747 #if defined(CONFIG_ARCH_OMAP2430)
1748 if (cpu_is_omap2430()) {
1749 gpio5_ick = clk_get(NULL, "gpio5_ick");
1750 if (IS_ERR(gpio5_ick))
1751 printk("Could not get gpio5_ick\n");
1752 else
1753 clk_enable(gpio5_ick);
1754 gpio5_fck = clk_get(NULL, "gpio5_fck");
1755 if (IS_ERR(gpio5_fck))
1756 printk("Could not get gpio5_fck\n");
1757 else
1758 clk_enable(gpio5_fck);
1759 }
1760 #endif
1761 }
1762 #endif
1763
1764 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1765 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1766 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1767 sprintf(clk_name, "gpio%d_ick", i + 1);
1768 gpio_iclks[i] = clk_get(NULL, clk_name);
1769 if (IS_ERR(gpio_iclks[i]))
1770 printk(KERN_ERR "Could not get %s\n", clk_name);
1771 else
1772 clk_enable(gpio_iclks[i]);
1773 }
1774 }
1775 #endif
1776
1777
1778 #ifdef CONFIG_ARCH_OMAP15XX
1779 if (cpu_is_omap15xx()) {
1780 gpio_bank_count = 2;
1781 gpio_bank = gpio_bank_1510;
1782 bank_size = SZ_2K;
1783 }
1784 #endif
1785 #if defined(CONFIG_ARCH_OMAP16XX)
1786 if (cpu_is_omap16xx()) {
1787 gpio_bank_count = 5;
1788 gpio_bank = gpio_bank_1610;
1789 bank_size = SZ_2K;
1790 }
1791 #endif
1792 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1793 if (cpu_is_omap7xx()) {
1794 gpio_bank_count = 7;
1795 gpio_bank = gpio_bank_7xx;
1796 bank_size = SZ_2K;
1797 }
1798 #endif
1799 #ifdef CONFIG_ARCH_OMAP24XX
1800 if (cpu_is_omap242x()) {
1801 gpio_bank_count = 4;
1802 gpio_bank = gpio_bank_242x;
1803 }
1804 if (cpu_is_omap243x()) {
1805 gpio_bank_count = 5;
1806 gpio_bank = gpio_bank_243x;
1807 }
1808 #endif
1809 #ifdef CONFIG_ARCH_OMAP34XX
1810 if (cpu_is_omap34xx()) {
1811 gpio_bank_count = OMAP34XX_NR_GPIOS;
1812 gpio_bank = gpio_bank_34xx;
1813 }
1814 #endif
1815 #ifdef CONFIG_ARCH_OMAP4
1816 if (cpu_is_omap44xx()) {
1817 gpio_bank_count = OMAP34XX_NR_GPIOS;
1818 gpio_bank = gpio_bank_44xx;
1819 }
1820 #endif
1821 for (i = 0; i < gpio_bank_count; i++) {
1822 int j, gpio_count = 16;
1823
1824 bank = &gpio_bank[i];
1825 spin_lock_init(&bank->lock);
1826
1827 /* Static mapping, never released */
1828 bank->base = ioremap(bank->pbase, bank_size);
1829 if (!bank->base) {
1830 printk(KERN_ERR "Could not ioremap gpio bank%i\n", i);
1831 continue;
1832 }
1833
1834 if (bank_is_mpuio(bank))
1835 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
1836 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1837 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1838 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1839 }
1840 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1841 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1842 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1843 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1844 }
1845 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1846 __raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK);
1847 __raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS);
1848
1849 gpio_count = 32; /* 7xx has 32-bit GPIOs */
1850 }
1851
1852 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1853 defined(CONFIG_ARCH_OMAP4)
1854 if (bank->method == METHOD_GPIO_24XX) {
1855 static const u32 non_wakeup_gpios[] = {
1856 0xe203ffc0, 0x08700040
1857 };
1858 if (cpu_is_omap44xx()) {
1859 __raw_writel(0xffffffff, bank->base +
1860 OMAP4_GPIO_IRQSTATUSCLR0);
1861 __raw_writew(0x0015, bank->base +
1862 OMAP4_GPIO_SYSCONFIG);
1863 __raw_writel(0x00000000, bank->base +
1864 OMAP4_GPIO_DEBOUNCENABLE);
1865 /* Initialize interface clock ungated, module enabled */
1866 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1867 } else {
1868 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1869 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1870 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1871 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_DEBOUNCE_EN);
1872
1873 /* Initialize interface clock ungated, module enabled */
1874 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1875 }
1876 if (cpu_is_omap24xx() &&
1877 i < ARRAY_SIZE(non_wakeup_gpios))
1878 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1879 gpio_count = 32;
1880 }
1881 #endif
1882 /* REVISIT eventually switch from OMAP-specific gpio structs
1883 * over to the generic ones
1884 */
1885 bank->chip.request = omap_gpio_request;
1886 bank->chip.free = omap_gpio_free;
1887 bank->chip.direction_input = gpio_input;
1888 bank->chip.get = gpio_get;
1889 bank->chip.direction_output = gpio_output;
1890 bank->chip.set = gpio_set;
1891 bank->chip.to_irq = gpio_2irq;
1892 if (bank_is_mpuio(bank)) {
1893 bank->chip.label = "mpuio";
1894 #ifdef CONFIG_ARCH_OMAP16XX
1895 bank->chip.dev = &omap_mpuio_device.dev;
1896 #endif
1897 bank->chip.base = OMAP_MPUIO(0);
1898 } else {
1899 bank->chip.label = "gpio";
1900 bank->chip.base = gpio;
1901 gpio += gpio_count;
1902 }
1903 bank->chip.ngpio = gpio_count;
1904
1905 gpiochip_add(&bank->chip);
1906
1907 for (j = bank->virtual_irq_start;
1908 j < bank->virtual_irq_start + gpio_count; j++) {
1909 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1910 set_irq_chip_data(j, bank);
1911 if (bank_is_mpuio(bank))
1912 set_irq_chip(j, &mpuio_irq_chip);
1913 else
1914 set_irq_chip(j, &gpio_irq_chip);
1915 set_irq_handler(j, handle_simple_irq);
1916 set_irq_flags(j, IRQF_VALID);
1917 }
1918 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1919 set_irq_data(bank->irq, bank);
1920
1921 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1922 sprintf(clk_name, "gpio%d_dbck", i + 1);
1923 bank->dbck = clk_get(NULL, clk_name);
1924 if (IS_ERR(bank->dbck))
1925 printk(KERN_ERR "Could not get %s\n", clk_name);
1926 }
1927 }
1928
1929 /* Enable system clock for GPIO module.
1930 * The CAM_CLK_CTRL *is* really the right place. */
1931 if (cpu_is_omap16xx())
1932 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1933
1934 /* Enable autoidle for the OCP interface */
1935 if (cpu_is_omap24xx())
1936 omap_writel(1 << 0, 0x48019010);
1937 if (cpu_is_omap34xx())
1938 omap_writel(1 << 0, 0x48306814);
1939
1940 omap_gpio_show_rev();
1941
1942 return 0;
1943 }
1944
1945 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
1946 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
1947 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1948 {
1949 int i;
1950
1951 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1952 return 0;
1953
1954 for (i = 0; i < gpio_bank_count; i++) {
1955 struct gpio_bank *bank = &gpio_bank[i];
1956 void __iomem *wake_status;
1957 void __iomem *wake_clear;
1958 void __iomem *wake_set;
1959 unsigned long flags;
1960
1961 switch (bank->method) {
1962 #ifdef CONFIG_ARCH_OMAP16XX
1963 case METHOD_GPIO_1610:
1964 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1965 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1966 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1967 break;
1968 #endif
1969 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1970 case METHOD_GPIO_24XX:
1971 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1972 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1973 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1974 break;
1975 #endif
1976 #ifdef CONFIG_ARCH_OMAP4
1977 case METHOD_GPIO_24XX:
1978 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1979 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1980 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1981 break;
1982 #endif
1983 default:
1984 continue;
1985 }
1986
1987 spin_lock_irqsave(&bank->lock, flags);
1988 bank->saved_wakeup = __raw_readl(wake_status);
1989 __raw_writel(0xffffffff, wake_clear);
1990 __raw_writel(bank->suspend_wakeup, wake_set);
1991 spin_unlock_irqrestore(&bank->lock, flags);
1992
1993 #ifdef CONFIG_ARCH_OMAP34XX
1994 if (bank->method == METHOD_GPIO_24XX) {
1995 int j;
1996 for (j = 0; j < 32; j++) {
1997 int offset = gpio_pad_map[j + i * 32];
1998 u16 v;
1999
2000 if (!offset)
2001 continue;
2002
2003 v = omap_ctrl_readw(offset);
2004 if (bank->suspend_wakeup & (1 << j))
2005 v |= OMAP3_PADCONF_WAKEUPENABLE0;
2006 else
2007 v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
2008 omap_ctrl_writew(v, offset);
2009 }
2010 }
2011 #endif
2012 }
2013
2014 return 0;
2015 }
2016
2017 static int omap_gpio_resume(struct sys_device *dev)
2018 {
2019 int i;
2020
2021 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
2022 return 0;
2023
2024 for (i = 0; i < gpio_bank_count; i++) {
2025 struct gpio_bank *bank = &gpio_bank[i];
2026 void __iomem *wake_clear;
2027 void __iomem *wake_set;
2028 unsigned long flags;
2029
2030 switch (bank->method) {
2031 #ifdef CONFIG_ARCH_OMAP16XX
2032 case METHOD_GPIO_1610:
2033 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
2034 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
2035 break;
2036 #endif
2037 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
2038 case METHOD_GPIO_24XX:
2039 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
2040 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
2041 break;
2042 #endif
2043 #ifdef CONFIG_ARCH_OMAP4
2044 case METHOD_GPIO_24XX:
2045 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
2046 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
2047 break;
2048 #endif
2049 default:
2050 continue;
2051 }
2052
2053 spin_lock_irqsave(&bank->lock, flags);
2054 __raw_writel(0xffffffff, wake_clear);
2055 __raw_writel(bank->saved_wakeup, wake_set);
2056 spin_unlock_irqrestore(&bank->lock, flags);
2057 }
2058
2059 return 0;
2060 }
2061
2062 static struct sysdev_class omap_gpio_sysclass = {
2063 .name = "gpio",
2064 .suspend = omap_gpio_suspend,
2065 .resume = omap_gpio_resume,
2066 };
2067
2068 static struct sys_device omap_gpio_device = {
2069 .id = 0,
2070 .cls = &omap_gpio_sysclass,
2071 };
2072
2073 #endif
2074
2075 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
2076 defined(CONFIG_ARCH_OMAP4)
2077
2078 static int workaround_enabled;
2079
2080 void omap2_gpio_prepare_for_idle(int power_state)
2081 {
2082 int i, c = 0;
2083 int min = 0;
2084
2085 if (cpu_is_omap34xx())
2086 min = 1;
2087
2088 for (i = min; i < gpio_bank_count; i++) {
2089 struct gpio_bank *bank = &gpio_bank[i];
2090 u32 l1, l2;
2091
2092 if (cpu_is_omap34xx() && bank->dbck_enable_mask)
2093 clk_disable(bank->dbck);
2094
2095 if (power_state > PWRDM_POWER_OFF)
2096 continue;
2097
2098 /* If going to OFF, remove triggering for all
2099 * non-wakeup GPIOs. Otherwise spurious IRQs will be
2100 * generated. See OMAP2420 Errata item 1.101. */
2101 if (!(bank->enabled_non_wakeup_gpios))
2102 continue;
2103 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
2104 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
2105 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2106 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
2107 #endif
2108 #ifdef CONFIG_ARCH_OMAP4
2109 bank->saved_datain = __raw_readl(bank->base +
2110 OMAP4_GPIO_DATAIN);
2111 l1 = __raw_readl(bank->base + OMAP4_GPIO_FALLINGDETECT);
2112 l2 = __raw_readl(bank->base + OMAP4_GPIO_RISINGDETECT);
2113 #endif
2114 bank->saved_fallingdetect = l1;
2115 bank->saved_risingdetect = l2;
2116 l1 &= ~bank->enabled_non_wakeup_gpios;
2117 l2 &= ~bank->enabled_non_wakeup_gpios;
2118 if (cpu_is_omap24xx()) {
2119 __raw_writel(l1, bank->base +
2120 OMAP24XX_GPIO_FALLINGDETECT);
2121 __raw_writel(l2, bank->base +
2122 OMAP24XX_GPIO_RISINGDETECT);
2123 }
2124 c++;
2125 }
2126 if (!c) {
2127 workaround_enabled = 0;
2128 return;
2129 }
2130 workaround_enabled = 1;
2131 }
2132
2133 void omap2_gpio_resume_after_idle(void)
2134 {
2135 int i;
2136 int min = 0;
2137
2138 if (cpu_is_omap34xx())
2139 min = 1;
2140 for (i = min; i < gpio_bank_count; i++) {
2141 struct gpio_bank *bank = &gpio_bank[i];
2142 u32 l, gen, gen0, gen1;
2143
2144 if (cpu_is_omap34xx() && bank->dbck_enable_mask)
2145 clk_enable(bank->dbck);
2146
2147 if (!workaround_enabled)
2148 continue;
2149
2150 if (!(bank->enabled_non_wakeup_gpios))
2151 continue;
2152 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
2153 __raw_writel(bank->saved_fallingdetect,
2154 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2155 __raw_writel(bank->saved_risingdetect,
2156 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2157 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
2158 #endif
2159 #ifdef CONFIG_ARCH_OMAP4
2160 __raw_writel(bank->saved_fallingdetect,
2161 bank->base + OMAP4_GPIO_FALLINGDETECT);
2162 __raw_writel(bank->saved_risingdetect,
2163 bank->base + OMAP4_GPIO_RISINGDETECT);
2164 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
2165 #endif
2166 /* Check if any of the non-wakeup interrupt GPIOs have changed
2167 * state. If so, generate an IRQ by software. This is
2168 * horribly racy, but it's the best we can do to work around
2169 * this silicon bug. */
2170 l ^= bank->saved_datain;
2171 l &= bank->enabled_non_wakeup_gpios;
2172
2173 /*
2174 * No need to generate IRQs for the rising edge for gpio IRQs
2175 * configured with falling edge only; and vice versa.
2176 */
2177 gen0 = l & bank->saved_fallingdetect;
2178 gen0 &= bank->saved_datain;
2179
2180 gen1 = l & bank->saved_risingdetect;
2181 gen1 &= ~(bank->saved_datain);
2182
2183 /* FIXME: Consider GPIO IRQs with level detections properly! */
2184 gen = l & (~(bank->saved_fallingdetect) &
2185 ~(bank->saved_risingdetect));
2186 /* Consider all GPIO IRQs needed to be updated */
2187 gen |= gen0 | gen1;
2188
2189 if (gen) {
2190 u32 old0, old1;
2191 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
2192 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2193 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2194 __raw_writel(old0 | gen, bank->base +
2195 OMAP24XX_GPIO_LEVELDETECT0);
2196 __raw_writel(old1 | gen, bank->base +
2197 OMAP24XX_GPIO_LEVELDETECT1);
2198 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2199 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2200 #endif
2201 #ifdef CONFIG_ARCH_OMAP4
2202 old0 = __raw_readl(bank->base +
2203 OMAP4_GPIO_LEVELDETECT0);
2204 old1 = __raw_readl(bank->base +
2205 OMAP4_GPIO_LEVELDETECT1);
2206 __raw_writel(old0 | l, bank->base +
2207 OMAP4_GPIO_LEVELDETECT0);
2208 __raw_writel(old1 | l, bank->base +
2209 OMAP4_GPIO_LEVELDETECT1);
2210 __raw_writel(old0, bank->base +
2211 OMAP4_GPIO_LEVELDETECT0);
2212 __raw_writel(old1, bank->base +
2213 OMAP4_GPIO_LEVELDETECT1);
2214 #endif
2215 }
2216 }
2217
2218 }
2219
2220 #endif
2221
2222 #ifdef CONFIG_ARCH_OMAP34XX
2223 /* save the registers of bank 2-6 */
2224 void omap_gpio_save_context(void)
2225 {
2226 int i;
2227 struct gpio_bank *bank;
2228 int n;
2229 u16 offset, conf;
2230 u32 out, pin;
2231 struct gpio_pad *pad;
2232 u32 tmp_oe[OMAP34XX_NR_GPIOS];
2233
2234 /* saving banks from 2-6 only since GPIO1 is in WKUP */
2235 for (i = 1; i < gpio_bank_count; i++) {
2236 bank = &gpio_bank[i];
2237 gpio_context[i].sysconfig =
2238 __raw_readl(bank->base + OMAP24XX_GPIO_SYSCONFIG);
2239 gpio_context[i].irqenable1 =
2240 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
2241 gpio_context[i].irqenable2 =
2242 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
2243 gpio_context[i].wake_en =
2244 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
2245 gpio_context[i].ctrl =
2246 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
2247 gpio_context[i].oe =
2248 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
2249 tmp_oe[i] = gpio_context[i].oe;
2250 gpio_context[i].leveldetect0 =
2251 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2252 gpio_context[i].leveldetect1 =
2253 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2254 gpio_context[i].risingdetect =
2255 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
2256 gpio_context[i].fallingdetect =
2257 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2258 gpio_context[i].dataout =
2259 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
2260 }
2261 pad = gpio_pads;
2262
2263 if (pad == NULL)
2264 return;
2265
2266 while (pad->gpio >= 0) {
2267 /* n = gpio number, 0..191 */
2268 n = pad->gpio;
2269 /* i = gpio bank, 0..5 */
2270 i = n >> 5;
2271 /* offset of padconf register */
2272 offset = pad->offset;
2273 bank = &gpio_bank[i];
2274 /* bit position of gpio in the bank 0..31 */
2275 pin = 1 << (n & 0x1f);
2276
2277 /* check if gpio is configured as output => need hack */
2278 if (!(tmp_oe[i] & pin)) {
2279 /* save current padconf setting */
2280 pad->save = omap_ctrl_readw(offset);
2281 out = gpio_context[i].dataout;
2282 if (out & pin)
2283 /* High: PU + input */
2284 conf = OMAP34XX_PAD_IN_PU_GPIO;
2285 else
2286 /* Low: PD + input */
2287 conf = OMAP34XX_PAD_IN_PD_GPIO;
2288 /* Set PAD to GPIO + input */
2289 omap_ctrl_writew(conf, offset);
2290 /* Set GPIO to input */
2291 tmp_oe[i] |= pin;
2292 __raw_writel(tmp_oe[i],
2293 bank->base + OMAP24XX_GPIO_OE);
2294 /* Set PAD to safe mode */
2295 omap_ctrl_writew(conf | OMAP34XX_PAD_SAFE_MODE, offset);
2296 } else
2297 pad->save = 0;
2298 pad++;
2299 }
2300 }
2301
2302 /* restore the required registers of bank 2-6 */
2303 void omap_gpio_restore_context(void)
2304 {
2305 int i;
2306
2307 for (i = 1; i < gpio_bank_count; i++) {
2308 struct gpio_bank *bank = &gpio_bank[i];
2309 __raw_writel(gpio_context[i].sysconfig,
2310 bank->base + OMAP24XX_GPIO_SYSCONFIG);
2311 __raw_writel(gpio_context[i].irqenable1,
2312 bank->base + OMAP24XX_GPIO_IRQENABLE1);
2313 __raw_writel(gpio_context[i].irqenable2,
2314 bank->base + OMAP24XX_GPIO_IRQENABLE2);
2315 __raw_writel(gpio_context[i].wake_en,
2316 bank->base + OMAP24XX_GPIO_WAKE_EN);
2317 __raw_writel(gpio_context[i].ctrl,
2318 bank->base + OMAP24XX_GPIO_CTRL);
2319 __raw_writel(gpio_context[i].leveldetect0,
2320 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2321 __raw_writel(gpio_context[i].leveldetect1,
2322 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2323 __raw_writel(gpio_context[i].risingdetect,
2324 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2325 __raw_writel(gpio_context[i].fallingdetect,
2326 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2327 __raw_writel(gpio_context[i].dataout,
2328 bank->base + OMAP24XX_GPIO_DATAOUT);
2329 __raw_writel(gpio_context[i].oe,
2330 bank->base + OMAP24XX_GPIO_OE);
2331 }
2332 }
2333
2334 void omap3_gpio_restore_pad_context(int restore_oe)
2335 {
2336 struct gpio_pad *pad;
2337 int i;
2338
2339 pad = gpio_pads;
2340
2341 if (restore_oe) {
2342 for (i = 1; i < gpio_bank_count; i++) {
2343 struct gpio_bank *bank = &gpio_bank[i];
2344 __raw_writel(gpio_context[i].oe,
2345 bank->base + OMAP24XX_GPIO_OE);
2346 }
2347 }
2348
2349 if (pad == NULL)
2350 return;
2351
2352 while (pad->gpio >= 0) {
2353 if (pad->save)
2354 omap_ctrl_writew(pad->save, pad->offset);
2355 pad++;
2356 }
2357 }
2358 #endif
2359
2360 /*
2361 * This may get called early from board specific init
2362 * for boards that have interrupts routed via FPGA.
2363 */
2364 int __init omap_gpio_init(void)
2365 {
2366 if (!initialized)
2367 return _omap_gpio_init();
2368 else
2369 return 0;
2370 }
2371
2372 static int __init omap_gpio_sysinit(void)
2373 {
2374 int ret = 0;
2375
2376 if (!initialized)
2377 ret = _omap_gpio_init();
2378
2379 mpuio_init();
2380
2381 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
2382 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
2383 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
2384 if (ret == 0) {
2385 ret = sysdev_class_register(&omap_gpio_sysclass);
2386 if (ret == 0)
2387 ret = sysdev_register(&omap_gpio_device);
2388 }
2389 }
2390 #endif
2391
2392 return ret;
2393 }
2394
2395 arch_initcall(omap_gpio_sysinit);
2396
2397
2398 #ifdef CONFIG_DEBUG_FS
2399
2400 #include <linux/debugfs.h>
2401 #include <linux/seq_file.h>
2402
2403 static int dbg_gpio_show(struct seq_file *s, void *unused)
2404 {
2405 unsigned i, j, gpio;
2406
2407 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
2408 struct gpio_bank *bank = gpio_bank + i;
2409 unsigned bankwidth = 16;
2410 u32 mask = 1;
2411
2412 if (bank_is_mpuio(bank))
2413 gpio = OMAP_MPUIO(0);
2414 else if (cpu_class_is_omap2() || cpu_is_omap7xx())
2415 bankwidth = 32;
2416
2417 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
2418 unsigned irq, value, is_in, irqstat;
2419 const char *label;
2420
2421 label = gpiochip_is_requested(&bank->chip, j);
2422 if (!label)
2423 continue;
2424
2425 irq = bank->virtual_irq_start + j;
2426 value = gpio_get_value(gpio);
2427 is_in = gpio_is_input(bank, mask);
2428
2429 if (bank_is_mpuio(bank))
2430 seq_printf(s, "MPUIO %2d ", j);
2431 else
2432 seq_printf(s, "GPIO %3d ", gpio);
2433 seq_printf(s, "(%-20.20s): %s %s",
2434 label,
2435 is_in ? "in " : "out",
2436 value ? "hi" : "lo");
2437
2438 /* FIXME for at least omap2, show pullup/pulldown state */
2439
2440 irqstat = irq_desc[irq].status;
2441 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
2442 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
2443 if (is_in && ((bank->suspend_wakeup & mask)
2444 || irqstat & IRQ_TYPE_SENSE_MASK)) {
2445 char *trigger = NULL;
2446
2447 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
2448 case IRQ_TYPE_EDGE_FALLING:
2449 trigger = "falling";
2450 break;
2451 case IRQ_TYPE_EDGE_RISING:
2452 trigger = "rising";
2453 break;
2454 case IRQ_TYPE_EDGE_BOTH:
2455 trigger = "bothedge";
2456 break;
2457 case IRQ_TYPE_LEVEL_LOW:
2458 trigger = "low";
2459 break;
2460 case IRQ_TYPE_LEVEL_HIGH:
2461 trigger = "high";
2462 break;
2463 case IRQ_TYPE_NONE:
2464 trigger = "(?)";
2465 break;
2466 }
2467 seq_printf(s, ", irq-%d %-8s%s",
2468 irq, trigger,
2469 (bank->suspend_wakeup & mask)
2470 ? " wakeup" : "");
2471 }
2472 #endif
2473 seq_printf(s, "\n");
2474 }
2475
2476 if (bank_is_mpuio(bank)) {
2477 seq_printf(s, "\n");
2478 gpio = 0;
2479 }
2480 }
2481 return 0;
2482 }
2483
2484 static int dbg_gpio_open(struct inode *inode, struct file *file)
2485 {
2486 return single_open(file, dbg_gpio_show, &inode->i_private);
2487 }
2488
2489 static const struct file_operations debug_fops = {
2490 .open = dbg_gpio_open,
2491 .read = seq_read,
2492 .llseek = seq_lseek,
2493 .release = single_release,
2494 };
2495
2496 static int __init omap_gpio_debuginit(void)
2497 {
2498 (void) debugfs_create_file("omap_gpio", S_IRUGO,
2499 NULL, NULL, &debug_fops);
2500 return 0;
2501 }
2502 late_initcall(omap_gpio_debuginit);
2503 #endif
Linux for Ginger Game Console