arch/arm/plat-omap/include/plat/io.h

   1 /*
   2  * arch/arm/plat-omap/include/mach/io.h
   3  *
   4  * IO definitions for TI OMAP processors and boards
   5  *
   6  * Copied from arch/arm/mach-sa1100/include/mach/io.h
   7  * Copyright (C) 1997-1999 Russell King
   8  *
   9  * Copyright (C) 2009 Texas Instruments
  10  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify it
  13  * under the terms of the GNU General Public License as published by the
  14  * Free Software Foundation; either version 2 of the License, or (at your
  15  * option) any later version.
  16  *
  17  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  18  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  19  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  20  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  23  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  24  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * You should have received a copy of the GNU General Public License along
  29  * with this program; if not, write to the Free Software Foundation, Inc.,
  30  * 675 Mass Ave, Cambridge, MA 02139, USA.
  31  *
  32  * Modifications:
  33  *  06-12-1997  RMK     Created.
  34  *  07-04-1999  RMK     Major cleanup
  35  */
  36
  37 #ifndef __ASM_ARM_ARCH_IO_H
  38 #define __ASM_ARM_ARCH_IO_H
  39
  40 #include <mach/hardware.h>
  41
  42 #define IO_SPACE_LIMIT 0xffffffff
  43
  44 /*
  45  * We don't actually have real ISA nor PCI buses, but there is so many
  46  * drivers out there that might just work if we fake them...
  47  */
  48 #define __io(a)         __typesafe_io(a)
  49 #define __mem_pci(a)    (a)
  50
  51 /*
  52  * ----------------------------------------------------------------------------
  53  * I/O mapping
  54  * ----------------------------------------------------------------------------
  55  */
  56
  57 #ifdef __ASSEMBLER__
  58 #define IOMEM(x)                (x)
  59 #else
  60 #define IOMEM(x)                ((void __force __iomem *)(x))
  61 #endif
  62
  63 #define OMAP1_IO_OFFSET         0x01000000      /* Virtual IO = 0xfefb0000 */
  64 #define OMAP1_IO_ADDRESS(pa)    IOMEM((pa) - OMAP1_IO_OFFSET)
  65
  66 #define OMAP2_L3_IO_OFFSET      0x90000000
  67 #define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */
  68
  69
  70 #define OMAP2_L4_IO_OFFSET      0xb2000000
  71 #define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */
  72
  73 #define OMAP4_L3_IO_OFFSET      0xb4000000
  74 #define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
  75
  76 #define OMAP4_L3_PER_IO_OFFSET  0xb1100000
  77 #define OMAP4_L3_PER_IO_ADDRESS(pa)     IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
  78
  79 #define OMAP4_GPMC_IO_OFFSET            0xa9000000
  80 #define OMAP4_GPMC_IO_ADDRESS(pa)       IOMEM((pa) + OMAP4_GPMC_IO_OFFSET)
  81
  82 #define OMAP2_EMU_IO_OFFSET             0xaa800000      /* Emulation */
  83 #define OMAP2_EMU_IO_ADDRESS(pa)        IOMEM((pa) + OMAP2_EMU_IO_OFFSET)
  84
  85 /*
  86  * ----------------------------------------------------------------------------
  87  * Omap1 specific IO mapping
  88  * ----------------------------------------------------------------------------
  89  */
  90
  91 #define OMAP1_IO_PHYS           0xFFFB0000
  92 #define OMAP1_IO_SIZE           0x40000
  93 #define OMAP1_IO_VIRT           (OMAP1_IO_PHYS - OMAP1_IO_OFFSET)
  94
  95 /*
  96  * ----------------------------------------------------------------------------
  97  * Omap2 specific IO mapping
  98  * ----------------------------------------------------------------------------
  99  */
 100
 101 /* We map both L3 and L4 on OMAP2 */
 102 #define L3_24XX_PHYS    L3_24XX_BASE    /* 0x68000000 --> 0xf8000000*/
 103 #define L3_24XX_VIRT    (L3_24XX_PHYS + OMAP2_L3_IO_OFFSET)
 104 #define L3_24XX_SIZE    SZ_1M           /* 44kB of 128MB used, want 1MB sect */
 105 #define L4_24XX_PHYS    L4_24XX_BASE    /* 0x48000000 --> 0xfa000000 */
 106 #define L4_24XX_VIRT    (L4_24XX_PHYS + OMAP2_L4_IO_OFFSET)
 107 #define L4_24XX_SIZE    SZ_1M           /* 1MB of 128MB used, want 1MB sect */
 108
 109 #define L4_WK_243X_PHYS         L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
 110 #define L4_WK_243X_VIRT         (L4_WK_243X_PHYS + OMAP2_L4_IO_OFFSET)
 111 #define L4_WK_243X_SIZE         SZ_1M
 112 #define OMAP243X_GPMC_PHYS      OMAP243X_GPMC_BASE
 113 #define OMAP243X_GPMC_VIRT      (OMAP243X_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
 114                                                 /* 0x6e000000 --> 0xfe000000 */
 115 #define OMAP243X_GPMC_SIZE      SZ_1M
 116 #define OMAP243X_SDRC_PHYS      OMAP243X_SDRC_BASE
 117                                                 /* 0x6D000000 --> 0xfd000000 */
 118 #define OMAP243X_SDRC_VIRT      (OMAP243X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
 119 #define OMAP243X_SDRC_SIZE      SZ_1M
 120 #define OMAP243X_SMS_PHYS       OMAP243X_SMS_BASE
 121                                                 /* 0x6c000000 --> 0xfc000000 */
 122 #define OMAP243X_SMS_VIRT       (OMAP243X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
 123 #define OMAP243X_SMS_SIZE       SZ_1M
 124
 125 /* DSP */
 126 #define DSP_MEM_24XX_PHYS       OMAP2420_DSP_MEM_BASE   /* 0x58000000 */
 127 #define DSP_MEM_24XX_VIRT       0xe0000000
 128 #define DSP_MEM_24XX_SIZE       0x28000
 129 #define DSP_IPI_24XX_PHYS       OMAP2420_DSP_IPI_BASE   /* 0x59000000 */
 130 #define DSP_IPI_24XX_VIRT       0xe1000000
 131 #define DSP_IPI_24XX_SIZE       SZ_4K
 132 #define DSP_MMU_24XX_PHYS       OMAP2420_DSP_MMU_BASE   /* 0x5a000000 */
 133 #define DSP_MMU_24XX_VIRT       0xe2000000
 134 #define DSP_MMU_24XX_SIZE       SZ_4K
 135
 136 /*
 137  * ----------------------------------------------------------------------------
 138  * Omap3 specific IO mapping
 139  * ----------------------------------------------------------------------------
 140  */
 141
 142 /* We map both L3 and L4 on OMAP3 */
 143 #define L3_34XX_PHYS            L3_34XX_BASE    /* 0x68000000 --> 0xf8000000 */
 144 #define L3_34XX_VIRT            (L3_34XX_PHYS + OMAP2_L3_IO_OFFSET)
 145 #define L3_34XX_SIZE            SZ_1M   /* 44kB of 128MB used, want 1MB sect */
 146
 147 #define L4_34XX_PHYS            L4_34XX_BASE    /* 0x48000000 --> 0xfa000000 */
 148 #define L4_34XX_VIRT            (L4_34XX_PHYS + OMAP2_L4_IO_OFFSET)
 149 #define L4_34XX_SIZE            SZ_4M   /* 1MB of 128MB used, want 1MB sect */
 150
 151 /*
 152  * Need to look at the Size 4M for L4.
 153  * VPOM3430 was not working for Int controller
 154  */
 155
 156 #define L4_WK_34XX_PHYS         L4_WK_34XX_BASE /* 0x48300000 --> 0xfa300000 */
 157 #define L4_WK_34XX_VIRT         (L4_WK_34XX_PHYS + OMAP2_L4_IO_OFFSET)
 158 #define L4_WK_34XX_SIZE         SZ_1M
 159
 160 #define L4_PER_34XX_PHYS        L4_PER_34XX_BASE
 161                                                 /* 0x49000000 --> 0xfb000000 */
 162 #define L4_PER_34XX_VIRT        (L4_PER_34XX_PHYS + OMAP2_L4_IO_OFFSET)
 163 #define L4_PER_34XX_SIZE        SZ_1M
 164
 165 #define L4_EMU_34XX_PHYS        L4_EMU_34XX_BASE
 166                                                 /* 0x54000000 --> 0xfe800000 */
 167 #define L4_EMU_34XX_VIRT        (L4_EMU_34XX_PHYS + OMAP2_EMU_IO_OFFSET)
 168 #define L4_EMU_34XX_SIZE        SZ_8M
 169
 170 #define OMAP34XX_GPMC_PHYS      OMAP34XX_GPMC_BASE
 171                                                 /* 0x6e000000 --> 0xfe000000 */
 172 #define OMAP34XX_GPMC_VIRT      (OMAP34XX_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
 173 #define OMAP34XX_GPMC_SIZE      SZ_1M
 174
 175 #define OMAP343X_SMS_PHYS       OMAP343X_SMS_BASE
 176                                                 /* 0x6c000000 --> 0xfc000000 */
 177 #define OMAP343X_SMS_VIRT       (OMAP343X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
 178 #define OMAP343X_SMS_SIZE       SZ_1M
 179
 180 #define OMAP343X_SDRC_PHYS      OMAP343X_SDRC_BASE
 181                                                 /* 0x6D000000 --> 0xfd000000 */
 182 #define OMAP343X_SDRC_VIRT      (OMAP343X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
 183 #define OMAP343X_SDRC_SIZE      SZ_1M
 184
 185 /* DSP */
 186 #define DSP_MEM_34XX_PHYS       OMAP34XX_DSP_MEM_BASE   /* 0x58000000 */
 187 #define DSP_MEM_34XX_VIRT       0xe0000000
 188 #define DSP_MEM_34XX_SIZE       0x28000
 189 #define DSP_IPI_34XX_PHYS       OMAP34XX_DSP_IPI_BASE   /* 0x59000000 */
 190 #define DSP_IPI_34XX_VIRT       0xe1000000
 191 #define DSP_IPI_34XX_SIZE       SZ_4K
 192 #define DSP_MMU_34XX_PHYS       OMAP34XX_DSP_MMU_BASE   /* 0x5a000000 */
 193 #define DSP_MMU_34XX_VIRT       0xe2000000
 194 #define DSP_MMU_34XX_SIZE       SZ_4K
 195
 196 /*
 197  * ----------------------------------------------------------------------------
 198  * Omap4 specific IO mapping
 199  * ----------------------------------------------------------------------------
 200  */
 201
 202 /* We map both L3 and L4 on OMAP4 */
 203 #define L3_44XX_PHYS            L3_44XX_BASE    /* 0x44000000 --> 0xf8000000 */
 204 #define L3_44XX_VIRT            (L3_44XX_PHYS + OMAP4_L3_IO_OFFSET)
 205 #define L3_44XX_SIZE            SZ_1M
 206
 207 #define L4_44XX_PHYS            L4_44XX_BASE    /* 0x4a000000 --> 0xfc000000 */
 208 #define L4_44XX_VIRT            (L4_44XX_PHYS + OMAP2_L4_IO_OFFSET)
 209 #define L4_44XX_SIZE            SZ_4M
 210
 211
 212 #define L4_WK_44XX_PHYS         L4_WK_44XX_BASE /* 0x4a300000 --> 0xfc300000 */
 213 #define L4_WK_44XX_VIRT         (L4_WK_44XX_PHYS + OMAP2_L4_IO_OFFSET)
 214 #define L4_WK_44XX_SIZE         SZ_1M
 215
 216 #define L4_PER_44XX_PHYS        L4_PER_44XX_BASE
 217                                                 /* 0x48000000 --> 0xfa000000 */
 218 #define L4_PER_44XX_VIRT        (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET)
 219 #define L4_PER_44XX_SIZE        SZ_4M
 220
 221 #define L4_ABE_44XX_PHYS        L4_ABE_44XX_BASE
 222                                                 /* 0x49000000 --> 0xfb000000 */
 223 #define L4_ABE_44XX_VIRT        (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET)
 224 #define L4_ABE_44XX_SIZE        SZ_1M
 225
 226 #define L4_EMU_44XX_PHYS        L4_EMU_44XX_BASE
 227                                                 /* 0x54000000 --> 0xfe800000 */
 228 #define L4_EMU_44XX_VIRT        (L4_EMU_44XX_PHYS + OMAP2_EMU_IO_OFFSET)
 229 #define L4_EMU_44XX_SIZE        SZ_8M
 230
 231 #define OMAP44XX_GPMC_PHYS      OMAP44XX_GPMC_BASE
 232                                                 /* 0x50000000 --> 0xf9000000 */
 233 #define OMAP44XX_GPMC_VIRT      (OMAP44XX_GPMC_PHYS + OMAP4_GPMC_IO_OFFSET)
 234 #define OMAP44XX_GPMC_SIZE      SZ_1M
 235
 236
 237 #define OMAP44XX_EMIF1_PHYS     OMAP44XX_EMIF1_BASE
 238                                                 /* 0x4c000000 --> 0xfd100000 */
 239 #define OMAP44XX_EMIF1_VIRT     (OMAP44XX_EMIF1_PHYS + OMAP4_L3_PER_IO_OFFSET)
 240 #define OMAP44XX_EMIF1_SIZE     SZ_1M
 241
 242 #define OMAP44XX_EMIF2_PHYS     OMAP44XX_EMIF2_BASE
 243                                                 /* 0x4d000000 --> 0xfd200000 */
 244 #define OMAP44XX_EMIF2_VIRT     (OMAP44XX_EMIF2_PHYS + OMAP4_L3_PER_IO_OFFSET)
 245 #define OMAP44XX_EMIF2_SIZE     SZ_1M
 246
 247 #define OMAP44XX_DMM_PHYS       OMAP44XX_DMM_BASE
 248                                                 /* 0x4e000000 --> 0xfd300000 */
 249 #define OMAP44XX_DMM_VIRT       (OMAP44XX_DMM_PHYS + OMAP4_L3_PER_IO_OFFSET)
 250 #define OMAP44XX_DMM_SIZE       SZ_1M
 251 /*
 252  * ----------------------------------------------------------------------------
 253  * Omap specific register access
 254  * ----------------------------------------------------------------------------
 255  */
 256
 257 #ifndef __ASSEMBLER__
 258
 259 /*
 260  * NOTE: Please use ioremap + __raw_read/write where possible instead of these
 261  */
 262
 263 extern u8 omap_readb(u32 pa);
 264 extern u16 omap_readw(u32 pa);
 265 extern u32 omap_readl(u32 pa);
 266 extern void omap_writeb(u8 v, u32 pa);
 267 extern void omap_writew(u16 v, u32 pa);
 268 extern void omap_writel(u32 v, u32 pa);
 269
 270 struct omap_sdrc_params;
 271 struct omap_opp;
 272
 273 extern void omap1_map_common_io(void);
 274 extern void omap1_init_common_hw(void);
 275
 276 extern void omap2_map_common_io(void);
 277 extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
 278                                  struct omap_sdrc_params *sdrc_cs1,
 279                                  struct omap_opp *mpu_opps,
 280                                  struct omap_opp *dsp_opps,
 281                                  struct omap_opp *l3_opps);
 282
 283 #define __arch_ioremap(p,s,t)   omap_ioremap(p,s,t)
 284 #define __arch_iounmap(v)       omap_iounmap(v)
 285
 286 void __iomem *omap_ioremap(unsigned long phys, size_t size, unsigned int type);
 287 void omap_iounmap(volatile void __iomem *addr);
 288
 289 #endif
 290
 291 #endif