arch/arm/plat-omap/include/plat/omap34xx.h

   1 /*
   2  * arch/arm/plat-omap/include/mach/omap34xx.h
   3  *
   4  * This file contains the processor specific definitions of the TI OMAP34XX.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  * Copyright (C) 2007 Nokia Corporation.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  22  */
  23
  24 #ifndef __ASM_ARCH_OMAP34XX_H
  25 #define __ASM_ARCH_OMAP34XX_H
  26
  27 /*
  28  * Please place only base defines here and put the rest in device
  29  * specific headers.
  30  */
  31
  32 #define L4_34XX_BASE            0x48000000
  33 #define L4_WK_34XX_BASE         0x48300000
  34 #define L4_PER_34XX_BASE        0x49000000
  35 #define L4_EMU_34XX_BASE        0x54000000
  36 #define L3_34XX_BASE            0x68000000
  37
  38 #define OMAP3430_32KSYNCT_BASE  0x48320000
  39 #define OMAP3430_CM_BASE        0x48004800
  40 #define OMAP3430_PRM_BASE       0x48306800
  41 #define OMAP343X_SMS_BASE       0x6C000000
  42 #define OMAP343X_SDRC_BASE      0x6D000000
  43 #define OMAP34XX_GPMC_BASE      0x6E000000
  44 #define OMAP343X_SCM_BASE       0x48002000
  45 #define OMAP343X_CTRL_BASE      OMAP343X_SCM_BASE
  46
  47 #define OMAP34XX_IC_BASE        0x48200000
  48
  49 #define OMAP3430_ISP_BASE               (L4_34XX_BASE + 0xBC000)
  50 #define OMAP3430_ISP_CBUFF_BASE         (OMAP3430_ISP_BASE + 0x0100)
  51 #define OMAP3430_ISP_CCP2_BASE          (OMAP3430_ISP_BASE + 0x0400)
  52 #define OMAP3430_ISP_CCDC_BASE          (OMAP3430_ISP_BASE + 0x0600)
  53 #define OMAP3430_ISP_HIST_BASE          (OMAP3430_ISP_BASE + 0x0A00)
  54 #define OMAP3430_ISP_H3A_BASE           (OMAP3430_ISP_BASE + 0x0C00)
  55 #define OMAP3430_ISP_PREV_BASE          (OMAP3430_ISP_BASE + 0x0E00)
  56 #define OMAP3430_ISP_RESZ_BASE          (OMAP3430_ISP_BASE + 0x1000)
  57 #define OMAP3430_ISP_SBL_BASE           (OMAP3430_ISP_BASE + 0x1200)
  58 #define OMAP3430_ISP_MMU_BASE           (OMAP3430_ISP_BASE + 0x1400)
  59 #define OMAP3430_ISP_CSI2A_BASE         (OMAP3430_ISP_BASE + 0x1800)
  60 #define OMAP3430_ISP_CSI2PHY_BASE       (OMAP3430_ISP_BASE + 0x1970)
  61
  62 #define OMAP3430_ISP_END                (OMAP3430_ISP_BASE         + 0x06F)
  63 #define OMAP3430_ISP_CBUFF_END          (OMAP3430_ISP_CBUFF_BASE   + 0x077)
  64 #define OMAP3430_ISP_CCP2_END           (OMAP3430_ISP_CCP2_BASE    + 0x1EF)
  65 #define OMAP3430_ISP_CCDC_END           (OMAP3430_ISP_CCDC_BASE    + 0x0A7)
  66 #define OMAP3430_ISP_HIST_END           (OMAP3430_ISP_HIST_BASE    + 0x047)
  67 #define OMAP3430_ISP_H3A_END            (OMAP3430_ISP_H3A_BASE     + 0x05F)
  68 #define OMAP3430_ISP_PREV_END           (OMAP3430_ISP_PREV_BASE    + 0x09F)
  69 #define OMAP3430_ISP_RESZ_END           (OMAP3430_ISP_RESZ_BASE    + 0x0AB)
  70 #define OMAP3430_ISP_SBL_END            (OMAP3430_ISP_SBL_BASE     + 0x0FB)
  71 #define OMAP3430_ISP_MMU_END            (OMAP3430_ISP_MMU_BASE     + 0x06F)
  72 #define OMAP3430_ISP_CSI2A_END          (OMAP3430_ISP_CSI2A_BASE   + 0x16F)
  73 #define OMAP3430_ISP_CSI2PHY_END        (OMAP3430_ISP_CSI2PHY_BASE + 0x007)
  74
  75 #define OMAP34XX_IVA_INTC_BASE  0x40000000
  76 #define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000)
  77 #define OMAP34XX_USBTLL_BASE    (L4_34XX_BASE + 0x62000)
  78 #define OMAP34XX_UHH_CONFIG_BASE        (L4_34XX_BASE + 0x64000)
  79 #define OMAP34XX_OHCI_BASE      (L4_34XX_BASE + 0x64400)
  80 #define OMAP34XX_EHCI_BASE      (L4_34XX_BASE + 0x64800)
  81 #define OMAP34XX_SR1_BASE       (L4_34XX_BASE + 0xC9000)
  82 #define OMAP34XX_SR2_BASE       (L4_34XX_BASE + 0xCB000)
  83
  84 #define OMAP34XX_MAILBOX_BASE   (L4_34XX_BASE + 0x94000)
  85
  86 #define OMAP34XX_DSP_BASE       0x58000000
  87 #define OMAP34XX_DSP_MEM_BASE   (OMAP34XX_DSP_BASE + 0x0)
  88 #define OMAP34XX_DSP_IPI_BASE   (OMAP34XX_DSP_BASE + 0x1000000)
  89 #define OMAP34XX_DSP_MMU_BASE   (OMAP34XX_DSP_BASE + 0x2000000)
  90
  91 /* VDD OPP identifiers */
  92 #define VDD1_OPP        0x1
  93 #define VDD2_OPP        0x2
  94
  95 /* VDD1 OPPS */
  96 #define VDD1_OPP1       0x1
  97 #define VDD1_OPP2       0x2
  98 #define VDD1_OPP3       0x3
  99 #define VDD1_OPP4       0x4
 100 #define VDD1_OPP5       0x5
 101 #define VDD1_OPP6       0x6
 102
 103 /* VDD2 OPPS */
 104 #define VDD2_OPP1       0x1
 105 #define VDD2_OPP2       0x2
 106 #define VDD2_OPP3       0x3
 107
 108 #define MIN_VDD1_OPP    VDD1_OPP1
 109 #define MAX_VDD1_OPP    VDD1_OPP6
 110 #define MIN_VDD2_OPP    VDD2_OPP1
 111 #define MAX_VDD2_OPP    VDD2_OPP3
 112
 113 #endif /* __ASM_ARCH_OMAP34XX_H */
 114