arch/blackfin/include/asm/cplbinit.h

   1 /*
   2  * Common CPLB definitions for CPLB init
   3  *
   4  * Copyright 2006-2008 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #ifndef __ASM_CPLBINIT_H__
  10 #define __ASM_CPLBINIT_H__
  11
  12 #include <asm/blackfin.h>
  13 #include <asm/cplb.h>
  14 #include <linux/threads.h>
  15
  16 #ifdef CONFIG_CPLB_SWITCH_TAB_L1
  17 # define PDT_ATTR __attribute__((l1_data))
  18 #else
  19 # define PDT_ATTR
  20 #endif
  21
  22 struct cplb_entry {
  23         unsigned long data, addr;
  24 };
  25
  26 struct cplb_boundary {
  27         unsigned long eaddr; /* End of this region.  */
  28         unsigned long data; /* CPLB data value.  */
  29 };
  30
  31 extern struct cplb_boundary dcplb_bounds[];
  32 extern struct cplb_boundary icplb_bounds[];
  33 extern int dcplb_nr_bounds, icplb_nr_bounds;
  34
  35 extern struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS];
  36 extern struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS];
  37 extern int first_switched_icplb;
  38 extern int first_switched_dcplb;
  39
  40 extern int nr_dcplb_miss[], nr_icplb_miss[], nr_icplb_supv_miss[];
  41 extern int nr_dcplb_prot[], nr_cplb_flush[];
  42
  43 #ifdef CONFIG_MPU
  44
  45 extern int first_mask_dcplb;
  46
  47 extern int page_mask_order;
  48 extern int page_mask_nelts;
  49
  50 extern unsigned long *current_rwx_mask[NR_CPUS];
  51
  52 extern void flush_switched_cplbs(unsigned int);
  53 extern void set_mask_dcplbs(unsigned long *, unsigned int);
  54
  55 extern void __noreturn panic_cplb_error(int seqstat, struct pt_regs *);
  56
  57 #endif /* CONFIG_MPU */
  58
  59 extern void bfin_icache_init(struct cplb_entry *icplb_tbl);
  60 extern void bfin_dcache_init(struct cplb_entry *icplb_tbl);
  61
  62 #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
  63 extern void generate_cplb_tables_all(void);
  64 extern void generate_cplb_tables_cpu(unsigned int cpu);
  65 #endif
  66 #endif