2 * Copyright 2004-2008 Analog Devices Inc.
4 * Licensed under the GPL-2 or later.
11 * GCC defines register number like this:
12 * -----------------------------
13 * 0 - 7 are data registers R0-R7
14 * 8 - 15 are address registers P0-P7
15 * 16 - 31 dsp registers I/B/L0 -- I/B/L3 & M0--M3
16 * 32 - 33 A registers A0 & A1
17 * 34 - status register
18 * -----------------------------
20 * We follows above, except:
21 * 32-33 --- Low 32-bit of A0&1
22 * 34-35 --- High 8-bit of A0&1
27 /* this struct defines the way the registers are stored on the
28 stack during a system call. */
37 long pc
; /* PC == RETI */
39 long reserved
; /* Used as scratch during system calls */
88 /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
89 #define PTRACE_GETREGS 12
90 #define PTRACE_SETREGS 13 /* ptrace signal */
92 #define PTRACE_GETFDPIC 31
93 #define PTRACE_GETFDPIC_EXEC 0
94 #define PTRACE_GETFDPIC_INTERP 1
100 /* user_mode returns true if only one bit is set in IPEND, other than the
101 master interrupt enable. */
102 #define user_mode(regs) (!(((regs)->ipend & ~0x10) & (((regs)->ipend & ~0x10) - 1)))
103 #define instruction_pointer(regs) ((regs)->pc)
104 #define profile_pc(regs) instruction_pointer(regs)
105 extern void show_regs(struct pt_regs
*);
107 #endif /* __KERNEL__ */
109 #endif /* __ASSEMBLY__ */
112 * Offsets used by 'ptrace' system call interface.
158 #define PT_RESERVED 32
167 #define PT_ORIG_R0 208
168 #define PT_ORIG_P0 212
169 #define PT_SYSCFG 216
170 #define PT_TEXT_ADDR 220
171 #define PT_TEXT_END_ADDR 224
172 #define PT_DATA_ADDR 228
173 #define PT_FDPIC_EXEC 232
174 #define PT_FDPIC_INTERP 236
176 #endif /* _BFIN_PTRACE_H */