| blob | 26b76083e14c084fb2cd48622573ffeb70566b29 |
1 /*
2 * File: include/asm-blackfin/mach-bf538/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 *
5 * Copyright (C) 2004-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
7 */
9 /* This file should be up to date with:
10 * - Revision G, 09/18/2008; ADSP-BF538/BF538F Blackfin Processor Anomaly List
11 * - Revision L, 09/18/2008; ADSP-BF539/BF539F Blackfin Processor Anomaly List
12 */
14 #ifndef _MACH_ANOMALY_H_
15 #define _MACH_ANOMALY_H_
17 /* We do not support old silicon - sorry */
18 #if __SILICON_REVISION__ < 4
19 # error will not work on BF538/BF539 silicon version 0.0, 0.1, 0.2, or 0.3
20 #endif
22 #if defined(__ADSPBF538__)
23 # define ANOMALY_BF538 1
24 #else
25 # define ANOMALY_BF538 0
26 #endif
27 #if defined(__ADSPBF539__)
28 # define ANOMALY_BF539 1
29 #else
30 # define ANOMALY_BF539 0
31 #endif
33 /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
34 #define ANOMALY_05000074 (1)
35 /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
36 #define ANOMALY_05000119 (1)
37 /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
38 #define ANOMALY_05000122 (1)
39 /* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
40 #define ANOMALY_05000166 (1)
41 /* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
42 #define ANOMALY_05000179 (1)
43 /* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
44 #define ANOMALY_05000180 (1)
45 /* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
46 #define ANOMALY_05000193 (1)
47 /* Current DMA Address Shows Wrong Value During Carry Fix */
48 #define ANOMALY_05000199 (__SILICON_REVISION__ < 4)
49 /* NMI Event at Boot Time Results in Unpredictable State */
50 #define ANOMALY_05000219 (1)
51 /* SPI Slave Boot Mode Modifies Registers from Reset Value */
52 #define ANOMALY_05000229 (1)
53 /* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
54 #define ANOMALY_05000233 (1)
55 /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
56 #define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
57 /* False Hardware Error from an Access in the Shadow of a Conditional Branch */
58 #define ANOMALY_05000245 (1)
59 /* Maximum External Clock Speed for Timers */
60 #define ANOMALY_05000253 (1)
61 /* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
62 #define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
63 /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
64 #define ANOMALY_05000270 (__SILICON_REVISION__ < 4)
65 /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
66 #define ANOMALY_05000272 (1)
67 /* Writes to Synchronous SDRAM Memory May Be Lost */
68 #define ANOMALY_05000273 (__SILICON_REVISION__ < 4)
69 /* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
70 #define ANOMALY_05000277 (__SILICON_REVISION__ < 4)
71 /* Disabling Peripherals with DMA Running May Cause DMA System Instability */
72 #define ANOMALY_05000278 (__SILICON_REVISION__ < 4)
73 /* False Hardware Error Exception when ISR Context Is Not Restored */
74 #define ANOMALY_05000281 (__SILICON_REVISION__ < 4)
75 /* Memory DMA Corruption with 32-Bit Data and Traffic Control */
76 #define ANOMALY_05000282 (__SILICON_REVISION__ < 4)
77 /* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
78 #define ANOMALY_05000283 (__SILICON_REVISION__ < 4)
79 /* SPORTs May Receive Bad Data If FIFOs Fill Up */
80 #define ANOMALY_05000288 (__SILICON_REVISION__ < 4)
81 /* Reads from CAN Mailbox and Acceptance Mask Area Can Fail */
82 #define ANOMALY_05000291 (__SILICON_REVISION__ < 4)
83 /* Hibernate Leakage Current Is Higher Than Specified */
84 #define ANOMALY_05000293 (__SILICON_REVISION__ < 4)
85 /* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
86 #define ANOMALY_05000294 (1)
87 /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
88 #define ANOMALY_05000301 (__SILICON_REVISION__ < 4)
89 /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
90 #define ANOMALY_05000304 (__SILICON_REVISION__ < 4)
91 /* SCKELOW Bit Does Not Maintain State Through Hibernate */
92 #define ANOMALY_05000307 (__SILICON_REVISION__ < 4)
93 /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
94 #define ANOMALY_05000310 (1)
95 /* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
96 #define ANOMALY_05000312 (__SILICON_REVISION__ < 5)
97 /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
98 #define ANOMALY_05000313 (__SILICON_REVISION__ < 4)
99 /* Killed System MMR Write Completes Erroneously on Next System MMR Access */
100 #define ANOMALY_05000315 (__SILICON_REVISION__ < 4)
101 /* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */
102 #define ANOMALY_05000318 (ANOMALY_BF539 && __SILICON_REVISION__ < 4)
103 /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
104 #define ANOMALY_05000355 (__SILICON_REVISION__ < 5)
105 /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
106 #define ANOMALY_05000357 (__SILICON_REVISION__ < 5)
107 /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
108 #define ANOMALY_05000366 (1)
109 /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
110 #define ANOMALY_05000371 (__SILICON_REVISION__ < 5)
111 /* Entering Hibernate State with Peripheral Wakeups Enabled Draws Excess Current */
112 #define ANOMALY_05000374 (__SILICON_REVISION__ == 4)
113 /* GPIO Pins PC1 and PC4 Can Function as Normal Outputs */
114 #define ANOMALY_05000375 (__SILICON_REVISION__ < 4)
115 /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
116 #define ANOMALY_05000402 (__SILICON_REVISION__ == 3)
117 /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
118 #define ANOMALY_05000403 (1)
119 /* Speculative Fetches Can Cause Undesired External FIFO Operations */
120 #define ANOMALY_05000416 (1)
121 /* Multichannel SPORT Channel Misalignment Under Specific Configuration */
122 #define ANOMALY_05000425 (1)
123 /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
124 #define ANOMALY_05000426 (1)
125 /* Specific GPIO Pins May Change State when Entering Hibernate */
126 #define ANOMALY_05000436 (__SILICON_REVISION__ > 3)
127 /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
128 #define ANOMALY_05000443 (1)
129 /* False Hardware Error when RETI Points to Invalid Memory */
130 #define ANOMALY_05000461 (1)
132 /* Anomalies that don't exist on this proc */
133 #define ANOMALY_05000099 (0)
134 #define ANOMALY_05000120 (0)
135 #define ANOMALY_05000125 (0)
136 #define ANOMALY_05000149 (0)
137 #define ANOMALY_05000158 (0)
138 #define ANOMALY_05000171 (0)
139 #define ANOMALY_05000182 (0)
140 #define ANOMALY_05000189 (0)
141 #define ANOMALY_05000198 (0)
142 #define ANOMALY_05000202 (0)
143 #define ANOMALY_05000215 (0)
144 #define ANOMALY_05000220 (0)
145 #define ANOMALY_05000227 (0)
146 #define ANOMALY_05000230 (0)
147 #define ANOMALY_05000231 (0)
148 #define ANOMALY_05000234 (0)
149 #define ANOMALY_05000242 (0)
150 #define ANOMALY_05000248 (0)
151 #define ANOMALY_05000250 (0)
152 #define ANOMALY_05000254 (0)
153 #define ANOMALY_05000257 (0)
154 #define ANOMALY_05000263 (0)
155 #define ANOMALY_05000266 (0)
156 #define ANOMALY_05000274 (0)
157 #define ANOMALY_05000287 (0)
158 #define ANOMALY_05000305 (0)
159 #define ANOMALY_05000311 (0)
160 #define ANOMALY_05000323 (0)
161 #define ANOMALY_05000353 (1)
162 #define ANOMALY_05000362 (1)
163 #define ANOMALY_05000363 (0)
164 #define ANOMALY_05000364 (0)
165 #define ANOMALY_05000380 (0)
166 #define ANOMALY_05000386 (1)
167 #define ANOMALY_05000389 (0)
168 #define ANOMALY_05000400 (0)
169 #define ANOMALY_05000412 (0)
170 #define ANOMALY_05000430 (0)
171 #define ANOMALY_05000432 (0)
172 #define ANOMALY_05000435 (0)
173 #define ANOMALY_05000447 (0)
174 #define ANOMALY_05000448 (0)
175 #define ANOMALY_05000456 (0)
176 #define ANOMALY_05000450 (0)
177 #define ANOMALY_05000465 (0)
178 #define ANOMALY_05000467 (0)
180 #endif