arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h

   1 /*
   2  * Copyright 2007-2009 Analog Devices Inc.
   3  *
   4  * Licensed under the GPL-2 or later.
   5  */
   6
   7 #include <linux/serial.h>
   8 #include <asm/dma.h>
   9 #include <asm/portmux.h>
  10
  11 #define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
  12 #define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
  13 #define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
  14 #define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER_SET))
  15 #define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
  16 #define UART_GET_LSR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LSR))
  17 #define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
  18 #define UART_GET_MSR(uart)      bfin_read16(((uart)->port.membase + OFFSET_MSR))
  19 #define UART_GET_MCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_MCR))
  20
  21 #define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
  22 #define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
  23 #define UART_SET_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER_SET),v)
  24 #define UART_CLEAR_IER(uart,v)  bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v)
  25 #define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
  26 #define UART_PUT_LSR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LSR),v)
  27 #define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
  28 #define UART_CLEAR_LSR(uart)    bfin_write16(((uart)->port.membase + OFFSET_LSR), -1)
  29 #define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
  30 #define UART_PUT_MCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_MCR),v)
  31 #define UART_CLEAR_SCTS(uart)   bfin_write16(((uart)->port.membase + OFFSET_MSR),SCTS)
  32
  33 #define UART_SET_DLAB(uart)     /* MMRs not muxed on BF54x */
  34 #define UART_CLEAR_DLAB(uart)   /* MMRs not muxed on BF54x */
  35
  36 #define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
  37 #define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS|MRTS))
  38 #define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
  39 #define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
  40 #define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
  41
  42 #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) || \
  43         defined(CONFIG_BFIN_UART2_CTSRTS) || defined(CONFIG_BFIN_UART3_CTSRTS)
  44 # define CONFIG_SERIAL_BFIN_HARD_CTSRTS
  45 #endif
  46
  47 #define BFIN_UART_TX_FIFO_SIZE  2
  48
  49 /*
  50  * The pin configuration is different from schematic
  51  */
  52 struct bfin_serial_port {
  53         struct uart_port        port;
  54         unsigned int            old_status;
  55         int                     status_irq;
  56 #ifdef CONFIG_SERIAL_BFIN_DMA
  57         int                     tx_done;
  58         int                     tx_count;
  59         struct circ_buf         rx_dma_buf;
  60         struct timer_list       rx_dma_timer;
  61         int                     rx_dma_nrows;
  62         unsigned int            tx_dma_channel;
  63         unsigned int            rx_dma_channel;
  64         struct work_struct      tx_dma_workqueue;
  65 #endif
  66 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
  67         int                     scts;
  68         int                     cts_pin;
  69         int                     rts_pin;
  70 #endif
  71 };
  72
  73 struct bfin_serial_res {
  74         unsigned long   uart_base_addr;
  75         int             uart_irq;
  76         int             uart_status_irq;
  77 #ifdef CONFIG_SERIAL_BFIN_DMA
  78         unsigned int    uart_tx_dma_channel;
  79         unsigned int    uart_rx_dma_channel;
  80 #endif
  81 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
  82         int             uart_cts_pin;
  83         int             uart_rts_pin;
  84 #endif
  85 };
  86
  87 struct bfin_serial_res bfin_serial_resource[] = {
  88 #ifdef CONFIG_SERIAL_BFIN_UART0
  89         {
  90         0xFFC00400,
  91         IRQ_UART0_RX,
  92         IRQ_UART0_ERROR,
  93 #ifdef CONFIG_SERIAL_BFIN_DMA
  94         CH_UART0_TX,
  95         CH_UART0_RX,
  96 #endif
  97 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
  98         0,
  99         0,
 100 #endif
 101         },
 102 #endif
 103 #ifdef CONFIG_SERIAL_BFIN_UART1
 104         {
 105         0xFFC02000,
 106         IRQ_UART1_RX,
 107         IRQ_UART1_ERROR,
 108 #ifdef CONFIG_SERIAL_BFIN_DMA
 109         CH_UART1_TX,
 110         CH_UART1_RX,
 111 #endif
 112 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
 113         GPIO_PE10,
 114         GPIO_PE9,
 115 #endif
 116         },
 117 #endif
 118 #ifdef CONFIG_SERIAL_BFIN_UART2
 119         {
 120         0xFFC02100,
 121         IRQ_UART2_RX,
 122         IRQ_UART2_ERROR,
 123 #ifdef CONFIG_SERIAL_BFIN_DMA
 124         CH_UART2_TX,
 125         CH_UART2_RX,
 126 #endif
 127 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
 128         0,
 129         0,
 130 #endif
 131         },
 132 #endif
 133 #ifdef CONFIG_SERIAL_BFIN_UART3
 134         {
 135         0xFFC03100,
 136         IRQ_UART3_RX,
 137         IRQ_UART3_ERROR,
 138 #ifdef CONFIG_SERIAL_BFIN_DMA
 139         CH_UART3_TX,
 140         CH_UART3_RX,
 141 #endif
 142 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
 143         GPIO_PB3,
 144         GPIO_PB2,
 145 #endif
 146         },
 147 #endif
 148 };
 149
 150 #define DRIVER_NAME "bfin-uart"