arch/blackfin/mach-bf548/include/mach/blackfin.h

   1 /*
   2  * Copyright 2007-2009 Analog Devices Inc.
   3  *
   4  * Licensed under the GPL-2 or later.
   5  */
   6
   7 #ifndef _MACH_BLACKFIN_H_
   8 #define _MACH_BLACKFIN_H_
   9
  10 #include "bf548.h"
  11 #include "anomaly.h"
  12
  13 #ifdef CONFIG_BF542
  14 #include "defBF542.h"
  15 #endif
  16
  17 #ifdef CONFIG_BF544
  18 #include "defBF544.h"
  19 #endif
  20
  21 #ifdef CONFIG_BF547
  22 #include "defBF547.h"
  23 #endif
  24
  25 #ifdef CONFIG_BF548
  26 #include "defBF548.h"
  27 #endif
  28
  29 #ifdef CONFIG_BF549
  30 #include "defBF549.h"
  31 #endif
  32
  33 #if !defined(__ASSEMBLY__)
  34 #ifdef CONFIG_BF542
  35 #include "cdefBF542.h"
  36 #endif
  37 #ifdef CONFIG_BF544
  38 #include "cdefBF544.h"
  39 #endif
  40 #ifdef CONFIG_BF547
  41 #include "cdefBF547.h"
  42 #endif
  43 #ifdef CONFIG_BF548
  44 #include "cdefBF548.h"
  45 #endif
  46 #ifdef CONFIG_BF549
  47 #include "cdefBF549.h"
  48 #endif
  49
  50 #endif
  51
  52 #define BFIN_UART_NR_PORTS      4
  53
  54 #define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
  55 #define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
  56 #define OFFSET_GCTL             0x08    /* Global Control Register              */
  57 #define OFFSET_LCR              0x0C    /* Line Control Register                */
  58 #define OFFSET_MCR              0x10    /* Modem Control Register               */
  59 #define OFFSET_LSR              0x14    /* Line Status Register                 */
  60 #define OFFSET_MSR              0x18    /* Modem Status Register                */
  61 #define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
  62 #define OFFSET_IER_SET          0x20    /* Set Interrupt Enable Register        */
  63 #define OFFSET_IER_CLEAR        0x24    /* Clear Interrupt Enable Register      */
  64 #define OFFSET_THR              0x28    /* Transmit Holding register            */
  65 #define OFFSET_RBR              0x2C    /* Receive Buffer register              */
  66
  67 /* PLL_DIV Masks */
  68 #define CCLK_DIV1 CSEL_DIV1     /* CCLK = VCO / 1 */
  69 #define CCLK_DIV2 CSEL_DIV2     /* CCLK = VCO / 2 */
  70 #define CCLK_DIV4 CSEL_DIV4     /* CCLK = VCO / 4 */
  71 #define CCLK_DIV8 CSEL_DIV8     /* CCLK = VCO / 8 */
  72
  73 #endif