arch/mips/include/asm/rtlx.h

   1 /*
   2  * Copyright (C) 2004, 2005 MIPS Technologies, Inc.  All rights reserved.
   3  *
   4  */
   5
   6 #ifndef __ASM_RTLX_H_
   7 #define __ASM_RTLX_H_
   8
   9 #include <irq.h>
  10
  11 #define LX_NODE_BASE 10
  12
  13 #define MIPS_CPU_RTLX_IRQ 0
  14
  15 #define RTLX_VERSION 2
  16 #define RTLX_xID 0x12345600
  17 #define RTLX_ID (RTLX_xID | RTLX_VERSION)
  18 #define RTLX_CHANNELS 8
  19
  20 #define RTLX_CHANNEL_STDIO      0
  21 #define RTLX_CHANNEL_DBG        1
  22 #define RTLX_CHANNEL_SYSIO      2
  23
  24 extern int rtlx_open(int index, int can_sleep);
  25 extern int rtlx_release(int index);
  26 extern ssize_t rtlx_read(int index, void __user *buff, size_t count);
  27 extern ssize_t rtlx_write(int index, const void __user *buffer, size_t count);
  28 extern unsigned int rtlx_read_poll(int index, int can_sleep);
  29 extern unsigned int rtlx_write_poll(int index);
  30
  31 enum rtlx_state {
  32         RTLX_STATE_UNUSED = 0,
  33         RTLX_STATE_INITIALISED,
  34         RTLX_STATE_REMOTE_READY,
  35         RTLX_STATE_OPENED
  36 };
  37
  38 #define RTLX_BUFFER_SIZE 2048
  39
  40 /* each channel supports read and write.
  41    linux (vpe0) reads lx_buffer  and writes rt_buffer
  42    SP (vpe1) reads rt_buffer and writes lx_buffer
  43 */
  44 struct rtlx_channel {
  45         enum rtlx_state rt_state;
  46         enum rtlx_state lx_state;
  47
  48         int buffer_size;
  49
  50         /* read and write indexes per buffer */
  51         int rt_write, rt_read;
  52         char *rt_buffer;
  53
  54         int lx_write, lx_read;
  55         char *lx_buffer;
  56 };
  57
  58 struct rtlx_info {
  59         unsigned long id;
  60         enum rtlx_state state;
  61
  62         struct rtlx_channel channel[RTLX_CHANNELS];
  63 };
  64
  65 #endif /* __ASM_RTLX_H_ */