arch/mips/include/asm/sgi/hpc3.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License. See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * hpc3.h: Definitions for SGI HPC3 controller
   7  *
   8  * Copyright (C) 1996 David S. Miller
   9  * Copyright (C) 1998 Ralf Baechle
  10  */
  11
  12 #ifndef _SGI_HPC3_H
  13 #define _SGI_HPC3_H
  14
  15 #include <linux/types.h>
  16 #include <asm/page.h>
  17
  18 /* An HPC DMA descriptor. */
  19 struct hpc_dma_desc {
  20         u32 pbuf;       /* physical address of data buffer */
  21         u32 cntinfo;    /* counter and info bits */
  22 #define HPCDMA_EOX      0x80000000 /* last desc in chain for tx */
  23 #define HPCDMA_EOR      0x80000000 /* last desc in chain for rx */
  24 #define HPCDMA_EOXP     0x40000000 /* end of packet for tx */
  25 #define HPCDMA_EORP     0x40000000 /* end of packet for rx */
  26 #define HPCDMA_XIE      0x20000000 /* irq generated when at end of this desc */
  27 #define HPCDMA_XIU      0x01000000 /* Tx buffer in use by CPU. */
  28 #define HPCDMA_EIPC     0x00ff0000 /* SEEQ ethernet special xternal bytecount */
  29 #define HPCDMA_ETXD     0x00008000 /* set to one by HPC when packet tx'd */
  30 #define HPCDMA_OWN      0x00004000 /* Denotes ring buffer ownership on rx */
  31 #define HPCDMA_BCNT     0x00003fff /* size in bytes of this dma buffer */
  32
  33         u32 pnext;      /* paddr of next hpc_dma_desc if any */
  34 };
  35
  36 /* The set of regs for each HPC3 PBUS DMA channel. */
  37 struct hpc3_pbus_dmacregs {
  38         volatile u32 pbdma_bptr;        /* pbus dma channel buffer ptr */
  39         volatile u32 pbdma_dptr;        /* pbus dma channel desc ptr */
  40         u32 _unused0[0x1000/4 - 2];     /* padding */
  41         volatile u32 pbdma_ctrl;        /* pbus dma channel control register has
  42                                          * copletely different meaning for read
  43                                          * compared with write */
  44         /* read */
  45 #define HPC3_PDMACTRL_INT       0x00000001 /* interrupt (cleared after read) */
  46 #define HPC3_PDMACTRL_ISACT     0x00000002 /* channel active */
  47         /* write */
  48 #define HPC3_PDMACTRL_SEL       0x00000002 /* little endian transfer */
  49 #define HPC3_PDMACTRL_RCV       0x00000004 /* direction is receive */
  50 #define HPC3_PDMACTRL_FLSH      0x00000008 /* enable flush for receive DMA */
  51 #define HPC3_PDMACTRL_ACT       0x00000010 /* start dma transfer */
  52 #define HPC3_PDMACTRL_LD        0x00000020 /* load enable for ACT */
  53 #define HPC3_PDMACTRL_RT        0x00000040 /* Use realtime GIO bus servicing */
  54 #define HPC3_PDMACTRL_HW        0x0000ff00 /* DMA High-water mark */
  55 #define HPC3_PDMACTRL_FB        0x003f0000 /* Ptr to beginning of fifo */
  56 #define HPC3_PDMACTRL_FE        0x3f000000 /* Ptr to end of fifo */
  57
  58         u32 _unused1[0x1000/4 - 1];     /* padding */
  59 };
  60
  61 /* The HPC3 SCSI registers, this does not include external ones. */
  62 struct hpc3_scsiregs {
  63         volatile u32 cbptr;     /* current dma buffer ptr, diagnostic use only */
  64         volatile u32 ndptr;     /* next dma descriptor ptr */
  65         u32 _unused0[0x1000/4 - 2];     /* padding */
  66         volatile u32 bcd;       /* byte count info */
  67 #define HPC3_SBCD_BCNTMSK 0x00003fff /* bytes to transfer from/to memory */
  68 #define HPC3_SBCD_XIE     0x00004000 /* Send IRQ when done with cur buf */
  69 #define HPC3_SBCD_EOX     0x00008000 /* Indicates this is last buf in chain */
  70
  71         volatile u32 ctrl;    /* control register */
  72 #define HPC3_SCTRL_IRQ    0x01 /* IRQ asserted, either dma done or parity */
  73 #define HPC3_SCTRL_ENDIAN 0x02 /* DMA endian mode, 0=big 1=little */
  74 #define HPC3_SCTRL_DIR    0x04 /* DMA direction, 1=dev2mem 0=mem2dev */
  75 #define HPC3_SCTRL_FLUSH  0x08 /* Tells HPC3 to flush scsi fifos */
  76 #define HPC3_SCTRL_ACTIVE 0x10 /* SCSI DMA channel is active */
  77 #define HPC3_SCTRL_AMASK  0x20 /* DMA active inhibits PIO */
  78 #define HPC3_SCTRL_CRESET 0x40 /* Resets dma channel and external controller */
  79 #define HPC3_SCTRL_PERR   0x80 /* Bad parity on HPC3 iface to scsi controller */
  80
  81         volatile u32 gfptr;     /* current GIO fifo ptr */
  82         volatile u32 dfptr;     /* current device fifo ptr */
  83         volatile u32 dconfig;   /* DMA configuration register */
  84 #define HPC3_SDCFG_HCLK 0x00001 /* Enable DMA half clock mode */
  85 #define HPC3_SDCFG_D1   0x00006 /* Cycles to spend in D1 state */
  86 #define HPC3_SDCFG_D2   0x00038 /* Cycles to spend in D2 state */
  87 #define HPC3_SDCFG_D3   0x001c0 /* Cycles to spend in D3 state */
  88 #define HPC3_SDCFG_HWAT 0x00e00 /* DMA high water mark */
  89 #define HPC3_SDCFG_HW   0x01000 /* Enable 16-bit halfword DMA accesses to scsi */
  90 #define HPC3_SDCFG_SWAP 0x02000 /* Byte swap all DMA accesses */
  91 #define HPC3_SDCFG_EPAR 0x04000 /* Enable parity checking for DMA */
  92 #define HPC3_SDCFG_POLL 0x08000 /* hd_dreq polarity control */
  93 #define HPC3_SDCFG_ERLY 0x30000 /* hd_dreq behavior control bits */
  94
  95         volatile u32 pconfig;   /* PIO configuration register */
  96 #define HPC3_SPCFG_P3   0x0003 /* Cycles to spend in P3 state */
  97 #define HPC3_SPCFG_P2W  0x001c /* Cycles to spend in P2 state for writes */
  98 #define HPC3_SPCFG_P2R  0x01e0 /* Cycles to spend in P2 state for reads */
  99 #define HPC3_SPCFG_P1   0x0e00 /* Cycles to spend in P1 state */
 100 #define HPC3_SPCFG_HW   0x1000 /* Enable 16-bit halfword PIO accesses to scsi */
 101 #define HPC3_SPCFG_SWAP 0x2000 /* Byte swap all PIO accesses */
 102 #define HPC3_SPCFG_EPAR 0x4000 /* Enable parity checking for PIO */
 103 #define HPC3_SPCFG_FUJI 0x8000 /* Fujitsu scsi controller mode for faster dma/pio */
 104
 105         u32 _unused1[0x1000/4 - 6];     /* padding */
 106 };
 107
 108 /* SEEQ ethernet HPC3 registers, only one seeq per HPC3. */
 109 struct hpc3_ethregs {
 110         /* Receiver registers. */
 111         volatile u32 rx_cbptr;   /* current dma buffer ptr, diagnostic use only */
 112         volatile u32 rx_ndptr;   /* next dma descriptor ptr */
 113         u32 _unused0[0x1000/4 - 2];     /* padding */
 114         volatile u32 rx_bcd;    /* byte count info */
 115 #define HPC3_ERXBCD_BCNTMSK 0x00003fff /* bytes to be sent to memory */
 116 #define HPC3_ERXBCD_XIE     0x20000000 /* HPC3 interrupts cpu at end of this buf */
 117 #define HPC3_ERXBCD_EOX     0x80000000 /* flags this as end of descriptor chain */
 118
 119         volatile u32 rx_ctrl;   /* control register */
 120 #define HPC3_ERXCTRL_STAT50 0x0000003f /* Receive status reg bits of Seeq8003 */
 121 #define HPC3_ERXCTRL_STAT6  0x00000040 /* Rdonly irq status */
 122 #define HPC3_ERXCTRL_STAT7  0x00000080 /* Rdonlt old/new status bit from Seeq */
 123 #define HPC3_ERXCTRL_ENDIAN 0x00000100 /* Endian for dma channel, little=1 big=0 */
 124 #define HPC3_ERXCTRL_ACTIVE 0x00000200 /* Tells if DMA transfer is in progress */
 125 #define HPC3_ERXCTRL_AMASK  0x00000400 /* Tells if ACTIVE inhibits PIO's to hpc3 */
 126 #define HPC3_ERXCTRL_RBO    0x00000800 /* Receive buffer overflow if set to 1 */
 127
 128         volatile u32 rx_gfptr;  /* current GIO fifo ptr */
 129         volatile u32 rx_dfptr;  /* current device fifo ptr */
 130         u32 _unused1;           /* padding */
 131         volatile u32 reset;     /* reset register */
 132 #define HPC3_ERST_CRESET 0x1    /* Reset dma channel and external controller */
 133 #define HPC3_ERST_CLRIRQ 0x2    /* Clear channel interrupt */
 134 #define HPC3_ERST_LBACK  0x4    /* Enable diagnostic loopback mode of Seeq8003 */
 135
 136         volatile u32 dconfig;    /* DMA configuration register */
 137 #define HPC3_EDCFG_D1    0x0000f /* Cycles to spend in D1 state for PIO */
 138 #define HPC3_EDCFG_D2    0x000f0 /* Cycles to spend in D2 state for PIO */
 139 #define HPC3_EDCFG_D3    0x00f00 /* Cycles to spend in D3 state for PIO */
 140 #define HPC3_EDCFG_WCTRL 0x01000 /* Enable writes of desc into ex ctrl port */
 141 #define HPC3_EDCFG_FRXDC 0x02000 /* Clear eop stat bits upon rxdc, hw seeq fix */
 142 #define HPC3_EDCFG_FEOP  0x04000 /* Bad packet marker timeout enable */
 143 #define HPC3_EDCFG_FIRQ  0x08000 /* Another bad packet timeout enable */
 144 #define HPC3_EDCFG_PTO   0x30000 /* Programmed timeout value for above two */
 145
 146         volatile u32 pconfig;   /* PIO configuration register */
 147 #define HPC3_EPCFG_P1    0x000f /* Cycles to spend in P1 state for PIO */
 148 #define HPC3_EPCFG_P2    0x00f0 /* Cycles to spend in P2 state for PIO */
 149 #define HPC3_EPCFG_P3    0x0f00 /* Cycles to spend in P3 state for PIO */
 150 #define HPC3_EPCFG_TST   0x1000 /* Diagnistic ram test feature bit */
 151
 152         u32 _unused2[0x1000/4 - 8];     /* padding */
 153
 154         /* Transmitter registers. */
 155         volatile u32 tx_cbptr;  /* current dma buffer ptr, diagnostic use only */
 156         volatile u32 tx_ndptr;  /* next dma descriptor ptr */
 157         u32 _unused3[0x1000/4 - 2];     /* padding */
 158         volatile u32 tx_bcd;            /* byte count info */
 159 #define HPC3_ETXBCD_BCNTMSK 0x00003fff  /* bytes to be read from memory */
 160 #define HPC3_ETXBCD_ESAMP   0x10000000  /* if set, too late to add descriptor */
 161 #define HPC3_ETXBCD_XIE     0x20000000  /* Interrupt cpu at end of cur desc */
 162 #define HPC3_ETXBCD_EOP     0x40000000  /* Last byte of cur buf is end of packet */
 163 #define HPC3_ETXBCD_EOX     0x80000000  /* This buf is the end of desc chain */
 164
 165         volatile u32 tx_ctrl;           /* control register */
 166 #define HPC3_ETXCTRL_STAT30 0x0000000f  /* Rdonly copy of seeq tx stat reg */
 167 #define HPC3_ETXCTRL_STAT4  0x00000010  /* Indicate late collision occurred */
 168 #define HPC3_ETXCTRL_STAT75 0x000000e0  /* Rdonly irq status from seeq */
 169 #define HPC3_ETXCTRL_ENDIAN 0x00000100  /* DMA channel endian mode, 1=little 0=big */
 170 #define HPC3_ETXCTRL_ACTIVE 0x00000200  /* DMA tx channel is active */
 171 #define HPC3_ETXCTRL_AMASK  0x00000400  /* Indicates ACTIVE inhibits PIO's */
 172
 173         volatile u32 tx_gfptr;          /* current GIO fifo ptr */
 174         volatile u32 tx_dfptr;          /* current device fifo ptr */
 175         u32 _unused4[0x1000/4 - 4];     /* padding */
 176 };
 177
 178 struct hpc3_regs {
 179         /* First regs for the PBUS 8 dma channels. */
 180         struct hpc3_pbus_dmacregs pbdma[8];
 181
 182         /* Now the HPC scsi registers, we get two scsi reg sets. */
 183         struct hpc3_scsiregs scsi_chan0, scsi_chan1;
 184
 185         /* The SEEQ hpc3 ethernet dma/control registers. */
 186         struct hpc3_ethregs ethregs;
 187
 188         /* Here are where the hpc3 fifo's can be directly accessed
 189          * via PIO accesses.  Under normal operation we never stick
 190          * our grubby paws in here so it's just padding. */
 191         u32 _unused0[0x18000/4];
 192
 193         /* HPC3 irq status regs.  Due to a peculiar bug you need to
 194          * look at two different register addresses to get at all of
 195          * the status bits.  The first reg can only reliably report
 196          * bits 4:0 of the status, and the second reg can only
 197          * reliably report bits 9:5 of the hpc3 irq status.  I told
 198          * you it was a peculiar bug. ;-)
 199          */
 200         volatile u32 istat0;            /* Irq status, only bits <4:0> reliable. */
 201 #define HPC3_ISTAT_PBIMASK      0x0ff   /* irq bits for pbus devs 0 --> 7 */
 202 #define HPC3_ISTAT_SC0MASK      0x100   /* irq bit for scsi channel 0 */
 203 #define HPC3_ISTAT_SC1MASK      0x200   /* irq bit for scsi channel 1 */
 204
 205         volatile u32 gio_misc;          /* GIO misc control bits. */
 206 #define HPC3_GIOMISC_ERTIME     0x1     /* Enable external timer real time. */
 207 #define HPC3_GIOMISC_DENDIAN    0x2     /* dma descriptor endian, 1=lit 0=big */
 208
 209         u32 eeprom;                     /* EEPROM data reg. */
 210 #define HPC3_EEPROM_EPROT       0x01    /* Protect register enable */
 211 #define HPC3_EEPROM_CSEL        0x02    /* Chip select */
 212 #define HPC3_EEPROM_ECLK        0x04    /* EEPROM clock */
 213 #define HPC3_EEPROM_DATO        0x08    /* Data out */
 214 #define HPC3_EEPROM_DATI        0x10    /* Data in */
 215
 216         volatile u32 istat1;            /* Irq status, only bits <9:5> reliable. */
 217         volatile u32 bestat;            /* Bus error interrupt status reg. */
 218 #define HPC3_BESTAT_BLMASK      0x000ff /* Bus lane where bad parity occurred */
 219 #define HPC3_BESTAT_CTYPE       0x00100 /* Bus cycle type, 0=PIO 1=DMA */
 220 #define HPC3_BESTAT_PIDSHIFT    9
 221 #define HPC3_BESTAT_PIDMASK     0x3f700 /* DMA channel parity identifier */
 222
 223         u32 _unused1[0x14000/4 - 5];    /* padding */
 224
 225         /* Now direct PIO per-HPC3 peripheral access to external regs. */
 226         volatile u32 scsi0_ext[256];    /* SCSI channel 0 external regs */
 227         u32 _unused2[0x7c00/4];
 228         volatile u32 scsi1_ext[256];    /* SCSI channel 1 external regs */
 229         u32 _unused3[0x7c00/4];
 230         volatile u32 eth_ext[320];      /* Ethernet external registers */
 231         u32 _unused4[0x3b00/4];
 232
 233         /* Per-peripheral device external registers and DMA/PIO control. */
 234         volatile u32 pbus_extregs[16][256];
 235         volatile u32 pbus_dmacfg[8][128];
 236         /* Cycles to spend in D3 for reads */
 237 #define HPC3_DMACFG_D3R_MASK            0x00000001
 238 #define HPC3_DMACFG_D3R_SHIFT           0
 239         /* Cycles to spend in D4 for reads */
 240 #define HPC3_DMACFG_D4R_MASK            0x0000001e
 241 #define HPC3_DMACFG_D4R_SHIFT           1
 242         /* Cycles to spend in D5 for reads */
 243 #define HPC3_DMACFG_D5R_MASK            0x000001e0
 244 #define HPC3_DMACFG_D5R_SHIFT           5
 245         /* Cycles to spend in D3 for writes */
 246 #define HPC3_DMACFG_D3W_MASK            0x00000200
 247 #define HPC3_DMACFG_D3W_SHIFT           9
 248         /* Cycles to spend in D4 for writes */
 249 #define HPC3_DMACFG_D4W_MASK            0x00003c00
 250 #define HPC3_DMACFG_D4W_SHIFT           10
 251         /* Cycles to spend in D5 for writes */
 252 #define HPC3_DMACFG_D5W_MASK            0x0003c000
 253 #define HPC3_DMACFG_D5W_SHIFT           14
 254         /* Enable 16-bit DMA access mode */
 255 #define HPC3_DMACFG_DS16                0x00040000
 256         /* Places halfwords on high 16 bits of bus */
 257 #define HPC3_DMACFG_EVENHI              0x00080000
 258         /* Make this device real time */
 259 #define HPC3_DMACFG_RTIME               0x00200000
 260         /* 5 bit burst count for DMA device */
 261 #define HPC3_DMACFG_BURST_MASK          0x07c00000
 262 #define HPC3_DMACFG_BURST_SHIFT 22
 263         /* Use live pbus_dreq unsynchronized signal */
 264 #define HPC3_DMACFG_DRQLIVE             0x08000000
 265         volatile u32 pbus_piocfg[16][64];
 266         /* Cycles to spend in P2 state for reads */
 267 #define HPC3_PIOCFG_P2R_MASK            0x00001
 268 #define HPC3_PIOCFG_P2R_SHIFT           0
 269         /* Cycles to spend in P3 state for reads */
 270 #define HPC3_PIOCFG_P3R_MASK            0x0001e
 271 #define HPC3_PIOCFG_P3R_SHIFT           1
 272         /* Cycles to spend in P4 state for reads */
 273 #define HPC3_PIOCFG_P4R_MASK            0x001e0
 274 #define HPC3_PIOCFG_P4R_SHIFT           5
 275         /* Cycles to spend in P2 state for writes */
 276 #define HPC3_PIOCFG_P2W_MASK            0x00200
 277 #define HPC3_PIOCFG_P2W_SHIFT           9
 278         /* Cycles to spend in P3 state for writes */
 279 #define HPC3_PIOCFG_P3W_MASK            0x03c00
 280 #define HPC3_PIOCFG_P3W_SHIFT           10
 281         /* Cycles to spend in P4 state for writes */
 282 #define HPC3_PIOCFG_P4W_MASK            0x3c000
 283 #define HPC3_PIOCFG_P4W_SHIFT           14
 284         /* Enable 16-bit PIO accesses */
 285 #define HPC3_PIOCFG_DS16                0x40000
 286         /* Place even address bits in bits <15:8> */
 287 #define HPC3_PIOCFG_EVENHI              0x80000
 288
 289         /* PBUS PROM control regs. */
 290         volatile u32 pbus_promwe;       /* PROM write enable register */
 291 #define HPC3_PROM_WENAB 0x1     /* Enable writes to the PROM */
 292
 293         u32 _unused5[0x0800/4 - 1];
 294         volatile u32 pbus_promswap;     /* Chip select swap reg */
 295 #define HPC3_PROM_SWAP  0x1     /* invert GIO addr bit to select prom0 or prom1 */
 296
 297         u32 _unused6[0x0800/4 - 1];
 298         volatile u32 pbus_gout; /* PROM general purpose output reg */
 299 #define HPC3_PROM_STAT  0x1     /* General purpose status bit in gout */
 300
 301         u32 _unused7[0x1000/4 - 1];
 302         volatile u32 rtcregs[14];       /* Dallas clock registers */
 303         u32 _unused8[50];
 304         volatile u32 bbram[8192-50-14]; /* Battery backed ram */
 305 };
 306
 307 /*
 308  * It is possible to have two HPC3's within the address space on
 309  * one machine, though only having one is more likely on an Indy.
 310  */
 311 extern struct hpc3_regs *hpc3c0, *hpc3c1;
 312 #define HPC3_CHIP0_BASE         0x1fb80000      /* physical */
 313 #define HPC3_CHIP1_BASE         0x1fb00000      /* physical */
 314
 315 extern void sgihpc_init(void);
 316
 317 #endif /* _SGI_HPC3_H */