arch/parisc/kernel/cache.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1999-2006 Helge Deller <deller@gmx.de> (07-13-1999)
   7  * Copyright (C) 1999 SuSE GmbH Nuernberg
   8  * Copyright (C) 2000 Philipp Rumpf (prumpf@tux.org)
   9  *
  10  * Cache and TLB management
  11  *
  12  */
  13
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <linux/mm.h>
  17 #include <linux/module.h>
  18 #include <linux/seq_file.h>
  19 #include <linux/pagemap.h>
  20 #include <linux/sched.h>
  21 #include <asm/pdc.h>
  22 #include <asm/cache.h>
  23 #include <asm/cacheflush.h>
  24 #include <asm/tlbflush.h>
  25 #include <asm/system.h>
  26 #include <asm/page.h>
  27 #include <asm/pgalloc.h>
  28 #include <asm/processor.h>
  29 #include <asm/sections.h>
  30
  31 int split_tlb __read_mostly;
  32 int dcache_stride __read_mostly;
  33 int icache_stride __read_mostly;
  34 EXPORT_SYMBOL(dcache_stride);
  35
  36
  37 /* On some machines (e.g. ones with the Merced bus), there can be
  38  * only a single PxTLB broadcast at a time; this must be guaranteed
  39  * by software.  We put a spinlock around all TLB flushes  to
  40  * ensure this.
  41  */
  42 DEFINE_SPINLOCK(pa_tlb_lock);
  43
  44 struct pdc_cache_info cache_info __read_mostly;
  45 #ifndef CONFIG_PA20
  46 static struct pdc_btlb_info btlb_info __read_mostly;
  47 #endif
  48
  49 #ifdef CONFIG_SMP
  50 void
  51 flush_data_cache(void)
  52 {
  53         on_each_cpu(flush_data_cache_local, NULL, 1);
  54 }
  55 void
  56 flush_instruction_cache(void)
  57 {
  58         on_each_cpu(flush_instruction_cache_local, NULL, 1);
  59 }
  60 #endif
  61
  62 void
  63 flush_cache_all_local(void)
  64 {
  65         flush_instruction_cache_local(NULL);
  66         flush_data_cache_local(NULL);
  67 }
  68 EXPORT_SYMBOL(flush_cache_all_local);
  69
  70 void
  71 update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
  72 {
  73         struct page *page = pte_page(pte);
  74
  75         if (pfn_valid(page_to_pfn(page)) && page_mapping(page) &&
  76             test_bit(PG_dcache_dirty, &page->flags)) {
  77
  78                 flush_kernel_dcache_page(page);
  79                 clear_bit(PG_dcache_dirty, &page->flags);
  80         } else if (parisc_requires_coherency())
  81                 flush_kernel_dcache_page(page);
  82 }
  83
  84 void
  85 show_cache_info(struct seq_file *m)
  86 {
  87         char buf[32];
  88
  89         seq_printf(m, "I-cache\t\t: %ld KB\n",
  90                 cache_info.ic_size/1024 );
  91         if (cache_info.dc_loop != 1)
  92                 snprintf(buf, 32, "%lu-way associative", cache_info.dc_loop);
  93         seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %s)\n",
  94                 cache_info.dc_size/1024,
  95                 (cache_info.dc_conf.cc_wt ? "WT":"WB"),
  96                 (cache_info.dc_conf.cc_sh ? ", shared I/D":""),
  97                 ((cache_info.dc_loop == 1) ? "direct mapped" : buf));
  98         seq_printf(m, "ITLB entries\t: %ld\n" "DTLB entries\t: %ld%s\n",
  99                 cache_info.it_size,
 100                 cache_info.dt_size,
 101                 cache_info.dt_conf.tc_sh ? " - shared with ITLB":""
 102         );
 103
 104 #ifndef CONFIG_PA20
 105         /* BTLB - Block TLB */
 106         if (btlb_info.max_size==0) {
 107                 seq_printf(m, "BTLB\t\t: not supported\n" );
 108         } else {
 109                 seq_printf(m,
 110                 "BTLB fixed\t: max. %d pages, pagesize=%d (%dMB)\n"
 111                 "BTLB fix-entr.\t: %d instruction, %d data (%d combined)\n"
 112                 "BTLB var-entr.\t: %d instruction, %d data (%d combined)\n",
 113                 btlb_info.max_size, (int)4096,
 114                 btlb_info.max_size>>8,
 115                 btlb_info.fixed_range_info.num_i,
 116                 btlb_info.fixed_range_info.num_d,
 117                 btlb_info.fixed_range_info.num_comb,
 118                 btlb_info.variable_range_info.num_i,
 119                 btlb_info.variable_range_info.num_d,
 120                 btlb_info.variable_range_info.num_comb
 121                 );
 122         }
 123 #endif
 124 }
 125
 126 void __init
 127 parisc_cache_init(void)
 128 {
 129         if (pdc_cache_info(&cache_info) < 0)
 130                 panic("parisc_cache_init: pdc_cache_info failed");
 131
 132 #if 0
 133         printk("ic_size %lx dc_size %lx it_size %lx\n",
 134                 cache_info.ic_size,
 135                 cache_info.dc_size,
 136                 cache_info.it_size);
 137
 138         printk("DC  base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
 139                 cache_info.dc_base,
 140                 cache_info.dc_stride,
 141                 cache_info.dc_count,
 142                 cache_info.dc_loop);
 143
 144         printk("dc_conf = 0x%lx  alias %d blk %d line %d shift %d\n",
 145                 *(unsigned long *) (&cache_info.dc_conf),
 146                 cache_info.dc_conf.cc_alias,
 147                 cache_info.dc_conf.cc_block,
 148                 cache_info.dc_conf.cc_line,
 149                 cache_info.dc_conf.cc_shift);
 150         printk("        wt %d sh %d cst %d hv %d\n",
 151                 cache_info.dc_conf.cc_wt,
 152                 cache_info.dc_conf.cc_sh,
 153                 cache_info.dc_conf.cc_cst,
 154                 cache_info.dc_conf.cc_hv);
 155
 156         printk("IC  base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
 157                 cache_info.ic_base,
 158                 cache_info.ic_stride,
 159                 cache_info.ic_count,
 160                 cache_info.ic_loop);
 161
 162         printk("ic_conf = 0x%lx  alias %d blk %d line %d shift %d\n",
 163                 *(unsigned long *) (&cache_info.ic_conf),
 164                 cache_info.ic_conf.cc_alias,
 165                 cache_info.ic_conf.cc_block,
 166                 cache_info.ic_conf.cc_line,
 167                 cache_info.ic_conf.cc_shift);
 168         printk("        wt %d sh %d cst %d hv %d\n",
 169                 cache_info.ic_conf.cc_wt,
 170                 cache_info.ic_conf.cc_sh,
 171                 cache_info.ic_conf.cc_cst,
 172                 cache_info.ic_conf.cc_hv);
 173
 174         printk("D-TLB conf: sh %d page %d cst %d aid %d pad1 %d \n",
 175                 cache_info.dt_conf.tc_sh,
 176                 cache_info.dt_conf.tc_page,
 177                 cache_info.dt_conf.tc_cst,
 178                 cache_info.dt_conf.tc_aid,
 179                 cache_info.dt_conf.tc_pad1);
 180
 181         printk("I-TLB conf: sh %d page %d cst %d aid %d pad1 %d \n",
 182                 cache_info.it_conf.tc_sh,
 183                 cache_info.it_conf.tc_page,
 184                 cache_info.it_conf.tc_cst,
 185                 cache_info.it_conf.tc_aid,
 186                 cache_info.it_conf.tc_pad1);
 187 #endif
 188
 189         split_tlb = 0;
 190         if (cache_info.dt_conf.tc_sh == 0 || cache_info.dt_conf.tc_sh == 2) {
 191                 if (cache_info.dt_conf.tc_sh == 2)
 192                         printk(KERN_WARNING "Unexpected TLB configuration. "
 193                         "Will flush I/D separately (could be optimized).\n");
 194
 195                 split_tlb = 1;
 196         }
 197
 198         /* "New and Improved" version from Jim Hull
 199          *      (1 << (cc_block-1)) * (cc_line << (4 + cnf.cc_shift))
 200          * The following CAFL_STRIDE is an optimized version, see
 201          * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023625.html
 202          * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023671.html
 203          */
 204 #define CAFL_STRIDE(cnf) (cnf.cc_line << (3 + cnf.cc_block + cnf.cc_shift))
 205         dcache_stride = CAFL_STRIDE(cache_info.dc_conf);
 206         icache_stride = CAFL_STRIDE(cache_info.ic_conf);
 207 #undef CAFL_STRIDE
 208
 209 #ifndef CONFIG_PA20
 210         if (pdc_btlb_info(&btlb_info) < 0) {
 211                 memset(&btlb_info, 0, sizeof btlb_info);
 212         }
 213 #endif
 214
 215         if ((boot_cpu_data.pdc.capabilities & PDC_MODEL_NVA_MASK) ==
 216                                                 PDC_MODEL_NVA_UNSUPPORTED) {
 217                 printk(KERN_WARNING "parisc_cache_init: Only equivalent aliasing supported!\n");
 218 #if 0
 219                 panic("SMP kernel required to avoid non-equivalent aliasing");
 220 #endif
 221         }
 222 }
 223
 224 void disable_sr_hashing(void)
 225 {
 226         int srhash_type, retval;
 227         unsigned long space_bits;
 228
 229         switch (boot_cpu_data.cpu_type) {
 230         case pcx: /* We shouldn't get this far.  setup.c should prevent it. */
 231                 BUG();
 232                 return;
 233
 234         case pcxs:
 235         case pcxt:
 236         case pcxt_:
 237                 srhash_type = SRHASH_PCXST;
 238                 break;
 239
 240         case pcxl:
 241                 srhash_type = SRHASH_PCXL;
 242                 break;
 243
 244         case pcxl2: /* pcxl2 doesn't support space register hashing */
 245                 return;
 246
 247         default: /* Currently all PA2.0 machines use the same ins. sequence */
 248                 srhash_type = SRHASH_PA20;
 249                 break;
 250         }
 251
 252         disable_sr_hashing_asm(srhash_type);
 253
 254         retval = pdc_spaceid_bits(&space_bits);
 255         /* If this procedure isn't implemented, don't panic. */
 256         if (retval < 0 && retval != PDC_BAD_OPTION)
 257                 panic("pdc_spaceid_bits call failed.\n");
 258         if (space_bits != 0)
 259                 panic("SpaceID hashing is still on!\n");
 260 }
 261
 262 /* Simple function to work out if we have an existing address translation
 263  * for a user space vma. */
 264 static inline int translation_exists(struct vm_area_struct *vma,
 265                                 unsigned long addr, unsigned long pfn)
 266 {
 267         pgd_t *pgd = pgd_offset(vma->vm_mm, addr);
 268         pmd_t *pmd;
 269         pte_t pte;
 270
 271         if(pgd_none(*pgd))
 272                 return 0;
 273
 274         pmd = pmd_offset(pgd, addr);
 275         if(pmd_none(*pmd) || pmd_bad(*pmd))
 276                 return 0;
 277
 278         /* We cannot take the pte lock here: flush_cache_page is usually
 279          * called with pte lock already held.  Whereas flush_dcache_page
 280          * takes flush_dcache_mmap_lock, which is lower in the hierarchy:
 281          * the vma itself is secure, but the pte might come or go racily.
 282          */
 283         pte = *pte_offset_map(pmd, addr);
 284         /* But pte_unmap() does nothing on this architecture */
 285
 286         /* Filter out coincidental file entries and swap entries */
 287         if (!(pte_val(pte) & (_PAGE_FLUSH|_PAGE_PRESENT)))
 288                 return 0;
 289
 290         return pte_pfn(pte) == pfn;
 291 }
 292
 293 /* Private function to flush a page from the cache of a non-current
 294  * process.  cr25 contains the Page Directory of the current user
 295  * process; we're going to hijack both it and the user space %sr3 to
 296  * temporarily make the non-current process current.  We have to do
 297  * this because cache flushing may cause a non-access tlb miss which
 298  * the handlers have to fill in from the pgd of the non-current
 299  * process. */
 300 static inline void
 301 flush_user_cache_page_non_current(struct vm_area_struct *vma,
 302                                   unsigned long vmaddr)
 303 {
 304         /* save the current process space and pgd */
 305         unsigned long space = mfsp(3), pgd = mfctl(25);
 306
 307         /* we don't mind taking interrupts since they may not
 308          * do anything with user space, but we can't
 309          * be preempted here */
 310         preempt_disable();
 311
 312         /* make us current */
 313         mtctl(__pa(vma->vm_mm->pgd), 25);
 314         mtsp(vma->vm_mm->context, 3);
 315
 316         flush_user_dcache_page(vmaddr);
 317         if(vma->vm_flags & VM_EXEC)
 318                 flush_user_icache_page(vmaddr);
 319
 320         /* put the old current process back */
 321         mtsp(space, 3);
 322         mtctl(pgd, 25);
 323         preempt_enable();
 324 }
 325
 326
 327 static inline void
 328 __flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr)
 329 {
 330         if (likely(vma->vm_mm->context == mfsp(3))) {
 331                 flush_user_dcache_page(vmaddr);
 332                 if (vma->vm_flags & VM_EXEC)
 333                         flush_user_icache_page(vmaddr);
 334         } else {
 335                 flush_user_cache_page_non_current(vma, vmaddr);
 336         }
 337 }
 338
 339 void flush_dcache_page(struct page *page)
 340 {
 341         struct address_space *mapping = page_mapping(page);
 342         struct vm_area_struct *mpnt;
 343         struct prio_tree_iter iter;
 344         unsigned long offset;
 345         unsigned long addr;
 346         pgoff_t pgoff;
 347         unsigned long pfn = page_to_pfn(page);
 348
 349
 350         if (mapping && !mapping_mapped(mapping)) {
 351                 set_bit(PG_dcache_dirty, &page->flags);
 352                 return;
 353         }
 354
 355         flush_kernel_dcache_page(page);
 356
 357         if (!mapping)
 358                 return;
 359
 360         pgoff = page->index << (PAGE_CACHE_SHIFT - PAGE_SHIFT);
 361
 362         /* We have carefully arranged in arch_get_unmapped_area() that
 363          * *any* mappings of a file are always congruently mapped (whether
 364          * declared as MAP_PRIVATE or MAP_SHARED), so we only need
 365          * to flush one address here for them all to become coherent */
 366
 367         flush_dcache_mmap_lock(mapping);
 368         vma_prio_tree_foreach(mpnt, &iter, &mapping->i_mmap, pgoff, pgoff) {
 369                 offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
 370                 addr = mpnt->vm_start + offset;
 371
 372                 /* Flush instructions produce non access tlb misses.
 373                  * On PA, we nullify these instructions rather than
 374                  * taking a page fault if the pte doesn't exist.
 375                  * This is just for speed.  If the page translation
 376                  * isn't there, there's no point exciting the
 377                  * nadtlb handler into a nullification frenzy.
 378                  *
 379                  * Make sure we really have this page: the private
 380                  * mappings may cover this area but have COW'd this
 381                  * particular page.
 382                  */
 383                 if (translation_exists(mpnt, addr, pfn)) {
 384                         __flush_cache_page(mpnt, addr);
 385                         break;
 386                 }
 387         }
 388         flush_dcache_mmap_unlock(mapping);
 389 }
 390 EXPORT_SYMBOL(flush_dcache_page);
 391
 392 /* Defined in arch/parisc/kernel/pacache.S */
 393 EXPORT_SYMBOL(flush_kernel_dcache_range_asm);
 394 EXPORT_SYMBOL(flush_kernel_dcache_page_asm);
 395 EXPORT_SYMBOL(flush_data_cache_local);
 396 EXPORT_SYMBOL(flush_kernel_icache_range_asm);
 397
 398 void clear_user_page_asm(void *page, unsigned long vaddr)
 399 {
 400         unsigned long flags;
 401         /* This function is implemented in assembly in pacache.S */
 402         extern void __clear_user_page_asm(void *page, unsigned long vaddr);
 403
 404         purge_tlb_start(flags);
 405         __clear_user_page_asm(page, vaddr);
 406         purge_tlb_end(flags);
 407 }
 408
 409 #define FLUSH_THRESHOLD 0x80000 /* 0.5MB */
 410 int parisc_cache_flush_threshold __read_mostly = FLUSH_THRESHOLD;
 411
 412 void __init parisc_setup_cache_timing(void)
 413 {
 414         unsigned long rangetime, alltime;
 415         unsigned long size;
 416
 417         alltime = mfctl(16);
 418         flush_data_cache();
 419         alltime = mfctl(16) - alltime;
 420
 421         size = (unsigned long)(_end - _text);
 422         rangetime = mfctl(16);
 423         flush_kernel_dcache_range((unsigned long)_text, size);
 424         rangetime = mfctl(16) - rangetime;
 425
 426         printk(KERN_DEBUG "Whole cache flush %lu cycles, flushing %lu bytes %lu cycles\n",
 427                 alltime, size, rangetime);
 428
 429         /* Racy, but if we see an intermediate value, it's ok too... */
 430         parisc_cache_flush_threshold = size * alltime / rangetime;
 431
 432         parisc_cache_flush_threshold = (parisc_cache_flush_threshold + L1_CACHE_BYTES - 1) &~ (L1_CACHE_BYTES - 1);
 433         if (!parisc_cache_flush_threshold)
 434                 parisc_cache_flush_threshold = FLUSH_THRESHOLD;
 435
 436         if (parisc_cache_flush_threshold > cache_info.dc_size)
 437                 parisc_cache_flush_threshold = cache_info.dc_size;
 438
 439         printk(KERN_INFO "Setting cache flush threshold to %x (%d CPUs online)\n", parisc_cache_flush_threshold, num_online_cpus());
 440 }
 441
 442 extern void purge_kernel_dcache_page(unsigned long);
 443 extern void clear_user_page_asm(void *page, unsigned long vaddr);
 444
 445 void clear_user_page(void *page, unsigned long vaddr, struct page *pg)
 446 {
 447         unsigned long flags;
 448
 449         purge_kernel_dcache_page((unsigned long)page);
 450         purge_tlb_start(flags);
 451         pdtlb_kernel(page);
 452         purge_tlb_end(flags);
 453         clear_user_page_asm(page, vaddr);
 454 }
 455 EXPORT_SYMBOL(clear_user_page);
 456
 457 void flush_kernel_dcache_page_addr(void *addr)
 458 {
 459         unsigned long flags;
 460
 461         flush_kernel_dcache_page_asm(addr);
 462         purge_tlb_start(flags);
 463         pdtlb_kernel(addr);
 464         purge_tlb_end(flags);
 465 }
 466 EXPORT_SYMBOL(flush_kernel_dcache_page_addr);
 467
 468 void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
 469                     struct page *pg)
 470 {
 471         /* no coherency needed (all in kmap/kunmap) */
 472         copy_user_page_asm(vto, vfrom);
 473         if (!parisc_requires_coherency())
 474                 flush_kernel_dcache_page_asm(vto);
 475 }
 476 EXPORT_SYMBOL(copy_user_page);
 477
 478 #ifdef CONFIG_PA8X00
 479
 480 void kunmap_parisc(void *addr)
 481 {
 482         if (parisc_requires_coherency())
 483                 flush_kernel_dcache_page_addr(addr);
 484 }
 485 EXPORT_SYMBOL(kunmap_parisc);
 486 #endif
 487
 488 void __flush_tlb_range(unsigned long sid, unsigned long start,
 489                        unsigned long end)
 490 {
 491         unsigned long npages;
 492
 493         npages = ((end - (start & PAGE_MASK)) + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
 494         if (npages >= 512)  /* 2MB of space: arbitrary, should be tuned */
 495                 flush_tlb_all();
 496         else {
 497                 unsigned long flags;
 498
 499                 mtsp(sid, 1);
 500                 purge_tlb_start(flags);
 501                 if (split_tlb) {
 502                         while (npages--) {
 503                                 pdtlb(start);
 504                                 pitlb(start);
 505                                 start += PAGE_SIZE;
 506                         }
 507                 } else {
 508                         while (npages--) {
 509                                 pdtlb(start);
 510                                 start += PAGE_SIZE;
 511                         }
 512                 }
 513                 purge_tlb_end(flags);
 514         }
 515 }
 516
 517 static void cacheflush_h_tmp_function(void *dummy)
 518 {
 519         flush_cache_all_local();
 520 }
 521
 522 void flush_cache_all(void)
 523 {
 524         on_each_cpu(cacheflush_h_tmp_function, NULL, 1);
 525 }
 526
 527 void flush_cache_mm(struct mm_struct *mm)
 528 {
 529 #ifdef CONFIG_SMP
 530         flush_cache_all();
 531 #else
 532         flush_cache_all_local();
 533 #endif
 534 }
 535
 536 void
 537 flush_user_dcache_range(unsigned long start, unsigned long end)
 538 {
 539         if ((end - start) < parisc_cache_flush_threshold)
 540                 flush_user_dcache_range_asm(start,end);
 541         else
 542                 flush_data_cache();
 543 }
 544
 545 void
 546 flush_user_icache_range(unsigned long start, unsigned long end)
 547 {
 548         if ((end - start) < parisc_cache_flush_threshold)
 549                 flush_user_icache_range_asm(start,end);
 550         else
 551                 flush_instruction_cache();
 552 }
 553
 554
 555 void flush_cache_range(struct vm_area_struct *vma,
 556                 unsigned long start, unsigned long end)
 557 {
 558         int sr3;
 559
 560         BUG_ON(!vma->vm_mm->context);
 561
 562         sr3 = mfsp(3);
 563         if (vma->vm_mm->context == sr3) {
 564                 flush_user_dcache_range(start,end);
 565                 flush_user_icache_range(start,end);
 566         } else {
 567                 flush_cache_all();
 568         }
 569 }
 570
 571 void
 572 flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn)
 573 {
 574         BUG_ON(!vma->vm_mm->context);
 575
 576         if (likely(translation_exists(vma, vmaddr, pfn)))
 577                 __flush_cache_page(vma, vmaddr);
 578
 579 }