| blob | 4e6a1a407bbd093bcf56cc553d0033c693b361bb |
1 /*
2 * MPC8378E RDB Device Tree Source
3 *
4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
12 /dts-v1/;
14 / {
15 compatible = "fsl,mpc8378rdb";
16 #address-cells = <1>;
17 #size-cells = <1>;
19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 serial0 = &serial0;
23 serial1 = &serial1;
24 pci0 = &pci0;
25 pci1 = &pci1;
26 pci2 = &pci2;
27 };
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
33 PowerPC,8378@0 {
34 device_type = "cpu";
35 reg = <0x0>;
36 d-cache-line-size = <32>;
37 i-cache-line-size = <32>;
38 d-cache-size = <32768>;
39 i-cache-size = <32768>;
40 timebase-frequency = <0>;
41 bus-frequency = <0>;
42 clock-frequency = <0>;
43 };
44 };
46 memory {
47 device_type = "memory";
48 reg = <0x00000000 0x10000000>; // 256MB at 0
49 };
51 localbus@e0005000 {
52 #address-cells = <2>;
53 #size-cells = <1>;
54 compatible = "fsl,mpc8378-elbc", "fsl,elbc", "simple-bus";
55 reg = <0xe0005000 0x1000>;
56 interrupts = <77 0x8>;
57 interrupt-parent = <&ipic>;
59 // CS0 and CS1 are swapped when
60 // booting from nand, but the
61 // addresses are the same.
62 ranges = <0x0 0x0 0xfe000000 0x00800000
63 0x1 0x0 0xe0600000 0x00008000
64 0x2 0x0 0xf0000000 0x00020000
65 0x3 0x0 0xfa000000 0x00008000>;
67 flash@0,0 {
68 #address-cells = <1>;
69 #size-cells = <1>;
70 compatible = "cfi-flash";
71 reg = <0x0 0x0 0x800000>;
72 bank-width = <2>;
73 device-width = <1>;
74 };
76 nand@1,0 {
77 #address-cells = <1>;
78 #size-cells = <1>;
79 compatible = "fsl,mpc8378-fcm-nand",
80 "fsl,elbc-fcm-nand";
81 reg = <0x1 0x0 0x8000>;
83 u-boot@0 {
84 reg = <0x0 0x100000>;
85 read-only;
86 };
88 kernel@100000 {
89 reg = <0x100000 0x300000>;
90 };
91 fs@400000 {
92 reg = <0x400000 0x1c00000>;
93 };
94 };
95 };
97 immr@e0000000 {
98 #address-cells = <1>;
99 #size-cells = <1>;
100 device_type = "soc";
101 compatible = "simple-bus";
102 ranges = <0x0 0xe0000000 0x00100000>;
103 reg = <0xe0000000 0x00000200>;
104 bus-frequency = <0>;
106 wdt@200 {
107 device_type = "watchdog";
108 compatible = "mpc83xx_wdt";
109 reg = <0x200 0x100>;
110 };
112 gpio1: gpio-controller@c00 {
113 #gpio-cells = <2>;
114 compatible = "fsl,mpc8378-gpio", "fsl,mpc8349-gpio";
115 reg = <0xc00 0x100>;
116 interrupts = <74 0x8>;
117 interrupt-parent = <&ipic>;
118 gpio-controller;
119 };
121 gpio2: gpio-controller@d00 {
122 #gpio-cells = <2>;
123 compatible = "fsl,mpc8378-gpio", "fsl,mpc8349-gpio";
124 reg = <0xd00 0x100>;
125 interrupts = <75 0x8>;
126 interrupt-parent = <&ipic>;
127 gpio-controller;
128 };
130 sleep-nexus {
131 #address-cells = <1>;
132 #size-cells = <1>;
133 compatible = "simple-bus";
134 sleep = <&pmc 0x0c000000>;
135 ranges;
137 i2c@3000 {
138 #address-cells = <1>;
139 #size-cells = <0>;
140 cell-index = <0>;
141 compatible = "fsl-i2c";
142 reg = <0x3000 0x100>;
143 interrupts = <14 0x8>;
144 interrupt-parent = <&ipic>;
145 dfsrr;
147 dtt@48 {
148 compatible = "national,lm75";
149 reg = <0x48>;
150 };
152 at24@50 {
153 compatible = "at24,24c256";
154 reg = <0x50>;
155 };
157 rtc@68 {
158 compatible = "dallas,ds1339";
159 reg = <0x68>;
160 };
162 mcu_pio: mcu@a {
163 #gpio-cells = <2>;
164 compatible = "fsl,mc9s08qg8-mpc8378erdb",
165 "fsl,mcu-mpc8349emitx";
166 reg = <0x0a>;
167 gpio-controller;
168 };
169 };
171 sdhci@2e000 {
172 compatible = "fsl,mpc8378-esdhc", "fsl,esdhc";
173 reg = <0x2e000 0x1000>;
174 interrupts = <42 0x8>;
175 interrupt-parent = <&ipic>;
176 sdhci,wp-inverted;
177 /* Filled in by U-Boot */
178 clock-frequency = <111111111>;
179 };
180 };
182 i2c@3100 {
183 #address-cells = <1>;
184 #size-cells = <0>;
185 cell-index = <1>;
186 compatible = "fsl-i2c";
187 reg = <0x3100 0x100>;
188 interrupts = <15 0x8>;
189 interrupt-parent = <&ipic>;
190 dfsrr;
191 };
193 spi@7000 {
194 cell-index = <0>;
195 compatible = "fsl,spi";
196 reg = <0x7000 0x1000>;
197 interrupts = <16 0x8>;
198 interrupt-parent = <&ipic>;
199 mode = "cpu";
200 };
202 dma@82a8 {
203 #address-cells = <1>;
204 #size-cells = <1>;
205 compatible = "fsl,mpc8378-dma", "fsl,elo-dma";
206 reg = <0x82a8 4>;
207 ranges = <0 0x8100 0x1a8>;
208 interrupt-parent = <&ipic>;
209 interrupts = <71 8>;
210 cell-index = <0>;
211 dma-channel@0 {
212 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
213 reg = <0 0x80>;
214 cell-index = <0>;
215 interrupt-parent = <&ipic>;
216 interrupts = <71 8>;
217 };
218 dma-channel@80 {
219 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
220 reg = <0x80 0x80>;
221 cell-index = <1>;
222 interrupt-parent = <&ipic>;
223 interrupts = <71 8>;
224 };
225 dma-channel@100 {
226 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
227 reg = <0x100 0x80>;
228 cell-index = <2>;
229 interrupt-parent = <&ipic>;
230 interrupts = <71 8>;
231 };
232 dma-channel@180 {
233 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
234 reg = <0x180 0x28>;
235 cell-index = <3>;
236 interrupt-parent = <&ipic>;
237 interrupts = <71 8>;
238 };
239 };
241 usb@23000 {
242 compatible = "fsl-usb2-dr";
243 reg = <0x23000 0x1000>;
244 #address-cells = <1>;
245 #size-cells = <0>;
246 interrupt-parent = <&ipic>;
247 interrupts = <38 0x8>;
248 phy_type = "ulpi";
249 sleep = <&pmc 0x00c00000>;
250 };
252 enet0: ethernet@24000 {
253 #address-cells = <1>;
254 #size-cells = <1>;
255 cell-index = <0>;
256 device_type = "network";
257 model = "eTSEC";
258 compatible = "gianfar";
259 reg = <0x24000 0x1000>;
260 ranges = <0x0 0x24000 0x1000>;
261 local-mac-address = [ 00 00 00 00 00 00 ];
262 interrupts = <32 0x8 33 0x8 34 0x8>;
263 phy-connection-type = "mii";
264 interrupt-parent = <&ipic>;
265 tbi-handle = <&tbi0>;
266 phy-handle = <&phy2>;
267 sleep = <&pmc 0xc0000000>;
268 fsl,magic-packet;
270 mdio@520 {
271 #address-cells = <1>;
272 #size-cells = <0>;
273 compatible = "fsl,gianfar-mdio";
274 reg = <0x520 0x20>;
276 phy2: ethernet-phy@2 {
277 interrupt-parent = <&ipic>;
278 interrupts = <17 0x8>;
279 reg = <0x2>;
280 device_type = "ethernet-phy";
281 };
283 tbi0: tbi-phy@11 {
284 reg = <0x11>;
285 device_type = "tbi-phy";
286 };
287 };
288 };
290 enet1: ethernet@25000 {
291 #address-cells = <1>;
292 #size-cells = <1>;
293 cell-index = <1>;
294 device_type = "network";
295 model = "eTSEC";
296 compatible = "gianfar";
297 reg = <0x25000 0x1000>;
298 ranges = <0x0 0x25000 0x1000>;
299 local-mac-address = [ 00 00 00 00 00 00 ];
300 interrupts = <35 0x8 36 0x8 37 0x8>;
301 phy-connection-type = "mii";
302 interrupt-parent = <&ipic>;
303 fixed-link = <1 1 1000 0 0>;
304 tbi-handle = <&tbi1>;
305 sleep = <&pmc 0x30000000>;
306 fsl,magic-packet;
308 mdio@520 {
309 #address-cells = <1>;
310 #size-cells = <0>;
311 compatible = "fsl,gianfar-tbi";
312 reg = <0x520 0x20>;
314 tbi1: tbi-phy@11 {
315 reg = <0x11>;
316 device_type = "tbi-phy";
317 };
318 };
319 };
321 serial0: serial@4500 {
322 cell-index = <0>;
323 device_type = "serial";
324 compatible = "ns16550";
325 reg = <0x4500 0x100>;
326 clock-frequency = <0>;
327 interrupts = <9 0x8>;
328 interrupt-parent = <&ipic>;
329 };
331 serial1: serial@4600 {
332 cell-index = <1>;
333 device_type = "serial";
334 compatible = "ns16550";
335 reg = <0x4600 0x100>;
336 clock-frequency = <0>;
337 interrupts = <10 0x8>;
338 interrupt-parent = <&ipic>;
339 };
341 crypto@30000 {
342 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
343 "fsl,sec2.1", "fsl,sec2.0";
344 reg = <0x30000 0x10000>;
345 interrupts = <11 0x8>;
346 interrupt-parent = <&ipic>;
347 fsl,num-channels = <4>;
348 fsl,channel-fifo-len = <24>;
349 fsl,exec-units-mask = <0x9fe>;
350 fsl,descriptor-types-mask = <0x3ab0ebf>;
351 sleep = <&pmc 0x03000000>;
352 };
354 /* IPIC
355 * interrupts cell = <intr #, sense>
356 * sense values match linux IORESOURCE_IRQ_* defines:
357 * sense == 8: Level, low assertion
358 * sense == 2: Edge, high-to-low change
359 */
360 ipic: interrupt-controller@700 {
361 compatible = "fsl,ipic";
362 interrupt-controller;
363 #address-cells = <0>;
364 #interrupt-cells = <2>;
365 reg = <0x700 0x100>;
366 };
368 pmc: power@b00 {
369 compatible = "fsl,mpc8378-pmc", "fsl,mpc8349-pmc";
370 reg = <0xb00 0x100 0xa00 0x100>;
371 interrupts = <80 0x8>;
372 interrupt-parent = <&ipic>;
373 };
374 };
376 pci0: pci@e0008500 {
377 interrupt-map-mask = <0xf800 0 0 7>;
378 interrupt-map = <
379 /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
381 /* IDSEL AD14 IRQ6 inta */
382 0x7000 0x0 0x0 0x1 &ipic 22 0x8
384 /* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
385 0x7800 0x0 0x0 0x1 &ipic 21 0x8
386 0x7800 0x0 0x0 0x2 &ipic 22 0x8
387 0x7800 0x0 0x0 0x4 &ipic 23 0x8
389 /* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
390 0xE000 0x0 0x0 0x1 &ipic 23 0x8
391 0xE000 0x0 0x0 0x2 &ipic 21 0x8
392 0xE000 0x0 0x0 0x3 &ipic 22 0x8>;
393 interrupt-parent = <&ipic>;
394 interrupts = <66 0x8>;
395 bus-range = <0 0>;
396 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
397 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
398 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
399 sleep = <&pmc 0x00010000>;
400 clock-frequency = <66666666>;
401 #interrupt-cells = <1>;
402 #size-cells = <2>;
403 #address-cells = <3>;
404 reg = <0xe0008500 0x100 /* internal registers */
405 0xe0008300 0x8>; /* config space access registers */
406 compatible = "fsl,mpc8349-pci";
407 device_type = "pci";
408 };
410 pci1: pcie@e0009000 {
411 #address-cells = <3>;
412 #size-cells = <2>;
413 #interrupt-cells = <1>;
414 device_type = "pci";
415 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
416 reg = <0xe0009000 0x00001000>;
417 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
418 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
419 bus-range = <0 255>;
420 interrupt-map-mask = <0xf800 0 0 7>;
421 interrupt-map = <0 0 0 1 &ipic 1 8
422 0 0 0 2 &ipic 1 8
423 0 0 0 3 &ipic 1 8
424 0 0 0 4 &ipic 1 8>;
425 sleep = <&pmc 0x00300000>;
426 clock-frequency = <0>;
428 pcie@0 {
429 #address-cells = <3>;
430 #size-cells = <2>;
431 device_type = "pci";
432 reg = <0 0 0 0 0>;
433 ranges = <0x02000000 0 0xa8000000
434 0x02000000 0 0xa8000000
435 0 0x10000000
436 0x01000000 0 0x00000000
437 0x01000000 0 0x00000000
438 0 0x00800000>;
439 };
440 };
442 pci2: pcie@e000a000 {
443 #address-cells = <3>;
444 #size-cells = <2>;
445 #interrupt-cells = <1>;
446 device_type = "pci";
447 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
448 reg = <0xe000a000 0x00001000>;
449 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
450 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
451 bus-range = <0 255>;
452 interrupt-map-mask = <0xf800 0 0 7>;
453 interrupt-map = <0 0 0 1 &ipic 2 8
454 0 0 0 2 &ipic 2 8
455 0 0 0 3 &ipic 2 8
456 0 0 0 4 &ipic 2 8>;
457 sleep = <&pmc 0x000c0000>;
458 clock-frequency = <0>;
460 pcie@0 {
461 #address-cells = <3>;
462 #size-cells = <2>;
463 device_type = "pci";
464 reg = <0 0 0 0 0>;
465 ranges = <0x02000000 0 0xc8000000
466 0x02000000 0 0xc8000000
467 0 0x10000000
468 0x01000000 0 0x00000000
469 0x01000000 0 0x00000000
470 0 0x00800000>;
471 };
472 };
473 };