| blob | 24dcc0ecf24628f47825c43aa3a251cf8575dcda |
1 /*
2 * Boot code and exception vectors for Book3E processors
3 *
4 * Copyright (C) 2007 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
12 #include <linux/threads.h>
13 #include <asm/reg.h>
14 #include <asm/page.h>
15 #include <asm/ppc_asm.h>
16 #include <asm/asm-offsets.h>
17 #include <asm/cputable.h>
18 #include <asm/setup.h>
19 #include <asm/thread_info.h>
20 #include <asm/exception-64e.h>
21 #include <asm/bug.h>
22 #include <asm/irqflags.h>
23 #include <asm/ptrace.h>
24 #include <asm/ppc-opcode.h>
25 #include <asm/mmu.h>
27 /* XXX This will ultimately add space for a special exception save
28 * structure used to save things like SRR0/SRR1, SPRGs, MAS, etc...
29 * when taking special interrupts. For now we don't support that,
30 * special interrupts from within a non-standard level will probably
31 * blow you up
32 */
33 #define SPECIAL_EXC_FRAME_SIZE INT_FRAME_SIZE
35 /* Exception prolog code for all exceptions */
36 #define EXCEPTION_PROLOG(n, type, addition) \
37 mtspr SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */ \
38 mfspr r13,SPRN_SPRG_PACA; /* get PACA */ \
39 std r10,PACA_EX##type+EX_R10(r13); \
40 std r11,PACA_EX##type+EX_R11(r13); \
41 mfcr r10; /* save CR */ \
42 addition; /* additional code for that exc. */ \
43 std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \
44 stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
45 mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \
46 type##_SET_KSTACK; /* get special stack if necessary */\
47 andi. r10,r11,MSR_PR; /* save stack pointer */ \
48 beq 1f; /* branch around if supervisor */ \
49 ld r1,PACAKSAVE(r13); /* get kernel stack coming from usr */\
50 1: cmpdi cr1,r1,0; /* check if SP makes sense */ \
51 bge- cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \
52 mfspr r10,SPRN_##type##_SRR0; /* read SRR0 before touching stack */
54 /* Exception type-specific macros */
55 #define GEN_SET_KSTACK \
56 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */
57 #define SPRN_GEN_SRR0 SPRN_SRR0
58 #define SPRN_GEN_SRR1 SPRN_SRR1
60 #define CRIT_SET_KSTACK \
61 ld r1,PACA_CRIT_STACK(r13); \
62 subi r1,r1,SPECIAL_EXC_FRAME_SIZE;
63 #define SPRN_CRIT_SRR0 SPRN_CSRR0
64 #define SPRN_CRIT_SRR1 SPRN_CSRR1
66 #define DBG_SET_KSTACK \
67 ld r1,PACA_DBG_STACK(r13); \
68 subi r1,r1,SPECIAL_EXC_FRAME_SIZE;
69 #define SPRN_DBG_SRR0 SPRN_DSRR0
70 #define SPRN_DBG_SRR1 SPRN_DSRR1
72 #define MC_SET_KSTACK \
73 ld r1,PACA_MC_STACK(r13); \
74 subi r1,r1,SPECIAL_EXC_FRAME_SIZE;
75 #define SPRN_MC_SRR0 SPRN_MCSRR0
76 #define SPRN_MC_SRR1 SPRN_MCSRR1
78 #define NORMAL_EXCEPTION_PROLOG(n, addition) \
79 EXCEPTION_PROLOG(n, GEN, addition##_GEN)
81 #define CRIT_EXCEPTION_PROLOG(n, addition) \
82 EXCEPTION_PROLOG(n, CRIT, addition##_CRIT)
84 #define DBG_EXCEPTION_PROLOG(n, addition) \
85 EXCEPTION_PROLOG(n, DBG, addition##_DBG)
87 #define MC_EXCEPTION_PROLOG(n, addition) \
88 EXCEPTION_PROLOG(n, MC, addition##_MC)
91 /* Variants of the "addition" argument for the prolog
92 */
93 #define PROLOG_ADDITION_NONE_GEN
94 #define PROLOG_ADDITION_NONE_CRIT
95 #define PROLOG_ADDITION_NONE_DBG
96 #define PROLOG_ADDITION_NONE_MC
98 #define PROLOG_ADDITION_MASKABLE_GEN \
99 lbz r11,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */ \
100 cmpwi cr0,r11,0; /* yes -> go out of line */ \
101 beq masked_interrupt_book3e;
103 #define PROLOG_ADDITION_2REGS_GEN \
104 std r14,PACA_EXGEN+EX_R14(r13); \
105 std r15,PACA_EXGEN+EX_R15(r13)
107 #define PROLOG_ADDITION_1REG_GEN \
108 std r14,PACA_EXGEN+EX_R14(r13);
110 #define PROLOG_ADDITION_2REGS_CRIT \
111 std r14,PACA_EXCRIT+EX_R14(r13); \
112 std r15,PACA_EXCRIT+EX_R15(r13)
114 #define PROLOG_ADDITION_2REGS_DBG \
115 std r14,PACA_EXDBG+EX_R14(r13); \
116 std r15,PACA_EXDBG+EX_R15(r13)
118 #define PROLOG_ADDITION_2REGS_MC \
119 std r14,PACA_EXMC+EX_R14(r13); \
120 std r15,PACA_EXMC+EX_R15(r13)
122 /* Core exception code for all exceptions except TLB misses.
123 * XXX: Needs to make SPRN_SPRG_GEN depend on exception type
124 */
125 #define EXCEPTION_COMMON(n, excf, ints) \
126 std r0,GPR0(r1); /* save r0 in stackframe */ \
127 std r2,GPR2(r1); /* save r2 in stackframe */ \
128 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
129 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
130 std r9,GPR9(r1); /* save r9 in stackframe */ \
131 std r10,_NIP(r1); /* save SRR0 to stackframe */ \
132 std r11,_MSR(r1); /* save SRR1 to stackframe */ \
133 ACCOUNT_CPU_USER_ENTRY(r10,r11);/* accounting (uses cr0+eq) */ \
134 ld r3,excf+EX_R10(r13); /* get back r10 */ \
135 ld r4,excf+EX_R11(r13); /* get back r11 */ \
136 mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 */ \
137 std r12,GPR12(r1); /* save r12 in stackframe */ \
138 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
139 mflr r6; /* save LR in stackframe */ \
140 mfctr r7; /* save CTR in stackframe */ \
141 mfspr r8,SPRN_XER; /* save XER in stackframe */ \
142 ld r9,excf+EX_R1(r13); /* load orig r1 back from PACA */ \
143 lwz r10,excf+EX_CR(r13); /* load orig CR back from PACA */ \
144 lbz r11,PACASOFTIRQEN(r13); /* get current IRQ softe */ \
145 ld r12,exception_marker@toc(r2); \
146 li r0,0; \
147 std r3,GPR10(r1); /* save r10 to stackframe */ \
148 std r4,GPR11(r1); /* save r11 to stackframe */ \
149 std r5,GPR13(r1); /* save it to stackframe */ \
150 std r6,_LINK(r1); \
151 std r7,_CTR(r1); \
152 std r8,_XER(r1); \
153 li r3,(n)+1; /* indicate partial regs in trap */ \
154 std r9,0(r1); /* store stack frame back link */ \
155 std r10,_CCR(r1); /* store orig CR in stackframe */ \
156 std r9,GPR1(r1); /* store stack frame back link */ \
157 std r11,SOFTE(r1); /* and save it to stackframe */ \
158 std r12,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ \
159 std r3,_TRAP(r1); /* set trap number */ \
160 std r0,RESULT(r1); /* clear regs->result */ \
161 ints;
163 /* Variants for the "ints" argument */
164 #define INTS_KEEP
165 #define INTS_DISABLE_SOFT \
166 stb r0,PACASOFTIRQEN(r13); /* mark interrupts soft-disabled */ \
167 TRACE_DISABLE_INTS;
168 #define INTS_DISABLE_HARD \
169 stb r0,PACAHARDIRQEN(r13); /* and hard disabled */
170 #define INTS_DISABLE_ALL \
171 INTS_DISABLE_SOFT \
172 INTS_DISABLE_HARD
174 /* This is called by exceptions that used INTS_KEEP (that is did not clear
175 * neither soft nor hard IRQ indicators in the PACA. This will restore MSR:EE
176 * to it's previous value
177 *
178 * XXX In the long run, we may want to open-code it in order to separate the
179 * load from the wrtee, thus limiting the latency caused by the dependency
180 * but at this point, I'll favor code clarity until we have a near to final
181 * implementation
182 */
183 #define INTS_RESTORE_HARD \
184 ld r11,_MSR(r1); \
185 wrtee r11;
187 /* XXX FIXME: Restore r14/r15 when necessary */
188 #define BAD_STACK_TRAMPOLINE(n) \
189 exc_##n##_bad_stack: \
190 li r1,(n); /* get exception number */ \
191 sth r1,PACA_TRAP_SAVE(r13); /* store trap */ \
192 b bad_stack_book3e; /* bad stack error */
194 #define EXCEPTION_STUB(loc, label) \
195 . = interrupt_base_book3e + loc; \
196 nop; /* To make debug interrupts happy */ \
197 b exc_##label##_book3e;
199 #define ACK_NONE(r)
200 #define ACK_DEC(r) \
201 lis r,TSR_DIS@h; \
202 mtspr SPRN_TSR,r
203 #define ACK_FIT(r) \
204 lis r,TSR_FIS@h; \
205 mtspr SPRN_TSR,r
207 #define MASKABLE_EXCEPTION(trapnum, label, hdlr, ack) \
208 START_EXCEPTION(label); \
209 NORMAL_EXCEPTION_PROLOG(trapnum, PROLOG_ADDITION_MASKABLE) \
210 EXCEPTION_COMMON(trapnum, PACA_EXGEN, INTS_DISABLE_ALL) \
211 ack(r8); \
212 addi r3,r1,STACK_FRAME_OVERHEAD; \
213 bl hdlr; \
214 b .ret_from_except_lite;
216 /* This value is used to mark exception frames on the stack. */
217 .section ".toc","aw"
218 exception_marker:
219 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
222 /*
223 * And here we have the exception vectors !
224 */
226 .text
227 .balign 0x1000
228 .globl interrupt_base_book3e
229 interrupt_base_book3e: /* fake trap */
230 /* Note: If real debug exceptions are supported by the HW, the vector
231 * below will have to be patched up to point to an appropriate handler
232 */
233 EXCEPTION_STUB(0x000, machine_check) /* 0x0200 */
234 EXCEPTION_STUB(0x020, critical_input) /* 0x0580 */
235 EXCEPTION_STUB(0x040, debug_crit) /* 0x0d00 */
236 EXCEPTION_STUB(0x060, data_storage) /* 0x0300 */
237 EXCEPTION_STUB(0x080, instruction_storage) /* 0x0400 */
238 EXCEPTION_STUB(0x0a0, external_input) /* 0x0500 */
239 EXCEPTION_STUB(0x0c0, alignment) /* 0x0600 */
240 EXCEPTION_STUB(0x0e0, program) /* 0x0700 */
241 EXCEPTION_STUB(0x100, fp_unavailable) /* 0x0800 */
242 EXCEPTION_STUB(0x120, system_call) /* 0x0c00 */
243 EXCEPTION_STUB(0x140, ap_unavailable) /* 0x0f20 */
244 EXCEPTION_STUB(0x160, decrementer) /* 0x0900 */
245 EXCEPTION_STUB(0x180, fixed_interval) /* 0x0980 */
246 EXCEPTION_STUB(0x1a0, watchdog) /* 0x09f0 */
247 EXCEPTION_STUB(0x1c0, data_tlb_miss)
248 EXCEPTION_STUB(0x1e0, instruction_tlb_miss)
250 #if 0
251 EXCEPTION_STUB(0x280, processor_doorbell)
252 EXCEPTION_STUB(0x220, processor_doorbell_crit)
253 #endif
254 .globl interrupt_end_book3e
255 interrupt_end_book3e:
257 /* Critical Input Interrupt */
258 START_EXCEPTION(critical_input);
259 CRIT_EXCEPTION_PROLOG(0x100, PROLOG_ADDITION_NONE)
260 // EXCEPTION_COMMON(0x100, PACA_EXCRIT, INTS_DISABLE_ALL)
261 // bl special_reg_save_crit
262 // addi r3,r1,STACK_FRAME_OVERHEAD
263 // bl .critical_exception
264 // b ret_from_crit_except
265 b .
267 /* Machine Check Interrupt */
268 START_EXCEPTION(machine_check);
269 CRIT_EXCEPTION_PROLOG(0x200, PROLOG_ADDITION_NONE)
270 // EXCEPTION_COMMON(0x200, PACA_EXMC, INTS_DISABLE_ALL)
271 // bl special_reg_save_mc
272 // addi r3,r1,STACK_FRAME_OVERHEAD
273 // bl .machine_check_exception
274 // b ret_from_mc_except
275 b .
277 /* Data Storage Interrupt */
278 START_EXCEPTION(data_storage)
279 NORMAL_EXCEPTION_PROLOG(0x300, PROLOG_ADDITION_2REGS)
280 mfspr r14,SPRN_DEAR
281 mfspr r15,SPRN_ESR
282 EXCEPTION_COMMON(0x300, PACA_EXGEN, INTS_KEEP)
283 b storage_fault_common
285 /* Instruction Storage Interrupt */
286 START_EXCEPTION(instruction_storage);
287 NORMAL_EXCEPTION_PROLOG(0x400, PROLOG_ADDITION_2REGS)
288 li r15,0
289 mr r14,r10
290 EXCEPTION_COMMON(0x400, PACA_EXGEN, INTS_KEEP)
291 b storage_fault_common
293 /* External Input Interrupt */
294 MASKABLE_EXCEPTION(0x500, external_input, .do_IRQ, ACK_NONE)
296 /* Alignment */
297 START_EXCEPTION(alignment);
298 NORMAL_EXCEPTION_PROLOG(0x600, PROLOG_ADDITION_2REGS)
299 mfspr r14,SPRN_DEAR
300 mfspr r15,SPRN_ESR
301 EXCEPTION_COMMON(0x600, PACA_EXGEN, INTS_KEEP)
302 b alignment_more /* no room, go out of line */
304 /* Program Interrupt */
305 START_EXCEPTION(program);
306 NORMAL_EXCEPTION_PROLOG(0x700, PROLOG_ADDITION_1REG)
307 mfspr r14,SPRN_ESR
308 EXCEPTION_COMMON(0x700, PACA_EXGEN, INTS_DISABLE_SOFT)
309 std r14,_DSISR(r1)
310 addi r3,r1,STACK_FRAME_OVERHEAD
311 ld r14,PACA_EXGEN+EX_R14(r13)
312 bl .save_nvgprs
313 INTS_RESTORE_HARD
314 bl .program_check_exception
315 b .ret_from_except
317 /* Floating Point Unavailable Interrupt */
318 START_EXCEPTION(fp_unavailable);
319 NORMAL_EXCEPTION_PROLOG(0x800, PROLOG_ADDITION_NONE)
320 /* we can probably do a shorter exception entry for that one... */
321 EXCEPTION_COMMON(0x800, PACA_EXGEN, INTS_KEEP)
322 bne 1f /* if from user, just load it up */
323 bl .save_nvgprs
324 addi r3,r1,STACK_FRAME_OVERHEAD
325 INTS_RESTORE_HARD
326 bl .kernel_fp_unavailable_exception
327 BUG_OPCODE
328 1: ld r12,_MSR(r1)
329 bl .load_up_fpu
330 b fast_exception_return
332 /* Decrementer Interrupt */
333 MASKABLE_EXCEPTION(0x900, decrementer, .timer_interrupt, ACK_DEC)
335 /* Fixed Interval Timer Interrupt */
336 MASKABLE_EXCEPTION(0x980, fixed_interval, .unknown_exception, ACK_FIT)
338 /* Watchdog Timer Interrupt */
339 START_EXCEPTION(watchdog);
340 CRIT_EXCEPTION_PROLOG(0x9f0, PROLOG_ADDITION_NONE)
341 // EXCEPTION_COMMON(0x9f0, PACA_EXCRIT, INTS_DISABLE_ALL)
342 // bl special_reg_save_crit
343 // addi r3,r1,STACK_FRAME_OVERHEAD
344 // bl .unknown_exception
345 // b ret_from_crit_except
346 b .
348 /* System Call Interrupt */
349 START_EXCEPTION(system_call)
350 mr r9,r13 /* keep a copy of userland r13 */
351 mfspr r11,SPRN_SRR0 /* get return address */
352 mfspr r12,SPRN_SRR1 /* get previous MSR */
353 mfspr r13,SPRN_SPRG_PACA /* get our PACA */
354 b system_call_common
356 /* Auxillary Processor Unavailable Interrupt */
357 START_EXCEPTION(ap_unavailable);
358 NORMAL_EXCEPTION_PROLOG(0xf20, PROLOG_ADDITION_NONE)
359 EXCEPTION_COMMON(0xf20, PACA_EXGEN, INTS_KEEP)
360 addi r3,r1,STACK_FRAME_OVERHEAD
361 bl .save_nvgprs
362 INTS_RESTORE_HARD
363 bl .unknown_exception
364 b .ret_from_except
366 /* Debug exception as a critical interrupt*/
367 START_EXCEPTION(debug_crit);
368 CRIT_EXCEPTION_PROLOG(0xd00, PROLOG_ADDITION_2REGS)
370 /*
371 * If there is a single step or branch-taken exception in an
372 * exception entry sequence, it was probably meant to apply to
373 * the code where the exception occurred (since exception entry
374 * doesn't turn off DE automatically). We simulate the effect
375 * of turning off DE on entry to an exception handler by turning
376 * off DE in the CSRR1 value and clearing the debug status.
377 */
379 mfspr r14,SPRN_DBSR /* check single-step/branch taken */
380 andis. r15,r14,DBSR_IC@h
381 beq+ 1f
383 LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)
384 LOAD_REG_IMMEDIATE(r15,interrupt_end_book3e)
385 cmpld cr0,r10,r14
386 cmpld cr1,r10,r15
387 blt+ cr0,1f
388 bge+ cr1,1f
390 /* here it looks like we got an inappropriate debug exception. */
391 lis r14,DBSR_IC@h /* clear the IC event */
392 rlwinm r11,r11,0,~MSR_DE /* clear DE in the CSRR1 value */
393 mtspr SPRN_DBSR,r14
394 mtspr SPRN_CSRR1,r11
395 lwz r10,PACA_EXCRIT+EX_CR(r13) /* restore registers */
396 ld r1,PACA_EXCRIT+EX_R1(r13)
397 ld r14,PACA_EXCRIT+EX_R14(r13)
398 ld r15,PACA_EXCRIT+EX_R15(r13)
399 mtcr r10
400 ld r10,PACA_EXCRIT+EX_R10(r13) /* restore registers */
401 ld r11,PACA_EXCRIT+EX_R11(r13)
402 mfspr r13,SPRN_SPRG_CRIT_SCRATCH
403 rfci
405 /* Normal debug exception */
406 /* XXX We only handle coming from userspace for now since we can't
407 * quite save properly an interrupted kernel state yet
408 */
409 1: andi. r14,r11,MSR_PR; /* check for userspace again */
410 beq kernel_dbg_exc; /* if from kernel mode */
412 /* Now we mash up things to make it look like we are coming on a
413 * normal exception
414 */
415 mfspr r15,SPRN_SPRG_CRIT_SCRATCH
416 mtspr SPRN_SPRG_GEN_SCRATCH,r15
417 mfspr r14,SPRN_DBSR
418 EXCEPTION_COMMON(0xd00, PACA_EXCRIT, INTS_DISABLE_ALL)
419 std r14,_DSISR(r1)
420 addi r3,r1,STACK_FRAME_OVERHEAD
421 mr r4,r14
422 ld r14,PACA_EXCRIT+EX_R14(r13)
423 ld r15,PACA_EXCRIT+EX_R15(r13)
424 bl .save_nvgprs
425 bl .DebugException
426 b .ret_from_except
428 kernel_dbg_exc:
429 b . /* NYI */
432 /*
433 * An interrupt came in while soft-disabled; clear EE in SRR1,
434 * clear paca->hard_enabled and return.
435 */
436 masked_interrupt_book3e:
437 mtcr r10
438 stb r11,PACAHARDIRQEN(r13)
439 mfspr r10,SPRN_SRR1
440 rldicl r11,r10,48,1 /* clear MSR_EE */
441 rotldi r10,r11,16
442 mtspr SPRN_SRR1,r10
443 ld r10,PACA_EXGEN+EX_R10(r13); /* restore registers */
444 ld r11,PACA_EXGEN+EX_R11(r13);
445 mfspr r13,SPRN_SPRG_GEN_SCRATCH;
446 rfi
447 b .
449 /*
450 * This is called from 0x300 and 0x400 handlers after the prologs with
451 * r14 and r15 containing the fault address and error code, with the
452 * original values stashed away in the PACA
453 */
454 storage_fault_common:
455 std r14,_DAR(r1)
456 std r15,_DSISR(r1)
457 addi r3,r1,STACK_FRAME_OVERHEAD
458 mr r4,r14
459 mr r5,r15
460 ld r14,PACA_EXGEN+EX_R14(r13)
461 ld r15,PACA_EXGEN+EX_R15(r13)
462 INTS_RESTORE_HARD
463 bl .do_page_fault
464 cmpdi r3,0
465 bne- 1f
466 b .ret_from_except_lite
467 1: bl .save_nvgprs
468 mr r5,r3
469 addi r3,r1,STACK_FRAME_OVERHEAD
470 ld r4,_DAR(r1)
471 bl .bad_page_fault
472 b .ret_from_except
474 /*
475 * Alignment exception doesn't fit entirely in the 0x100 bytes so it
476 * continues here.
477 */
478 alignment_more:
479 std r14,_DAR(r1)
480 std r15,_DSISR(r1)
481 addi r3,r1,STACK_FRAME_OVERHEAD
482 ld r14,PACA_EXGEN+EX_R14(r13)
483 ld r15,PACA_EXGEN+EX_R15(r13)
484 bl .save_nvgprs
485 INTS_RESTORE_HARD
486 bl .alignment_exception
487 b .ret_from_except
489 /*
490 * We branch here from entry_64.S for the last stage of the exception
491 * return code path. MSR:EE is expected to be off at that point
492 */
493 _GLOBAL(exception_return_book3e)
494 b 1f
496 /* This is the return from load_up_fpu fast path which could do with
497 * less GPR restores in fact, but for now we have a single return path
498 */
499 .globl fast_exception_return
500 fast_exception_return:
501 wrteei 0
502 1: mr r0,r13
503 ld r10,_MSR(r1)
504 REST_4GPRS(2, r1)
505 andi. r6,r10,MSR_PR
506 REST_2GPRS(6, r1)
507 beq 1f
508 ACCOUNT_CPU_USER_EXIT(r10, r11)
509 ld r0,GPR13(r1)
511 1: stdcx. r0,0,r1 /* to clear the reservation */
513 ld r8,_CCR(r1)
514 ld r9,_LINK(r1)
515 ld r10,_CTR(r1)
516 ld r11,_XER(r1)
517 mtcr r8
518 mtlr r9
519 mtctr r10
520 mtxer r11
521 REST_2GPRS(8, r1)
522 ld r10,GPR10(r1)
523 ld r11,GPR11(r1)
524 ld r12,GPR12(r1)
525 mtspr SPRN_SPRG_GEN_SCRATCH,r0
527 std r10,PACA_EXGEN+EX_R10(r13);
528 std r11,PACA_EXGEN+EX_R11(r13);
529 ld r10,_NIP(r1)
530 ld r11,_MSR(r1)
531 ld r0,GPR0(r1)
532 ld r1,GPR1(r1)
533 mtspr SPRN_SRR0,r10
534 mtspr SPRN_SRR1,r11
535 ld r10,PACA_EXGEN+EX_R10(r13)
536 ld r11,PACA_EXGEN+EX_R11(r13)
537 mfspr r13,SPRN_SPRG_GEN_SCRATCH
538 rfi
540 /*
541 * Trampolines used when spotting a bad kernel stack pointer in
542 * the exception entry code.
543 *
544 * TODO: move some bits like SRR0 read to trampoline, pass PACA
545 * index around, etc... to handle crit & mcheck
546 */
547 BAD_STACK_TRAMPOLINE(0x000)
548 BAD_STACK_TRAMPOLINE(0x100)
549 BAD_STACK_TRAMPOLINE(0x200)
550 BAD_STACK_TRAMPOLINE(0x300)
551 BAD_STACK_TRAMPOLINE(0x400)
552 BAD_STACK_TRAMPOLINE(0x500)
553 BAD_STACK_TRAMPOLINE(0x600)
554 BAD_STACK_TRAMPOLINE(0x700)
555 BAD_STACK_TRAMPOLINE(0x800)
556 BAD_STACK_TRAMPOLINE(0x900)
557 BAD_STACK_TRAMPOLINE(0x980)
558 BAD_STACK_TRAMPOLINE(0x9f0)
559 BAD_STACK_TRAMPOLINE(0xa00)
560 BAD_STACK_TRAMPOLINE(0xb00)
561 BAD_STACK_TRAMPOLINE(0xc00)
562 BAD_STACK_TRAMPOLINE(0xd00)
563 BAD_STACK_TRAMPOLINE(0xe00)
564 BAD_STACK_TRAMPOLINE(0xf00)
565 BAD_STACK_TRAMPOLINE(0xf20)
567 .globl bad_stack_book3e
568 bad_stack_book3e:
569 /* XXX: Needs to make SPRN_SPRG_GEN depend on exception type */
570 mfspr r10,SPRN_SRR0; /* read SRR0 before touching stack */
571 ld r1,PACAEMERGSP(r13)
572 subi r1,r1,64+INT_FRAME_SIZE
573 std r10,_NIP(r1)
574 std r11,_MSR(r1)
575 ld r10,PACA_EXGEN+EX_R1(r13) /* FIXME for crit & mcheck */
576 lwz r11,PACA_EXGEN+EX_CR(r13) /* FIXME for crit & mcheck */
577 std r10,GPR1(r1)
578 std r11,_CCR(r1)
579 mfspr r10,SPRN_DEAR
580 mfspr r11,SPRN_ESR
581 std r10,_DAR(r1)
582 std r11,_DSISR(r1)
583 std r0,GPR0(r1); /* save r0 in stackframe */ \
584 std r2,GPR2(r1); /* save r2 in stackframe */ \
585 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
586 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
587 std r9,GPR9(r1); /* save r9 in stackframe */ \
588 ld r3,PACA_EXGEN+EX_R10(r13);/* get back r10 */ \
589 ld r4,PACA_EXGEN+EX_R11(r13);/* get back r11 */ \
590 mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 XXX can be wrong */ \
591 std r3,GPR10(r1); /* save r10 to stackframe */ \
592 std r4,GPR11(r1); /* save r11 to stackframe */ \
593 std r12,GPR12(r1); /* save r12 in stackframe */ \
594 std r5,GPR13(r1); /* save it to stackframe */ \
595 mflr r10
596 mfctr r11
597 mfxer r12
598 std r10,_LINK(r1)
599 std r11,_CTR(r1)
600 std r12,_XER(r1)
601 SAVE_10GPRS(14,r1)
602 SAVE_8GPRS(24,r1)
603 lhz r12,PACA_TRAP_SAVE(r13)
604 std r12,_TRAP(r1)
605 addi r11,r1,INT_FRAME_SIZE
606 std r11,0(r1)
607 li r12,0
608 std r12,0(r11)
609 ld r2,PACATOC(r13)
610 1: addi r3,r1,STACK_FRAME_OVERHEAD
611 bl .kernel_bad_stack
612 b 1b
614 /*
615 * Setup the initial TLB for a core. This current implementation
616 * assume that whatever we are running off will not conflict with
617 * the new mapping at PAGE_OFFSET.
618 */
619 _GLOBAL(initial_tlb_book3e)
621 /* Look for the first TLB with IPROT set */
622 mfspr r4,SPRN_TLB0CFG
623 andi. r3,r4,TLBnCFG_IPROT
624 lis r3,MAS0_TLBSEL(0)@h
625 bne found_iprot
627 mfspr r4,SPRN_TLB1CFG
628 andi. r3,r4,TLBnCFG_IPROT
629 lis r3,MAS0_TLBSEL(1)@h
630 bne found_iprot
632 mfspr r4,SPRN_TLB2CFG
633 andi. r3,r4,TLBnCFG_IPROT
634 lis r3,MAS0_TLBSEL(2)@h
635 bne found_iprot
637 lis r3,MAS0_TLBSEL(3)@h
638 mfspr r4,SPRN_TLB3CFG
639 /* fall through */
641 found_iprot:
642 andi. r5,r4,TLBnCFG_HES
643 bne have_hes
645 mflr r8 /* save LR */
646 /* 1. Find the index of the entry we're executing in
647 *
648 * r3 = MAS0_TLBSEL (for the iprot array)
649 * r4 = SPRN_TLBnCFG
650 */
651 bl invstr /* Find our address */
652 invstr: mflr r6 /* Make it accessible */
653 mfmsr r7
654 rlwinm r5,r7,27,31,31 /* extract MSR[IS] */
655 mfspr r7,SPRN_PID
656 slwi r7,r7,16
657 or r7,r7,r5
658 mtspr SPRN_MAS6,r7
659 tlbsx 0,r6 /* search MSR[IS], SPID=PID */
661 mfspr r3,SPRN_MAS0
662 rlwinm r5,r3,16,20,31 /* Extract MAS0(Entry) */
664 mfspr r7,SPRN_MAS1 /* Insure IPROT set */
665 oris r7,r7,MAS1_IPROT@h
666 mtspr SPRN_MAS1,r7
667 tlbwe
669 /* 2. Invalidate all entries except the entry we're executing in
670 *
671 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
672 * r4 = SPRN_TLBnCFG
673 * r5 = ESEL of entry we are running in
674 */
675 andi. r4,r4,TLBnCFG_N_ENTRY /* Extract # entries */
676 li r6,0 /* Set Entry counter to 0 */
677 1: mr r7,r3 /* Set MAS0(TLBSEL) */
678 rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
679 mtspr SPRN_MAS0,r7
680 tlbre
681 mfspr r7,SPRN_MAS1
682 rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */
683 cmpw r5,r6
684 beq skpinv /* Dont update the current execution TLB */
685 mtspr SPRN_MAS1,r7
686 tlbwe
687 isync
688 skpinv: addi r6,r6,1 /* Increment */
689 cmpw r6,r4 /* Are we done? */
690 bne 1b /* If not, repeat */
692 /* Invalidate all TLBs */
693 PPC_TLBILX_ALL(0,0)
694 sync
695 isync
697 /* 3. Setup a temp mapping and jump to it
698 *
699 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
700 * r5 = ESEL of entry we are running in
701 */
702 andi. r7,r5,0x1 /* Find an entry not used and is non-zero */
703 addi r7,r7,0x1
704 mr r4,r3 /* Set MAS0(TLBSEL) = 1 */
705 mtspr SPRN_MAS0,r4
706 tlbre
708 rlwimi r4,r7,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r7) */
709 mtspr SPRN_MAS0,r4
711 mfspr r7,SPRN_MAS1
712 xori r6,r7,MAS1_TS /* Setup TMP mapping in the other Address space */
713 mtspr SPRN_MAS1,r6
715 tlbwe
717 mfmsr r6
718 xori r6,r6,MSR_IS
719 mtspr SPRN_SRR1,r6
720 bl 1f /* Find our address */
721 1: mflr r6
722 addi r6,r6,(2f - 1b)
723 mtspr SPRN_SRR0,r6
724 rfi
725 2:
727 /* 4. Clear out PIDs & Search info
728 *
729 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
730 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
731 * r5 = MAS3
732 */
733 li r6,0
734 mtspr SPRN_MAS6,r6
735 mtspr SPRN_PID,r6
737 /* 5. Invalidate mapping we started in
738 *
739 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
740 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
741 * r5 = MAS3
742 */
743 mtspr SPRN_MAS0,r3
744 tlbre
745 mfspr r6,SPRN_MAS1
746 rlwinm r6,r6,0,2,0 /* clear IPROT */
747 mtspr SPRN_MAS1,r6
748 tlbwe
750 /* Invalidate TLB1 */
751 PPC_TLBILX_ALL(0,0)
752 sync
753 isync
755 /* The mapping only needs to be cache-coherent on SMP */
756 #ifdef CONFIG_SMP
757 #define M_IF_SMP MAS2_M
758 #else
759 #define M_IF_SMP 0
760 #endif
762 /* 6. Setup KERNELBASE mapping in TLB[0]
763 *
764 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
765 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
766 * r5 = MAS3
767 */
768 rlwinm r3,r3,0,16,3 /* clear ESEL */
769 mtspr SPRN_MAS0,r3
770 lis r6,(MAS1_VALID|MAS1_IPROT)@h
771 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l
772 mtspr SPRN_MAS1,r6
774 LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET | M_IF_SMP)
775 mtspr SPRN_MAS2,r6
777 rlwinm r5,r5,0,0,25
778 ori r5,r5,MAS3_SR | MAS3_SW | MAS3_SX
779 mtspr SPRN_MAS3,r5
780 li r5,-1
781 rlwinm r5,r5,0,0,25
783 tlbwe
785 /* 7. Jump to KERNELBASE mapping
786 *
787 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
788 */
789 /* Now we branch the new virtual address mapped by this entry */
790 LOAD_REG_IMMEDIATE(r6,2f)
791 lis r7,MSR_KERNEL@h
792 ori r7,r7,MSR_KERNEL@l
793 mtspr SPRN_SRR0,r6
794 mtspr SPRN_SRR1,r7
795 rfi /* start execution out of TLB1[0] entry */
796 2:
798 /* 8. Clear out the temp mapping
799 *
800 * r4 = MAS0 w/TLBSEL & ESEL for the entry we are running in
801 */
802 mtspr SPRN_MAS0,r4
803 tlbre
804 mfspr r5,SPRN_MAS1
805 rlwinm r5,r5,0,2,0 /* clear IPROT */
806 mtspr SPRN_MAS1,r5
807 tlbwe
809 /* Invalidate TLB1 */
810 PPC_TLBILX_ALL(0,0)
811 sync
812 isync
814 /* We translate LR and return */
815 tovirt(r8,r8)
816 mtlr r8
817 blr
819 have_hes:
820 /* Setup MAS 0,1,2,3 and 7 for tlbwe of a 1G entry that maps the
821 * kernel linear mapping. We also set MAS8 once for all here though
822 * that will have to be made dependent on whether we are running under
823 * a hypervisor I suppose.
824 */
825 ori r3,r3,MAS0_HES | MAS0_WQ_ALLWAYS
826 mtspr SPRN_MAS0,r3
827 lis r3,(MAS1_VALID | MAS1_IPROT)@h
828 ori r3,r3,BOOK3E_PAGESZ_1GB << MAS1_TSIZE_SHIFT
829 mtspr SPRN_MAS1,r3
830 LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET | MAS2_M)
831 mtspr SPRN_MAS2,r3
832 li r3,MAS3_SR | MAS3_SW | MAS3_SX
833 mtspr SPRN_MAS7_MAS3,r3
834 li r3,0
835 mtspr SPRN_MAS8,r3
837 /* Write the TLB entry */
838 tlbwe
840 /* Now we branch the new virtual address mapped by this entry */
841 LOAD_REG_IMMEDIATE(r3,1f)
842 mtctr r3
843 bctr
845 1: /* We are now running at PAGE_OFFSET, clean the TLB of everything
846 * else (XXX we should scan for bolted crap from the firmware too)
847 */
848 PPC_TLBILX(0,0,0)
849 sync
850 isync
852 /* We translate LR and return */
853 mflr r3
854 tovirt(r3,r3)
855 mtlr r3
856 blr
858 /*
859 * Main entry (boot CPU, thread 0)
860 *
861 * We enter here from head_64.S, possibly after the prom_init trampoline
862 * with r3 and r4 already saved to r31 and 30 respectively and in 64 bits
863 * mode. Anything else is as it was left by the bootloader
864 *
865 * Initial requirements of this port:
866 *
867 * - Kernel loaded at 0 physical
868 * - A good lump of memory mapped 0:0 by UTLB entry 0
869 * - MSR:IS & MSR:DS set to 0
870 *
871 * Note that some of the above requirements will be relaxed in the future
872 * as the kernel becomes smarter at dealing with different initial conditions
873 * but for now you have to be careful
874 */
875 _GLOBAL(start_initialization_book3e)
876 mflr r28
878 /* First, we need to setup some initial TLBs to map the kernel
879 * text, data and bss at PAGE_OFFSET. We don't have a real mode
880 * and always use AS 0, so we just set it up to match our link
881 * address and never use 0 based addresses.
882 */
883 bl .initial_tlb_book3e
885 /* Init global core bits */
886 bl .init_core_book3e
888 /* Init per-thread bits */
889 bl .init_thread_book3e
891 /* Return to common init code */
892 tovirt(r28,r28)
893 mtlr r28
894 blr
897 /*
898 * Secondary core/processor entry
899 *
900 * This is entered for thread 0 of a secondary core, all other threads
901 * are expected to be stopped. It's similar to start_initialization_book3e
902 * except that it's generally entered from the holding loop in head_64.S
903 * after CPUs have been gathered by Open Firmware.
904 *
905 * We assume we are in 32 bits mode running with whatever TLB entry was
906 * set for us by the firmware or POR engine.
907 */
908 _GLOBAL(book3e_secondary_core_init_tlb_set)
909 li r4,1
910 b .generic_secondary_smp_init
912 _GLOBAL(book3e_secondary_core_init)
913 mflr r28
915 /* Do we need to setup initial TLB entry ? */
916 cmplwi r4,0
917 bne 2f
919 /* Setup TLB for this core */
920 bl .initial_tlb_book3e
922 /* We can return from the above running at a different
923 * address, so recalculate r2 (TOC)
924 */
925 bl .relative_toc
927 /* Init global core bits */
928 2: bl .init_core_book3e
930 /* Init per-thread bits */
931 3: bl .init_thread_book3e
933 /* Return to common init code at proper virtual address.
934 *
935 * Due to various previous assumptions, we know we entered this
936 * function at either the final PAGE_OFFSET mapping or using a
937 * 1:1 mapping at 0, so we don't bother doing a complicated check
938 * here, we just ensure the return address has the right top bits.
939 *
940 * Note that if we ever want to be smarter about where we can be
941 * started from, we have to be careful that by the time we reach
942 * the code below we may already be running at a different location
943 * than the one we were called from since initial_tlb_book3e can
944 * have moved us already.
945 */
946 cmpdi cr0,r28,0
947 blt 1f
948 lis r3,PAGE_OFFSET@highest
949 sldi r3,r3,32
950 or r28,r28,r3
951 1: mtlr r28
952 blr
954 _GLOBAL(book3e_secondary_thread_init)
955 mflr r28
956 b 3b
958 _STATIC(init_core_book3e)
959 /* Establish the interrupt vector base */
960 LOAD_REG_IMMEDIATE(r3, interrupt_base_book3e)
961 mtspr SPRN_IVPR,r3
962 sync
963 blr
965 _STATIC(init_thread_book3e)
966 lis r3,(SPRN_EPCR_ICM | SPRN_EPCR_GICM)@h
967 mtspr SPRN_EPCR,r3
969 /* Make sure interrupts are off */
970 wrteei 0
972 /* disable all timers and clear out status */
973 li r3,0
974 mtspr SPRN_TCR,r3
975 mfspr r3,SPRN_TSR
976 mtspr SPRN_TSR,r3
978 blr
980 _GLOBAL(__setup_base_ivors)
981 SET_IVOR(0, 0x020) /* Critical Input */
982 SET_IVOR(1, 0x000) /* Machine Check */
983 SET_IVOR(2, 0x060) /* Data Storage */
984 SET_IVOR(3, 0x080) /* Instruction Storage */
985 SET_IVOR(4, 0x0a0) /* External Input */
986 SET_IVOR(5, 0x0c0) /* Alignment */
987 SET_IVOR(6, 0x0e0) /* Program */
988 SET_IVOR(7, 0x100) /* FP Unavailable */
989 SET_IVOR(8, 0x120) /* System Call */
990 SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */
991 SET_IVOR(10, 0x160) /* Decrementer */
992 SET_IVOR(11, 0x180) /* Fixed Interval Timer */
993 SET_IVOR(12, 0x1a0) /* Watchdog Timer */
994 SET_IVOR(13, 0x1c0) /* Data TLB Error */
995 SET_IVOR(14, 0x1e0) /* Instruction TLB Error */
996 SET_IVOR(15, 0x040) /* Debug */
998 sync
1000 blr