arch/powerpc/platforms/86xx/gef_ppc9a.c

   1 /*
   2  * GE Fanuc PPC9A board support
   3  *
   4  * Author: Martyn Welch <martyn.welch@gefanuc.com>
   5  *
   6  * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  * Based on: mpc86xx_hpcn.c (MPC86xx HPCN board specific routines)
  14  * Copyright 2006 Freescale Semiconductor Inc.
  15  *
  16  * NEC fixup adapted from arch/mips/pci/fixup-lm2e.c
  17  */
  18
  19 #include <linux/stddef.h>
  20 #include <linux/kernel.h>
  21 #include <linux/pci.h>
  22 #include <linux/kdev_t.h>
  23 #include <linux/delay.h>
  24 #include <linux/seq_file.h>
  25 #include <linux/of_platform.h>
  26
  27 #include <asm/system.h>
  28 #include <asm/time.h>
  29 #include <asm/machdep.h>
  30 #include <asm/pci-bridge.h>
  31 #include <asm/prom.h>
  32 #include <mm/mmu_decl.h>
  33 #include <asm/udbg.h>
  34
  35 #include <asm/mpic.h>
  36
  37 #include <sysdev/fsl_pci.h>
  38 #include <sysdev/fsl_soc.h>
  39
  40 #include "mpc86xx.h"
  41 #include "gef_pic.h"
  42
  43 #undef DEBUG
  44
  45 #ifdef DEBUG
  46 #define DBG (fmt...) do { printk(KERN_ERR "PPC9A: " fmt); } while (0)
  47 #else
  48 #define DBG (fmt...) do { } while (0)
  49 #endif
  50
  51 void __iomem *ppc9a_regs;
  52
  53 static void __init gef_ppc9a_init_irq(void)
  54 {
  55         struct device_node *cascade_node = NULL;
  56
  57         mpc86xx_init_irq();
  58
  59         /*
  60          * There is a simple interrupt handler in the main FPGA, this needs
  61          * to be cascaded into the MPIC
  62          */
  63         cascade_node = of_find_compatible_node(NULL, NULL, "gef,fpga-pic-1.00");
  64         if (!cascade_node) {
  65                 printk(KERN_WARNING "PPC9A: No FPGA PIC\n");
  66                 return;
  67         }
  68
  69         gef_pic_init(cascade_node);
  70         of_node_put(cascade_node);
  71 }
  72
  73 static void __init gef_ppc9a_setup_arch(void)
  74 {
  75         struct device_node *regs;
  76 #ifdef CONFIG_PCI
  77         struct device_node *np;
  78
  79         for_each_compatible_node(np, "pci", "fsl,mpc8641-pcie") {
  80                 fsl_add_bridge(np, 1);
  81         }
  82 #endif
  83
  84         printk(KERN_INFO "GE Fanuc Intelligent Platforms PPC9A 6U VME SBC\n");
  85
  86 #ifdef CONFIG_SMP
  87         mpc86xx_smp_init();
  88 #endif
  89
  90         /* Remap basic board registers */
  91         regs = of_find_compatible_node(NULL, NULL, "gef,ppc9a-fpga-regs");
  92         if (regs) {
  93                 ppc9a_regs = of_iomap(regs, 0);
  94                 if (ppc9a_regs == NULL)
  95                         printk(KERN_WARNING "Unable to map board registers\n");
  96                 of_node_put(regs);
  97         }
  98 }
  99
 100 /* Return the PCB revision */
 101 static unsigned int gef_ppc9a_get_pcb_rev(void)
 102 {
 103         unsigned int reg;
 104
 105         reg = ioread32be(ppc9a_regs);
 106         return (reg >> 16) & 0xff;
 107 }
 108
 109 /* Return the board (software) revision */
 110 static unsigned int gef_ppc9a_get_board_rev(void)
 111 {
 112         unsigned int reg;
 113
 114         reg = ioread32be(ppc9a_regs);
 115         return (reg >> 8) & 0xff;
 116 }
 117
 118 /* Return the FPGA revision */
 119 static unsigned int gef_ppc9a_get_fpga_rev(void)
 120 {
 121         unsigned int reg;
 122
 123         reg = ioread32be(ppc9a_regs);
 124         return reg & 0xf;
 125 }
 126
 127 /* Return VME Geographical Address */
 128 static unsigned int gef_ppc9a_get_vme_geo_addr(void)
 129 {
 130         unsigned int reg;
 131
 132         reg = ioread32be(ppc9a_regs + 0x4);
 133         return reg & 0x1f;
 134 }
 135
 136 /* Return VME System Controller Status */
 137 static unsigned int gef_ppc9a_get_vme_is_syscon(void)
 138 {
 139         unsigned int reg;
 140
 141         reg = ioread32be(ppc9a_regs + 0x4);
 142         return (reg >> 9) & 0x1;
 143 }
 144
 145 static void gef_ppc9a_show_cpuinfo(struct seq_file *m)
 146 {
 147         uint svid = mfspr(SPRN_SVR);
 148
 149         seq_printf(m, "Vendor\t\t: GE Fanuc Intelligent Platforms\n");
 150
 151         seq_printf(m, "Revision\t: %u%c\n", gef_ppc9a_get_pcb_rev(),
 152                 ('A' + gef_ppc9a_get_board_rev()));
 153         seq_printf(m, "FPGA Revision\t: %u\n", gef_ppc9a_get_fpga_rev());
 154
 155         seq_printf(m, "SVR\t\t: 0x%x\n", svid);
 156
 157         seq_printf(m, "VME geo. addr\t: %u\n", gef_ppc9a_get_vme_geo_addr());
 158
 159         seq_printf(m, "VME syscon\t: %s\n",
 160                 gef_ppc9a_get_vme_is_syscon() ? "yes" : "no");
 161 }
 162
 163 static void __init gef_ppc9a_nec_fixup(struct pci_dev *pdev)
 164 {
 165         unsigned int val;
 166
 167         /* Do not do the fixup on other platforms! */
 168         if (!machine_is(gef_ppc9a))
 169                 return;
 170
 171         printk(KERN_INFO "Running NEC uPD720101 Fixup\n");
 172
 173         /* Ensure ports 1, 2, 3, 4 & 5 are enabled */
 174         pci_read_config_dword(pdev, 0xe0, &val);
 175         pci_write_config_dword(pdev, 0xe0, (val & ~7) | 0x5);
 176
 177         /* System clock is 48-MHz Oscillator and EHCI Enabled. */
 178         pci_write_config_dword(pdev, 0xe4, 1 << 5);
 179 }
 180 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB,
 181         gef_ppc9a_nec_fixup);
 182
 183 /*
 184  * Called very early, device-tree isn't unflattened
 185  *
 186  * This function is called to determine whether the BSP is compatible with the
 187  * supplied device-tree, which is assumed to be the correct one for the actual
 188  * board. It is expected thati, in the future, a kernel may support multiple
 189  * boards.
 190  */
 191 static int __init gef_ppc9a_probe(void)
 192 {
 193         unsigned long root = of_get_flat_dt_root();
 194
 195         if (of_flat_dt_is_compatible(root, "gef,ppc9a"))
 196                 return 1;
 197
 198         return 0;
 199 }
 200
 201 static long __init mpc86xx_time_init(void)
 202 {
 203         unsigned int temp;
 204
 205         /* Set the time base to zero */
 206         mtspr(SPRN_TBWL, 0);
 207         mtspr(SPRN_TBWU, 0);
 208
 209         temp = mfspr(SPRN_HID0);
 210         temp |= HID0_TBEN;
 211         mtspr(SPRN_HID0, temp);
 212         asm volatile("isync");
 213
 214         return 0;
 215 }
 216
 217 static __initdata struct of_device_id of_bus_ids[] = {
 218         { .compatible = "simple-bus", },
 219         { .compatible = "gianfar", },
 220         {},
 221 };
 222
 223 static int __init declare_of_platform_devices(void)
 224 {
 225         printk(KERN_DEBUG "Probe platform devices\n");
 226         of_platform_bus_probe(NULL, of_bus_ids, NULL);
 227
 228         return 0;
 229 }
 230 machine_device_initcall(gef_ppc9a, declare_of_platform_devices);
 231
 232 define_machine(gef_ppc9a) {
 233         .name                   = "GE Fanuc PPC9A",
 234         .probe                  = gef_ppc9a_probe,
 235         .setup_arch             = gef_ppc9a_setup_arch,
 236         .init_IRQ               = gef_ppc9a_init_irq,
 237         .show_cpuinfo           = gef_ppc9a_show_cpuinfo,
 238         .get_irq                = mpic_get_irq,
 239         .restart                = fsl_rstcr_restart,
 240         .time_init              = mpc86xx_time_init,
 241         .calibrate_decr         = generic_calibrate_decr,
 242         .progress               = udbg_progress,
 243 #ifdef CONFIG_PCI
 244         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 245 #endif
 246 };