arch/powerpc/platforms/cell/celleb_setup.c

   1 /*
   2  * Celleb setup code
   3  *
   4  * (C) Copyright 2006-2007 TOSHIBA CORPORATION
   5  *
   6  * This code is based on arch/powerpc/platforms/cell/setup.c:
   7  *  Copyright (C) 1995  Linus Torvalds
   8  *  Adapted from 'alpha' version by Gary Thomas
   9  *  Modified by Cort Dougan (cort@cs.nmt.edu)
  10  *  Modified by PPC64 Team, IBM Corp
  11  *  Modified by Cell Team, IBM Deutschland Entwicklung GmbH
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License along
  24  * with this program; if not, write to the Free Software Foundation, Inc.,
  25  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  26  */
  27
  28 #undef DEBUG
  29
  30 #include <linux/cpu.h>
  31 #include <linux/sched.h>
  32 #include <linux/kernel.h>
  33 #include <linux/mm.h>
  34 #include <linux/stddef.h>
  35 #include <linux/unistd.h>
  36 #include <linux/reboot.h>
  37 #include <linux/init.h>
  38 #include <linux/delay.h>
  39 #include <linux/irq.h>
  40 #include <linux/seq_file.h>
  41 #include <linux/root_dev.h>
  42 #include <linux/console.h>
  43 #include <linux/of_platform.h>
  44
  45 #include <asm/mmu.h>
  46 #include <asm/processor.h>
  47 #include <asm/io.h>
  48 #include <asm/prom.h>
  49 #include <asm/machdep.h>
  50 #include <asm/cputable.h>
  51 #include <asm/irq.h>
  52 #include <asm/time.h>
  53 #include <asm/spu_priv1.h>
  54 #include <asm/firmware.h>
  55 #include <asm/rtas.h>
  56 #include <asm/cell-regs.h>
  57
  58 #include "beat_interrupt.h"
  59 #include "beat_wrapper.h"
  60 #include "beat.h"
  61 #include "celleb_pci.h"
  62 #include "interrupt.h"
  63 #include "pervasive.h"
  64 #include "ras.h"
  65
  66 static char celleb_machine_type[128] = "Celleb";
  67
  68 static void celleb_show_cpuinfo(struct seq_file *m)
  69 {
  70         struct device_node *root;
  71         const char *model = "";
  72
  73         root = of_find_node_by_path("/");
  74         if (root)
  75                 model = of_get_property(root, "model", NULL);
  76         /* using "CHRP" is to trick anaconda into installing FCx into Celleb */
  77         seq_printf(m, "machine\t\t: %s %s\n", celleb_machine_type, model);
  78         of_node_put(root);
  79 }
  80
  81 static int __init celleb_machine_type_hack(char *ptr)
  82 {
  83         strlcpy(celleb_machine_type, ptr, sizeof(celleb_machine_type));
  84         return 0;
  85 }
  86
  87 __setup("celleb_machine_type_hack=", celleb_machine_type_hack);
  88
  89 static void celleb_progress(char *s, unsigned short hex)
  90 {
  91         printk("*** %04x : %s\n", hex, s ? s : "");
  92 }
  93
  94 static void __init celleb_setup_arch_common(void)
  95 {
  96         /* init to some ~sane value until calibrate_delay() runs */
  97         loops_per_jiffy = 50000000;
  98
  99 #ifdef CONFIG_DUMMY_CONSOLE
 100         conswitchp = &dummy_con;
 101 #endif
 102 }
 103
 104 static struct of_device_id celleb_bus_ids[] __initdata = {
 105         { .type = "scc", },
 106         { .type = "ioif", },    /* old style */
 107         {},
 108 };
 109
 110 static int __init celleb_publish_devices(void)
 111 {
 112         /* Publish OF platform devices for southbridge IOs */
 113         of_platform_bus_probe(NULL, celleb_bus_ids, NULL);
 114
 115         return 0;
 116 }
 117 machine_device_initcall(celleb_beat, celleb_publish_devices);
 118 machine_device_initcall(celleb_native, celleb_publish_devices);
 119
 120
 121 /*
 122  * functions for Celleb-Beat
 123  */
 124 static void __init celleb_setup_arch_beat(void)
 125 {
 126 #ifdef CONFIG_SPU_BASE
 127         spu_priv1_ops           = &spu_priv1_beat_ops;
 128         spu_management_ops      = &spu_management_of_ops;
 129 #endif
 130
 131 #ifdef CONFIG_SMP
 132         smp_init_celleb();
 133 #endif
 134
 135         celleb_setup_arch_common();
 136 }
 137
 138 static int __init celleb_probe_beat(void)
 139 {
 140         unsigned long root = of_get_flat_dt_root();
 141
 142         if (!of_flat_dt_is_compatible(root, "Beat"))
 143                 return 0;
 144
 145         powerpc_firmware_features |= FW_FEATURE_CELLEB_ALWAYS
 146                 | FW_FEATURE_BEAT | FW_FEATURE_LPAR;
 147         hpte_init_beat_v3();
 148
 149         return 1;
 150 }
 151
 152
 153 /*
 154  * functions for Celleb-native
 155  */
 156 static void __init celleb_init_IRQ_native(void)
 157 {
 158         iic_init_IRQ();
 159         spider_init_IRQ();
 160 }
 161
 162 static void __init celleb_setup_arch_native(void)
 163 {
 164 #ifdef CONFIG_SPU_BASE
 165         spu_priv1_ops           = &spu_priv1_mmio_ops;
 166         spu_management_ops      = &spu_management_of_ops;
 167 #endif
 168
 169         cbe_regs_init();
 170
 171 #ifdef CONFIG_CBE_RAS
 172         cbe_ras_init();
 173 #endif
 174
 175 #ifdef CONFIG_SMP
 176         smp_init_cell();
 177 #endif
 178
 179         cbe_pervasive_init();
 180
 181         /* XXX: nvram initialization should be added */
 182
 183         celleb_setup_arch_common();
 184 }
 185
 186 static int __init celleb_probe_native(void)
 187 {
 188         unsigned long root = of_get_flat_dt_root();
 189
 190         if (of_flat_dt_is_compatible(root, "Beat") ||
 191             !of_flat_dt_is_compatible(root, "TOSHIBA,Celleb"))
 192                 return 0;
 193
 194         powerpc_firmware_features |= FW_FEATURE_CELLEB_ALWAYS;
 195         hpte_init_native();
 196
 197         return 1;
 198 }
 199
 200
 201 /*
 202  * machine definitions
 203  */
 204 define_machine(celleb_beat) {
 205         .name                   = "Cell Reference Set (Beat)",
 206         .probe                  = celleb_probe_beat,
 207         .setup_arch             = celleb_setup_arch_beat,
 208         .show_cpuinfo           = celleb_show_cpuinfo,
 209         .restart                = beat_restart,
 210         .power_off              = beat_power_off,
 211         .halt                   = beat_halt,
 212         .get_rtc_time           = beat_get_rtc_time,
 213         .set_rtc_time           = beat_set_rtc_time,
 214         .calibrate_decr         = generic_calibrate_decr,
 215         .progress               = celleb_progress,
 216         .power_save             = beat_power_save,
 217         .nvram_size             = beat_nvram_get_size,
 218         .nvram_read             = beat_nvram_read,
 219         .nvram_write            = beat_nvram_write,
 220         .set_dabr               = beat_set_xdabr,
 221         .init_IRQ               = beatic_init_IRQ,
 222         .get_irq                = beatic_get_irq,
 223         .pci_probe_mode         = celleb_pci_probe_mode,
 224         .pci_setup_phb          = celleb_setup_phb,
 225 #ifdef CONFIG_KEXEC
 226         .kexec_cpu_down         = beat_kexec_cpu_down,
 227 #endif
 228 };
 229
 230 define_machine(celleb_native) {
 231         .name                   = "Cell Reference Set (native)",
 232         .probe                  = celleb_probe_native,
 233         .setup_arch             = celleb_setup_arch_native,
 234         .show_cpuinfo           = celleb_show_cpuinfo,
 235         .restart                = rtas_restart,
 236         .power_off              = rtas_power_off,
 237         .halt                   = rtas_halt,
 238         .get_boot_time          = rtas_get_boot_time,
 239         .get_rtc_time           = rtas_get_rtc_time,
 240         .set_rtc_time           = rtas_set_rtc_time,
 241         .calibrate_decr         = generic_calibrate_decr,
 242         .progress               = celleb_progress,
 243         .pci_probe_mode         = celleb_pci_probe_mode,
 244         .pci_setup_phb          = celleb_setup_phb,
 245         .init_IRQ               = celleb_init_IRQ_native,
 246 };