arch/powerpc/platforms/iseries/exception.S

   1 /*
   2  *  Low level routines for legacy iSeries support.
   3  *
   4  *  Extracted from head_64.S
   5  *
   6  *  PowerPC version
   7  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
   8  *
   9  *  Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
  10  *    Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
  11  *  Adapted for Power Macintosh by Paul Mackerras.
  12  *  Low-level exception handlers and MMU support
  13  *  rewritten by Paul Mackerras.
  14  *    Copyright (C) 1996 Paul Mackerras.
  15  *
  16  *  Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
  17  *    Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
  18  *
  19  *  This file contains the low-level support and setup for the
  20  *  PowerPC-64 platform, including trap and interrupt dispatch.
  21  *
  22  *  This program is free software; you can redistribute it and/or
  23  *  modify it under the terms of the GNU General Public License
  24  *  as published by the Free Software Foundation; either version
  25  *  2 of the License, or (at your option) any later version.
  26  */
  27
  28 #include <asm/reg.h>
  29 #include <asm/ppc_asm.h>
  30 #include <asm/asm-offsets.h>
  31 #include <asm/thread_info.h>
  32 #include <asm/ptrace.h>
  33 #include <asm/cputable.h>
  34
  35 #include "exception.h"
  36
  37         .text
  38
  39         .globl system_reset_iSeries
  40 system_reset_iSeries:
  41         bl      .relative_toc
  42         mfspr   r13,SPRN_SPRG3          /* Get alpaca address */
  43         LOAD_REG_ADDR(r23, alpaca)
  44         li      r0,ALPACA_SIZE
  45         sub     r23,r13,r23
  46         divdu   r23,r23,r0              /* r23 has cpu number */
  47         LOAD_REG_ADDR(r13, paca)
  48         mulli   r0,r23,PACA_SIZE
  49         add     r13,r13,r0
  50         mtspr   SPRN_SPRG_PACA,r13      /* Save it away for the future */
  51         mfmsr   r24
  52         ori     r24,r24,MSR_RI
  53         mtmsrd  r24                     /* RI on */
  54         mr      r24,r23
  55         cmpwi   0,r24,0                 /* Are we processor 0? */
  56         bne     1f
  57         b       .__start_initialization_iSeries /* Start up the first processor */
  58 1:      mfspr   r4,SPRN_CTRLF
  59         li      r5,CTRL_RUNLATCH        /* Turn off the run light */
  60         andc    r4,r4,r5
  61         mtspr   SPRN_CTRLT,r4
  62
  63 /* Spin on __secondary_hold_spinloop until it is updated by the boot cpu. */
  64 /* In the UP case we'll yield() later, and we will not access the paca anyway */
  65 #ifdef CONFIG_SMP
  66 1:
  67         HMT_LOW
  68         LOAD_REG_ADDR(r23, __secondary_hold_spinloop)
  69         ld      r23,0(r23)
  70         sync
  71         LOAD_REG_ADDR(r3,current_set)
  72         sldi    r28,r24,3               /* get current_set[cpu#] */
  73         ldx     r3,r3,r28
  74         addi    r1,r3,THREAD_SIZE
  75         subi    r1,r1,STACK_FRAME_OVERHEAD
  76
  77         cmpwi   0,r23,0                 /* Keep poking the Hypervisor until */
  78         bne     2f                      /* we're released */
  79         /* Let the Hypervisor know we are alive */
  80         /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */
  81         lis     r3,0x8002
  82         rldicr  r3,r3,32,15             /* r0 = (r3 << 32) & 0xffff000000000000 */
  83         li      r0,-1                   /* r0=-1 indicates a Hypervisor call */
  84         sc                              /* Invoke the hypervisor via a system call */
  85         b       1b
  86 #endif
  87
  88 2:
  89         HMT_LOW
  90 #ifdef CONFIG_SMP
  91         lbz     r23,PACAPROCSTART(r13)  /* Test if this processor
  92                                          * should start */
  93         sync
  94         LOAD_REG_ADDR(r3,current_set)
  95         sldi    r28,r24,3               /* get current_set[cpu#] */
  96         ldx     r3,r3,r28
  97         addi    r1,r3,THREAD_SIZE
  98         subi    r1,r1,STACK_FRAME_OVERHEAD
  99
 100         cmpwi   0,r23,0
 101         beq     iSeries_secondary_smp_loop      /* Loop until told to go */
 102         b       __secondary_start               /* Loop until told to go */
 103 iSeries_secondary_smp_loop:
 104         /* Let the Hypervisor know we are alive */
 105         /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */
 106         lis     r3,0x8002
 107         rldicr  r3,r3,32,15             /* r0 = (r3 << 32) & 0xffff000000000000 */
 108 #else /* CONFIG_SMP */
 109         /* Yield the processor.  This is required for non-SMP kernels
 110                 which are running on multi-threaded machines. */
 111         lis     r3,0x8000
 112         rldicr  r3,r3,32,15             /* r3 = (r3 << 32) & 0xffff000000000000 */
 113         addi    r3,r3,18                /* r3 = 0x8000000000000012 which is "yield" */
 114         li      r4,0                    /* "yield timed" */
 115         li      r5,-1                   /* "yield forever" */
 116 #endif /* CONFIG_SMP */
 117         li      r0,-1                   /* r0=-1 indicates a Hypervisor call */
 118         sc                              /* Invoke the hypervisor via a system call */
 119         mfspr   r13,SPRN_SPRG_PACA      /* Put r13 back ???? */
 120         b       2b                      /* If SMP not configured, secondaries
 121                                          * loop forever */
 122
 123 /***  ISeries-LPAR interrupt handlers ***/
 124
 125         STD_EXCEPTION_ISERIES(machine_check, PACA_EXMC)
 126
 127         .globl data_access_iSeries
 128 data_access_iSeries:
 129         mtspr   SPRN_SPRG_SCRATCH0,r13
 130 BEGIN_FTR_SECTION
 131         mfspr   r13,SPRN_SPRG_PACA
 132         std     r9,PACA_EXSLB+EX_R9(r13)
 133         std     r10,PACA_EXSLB+EX_R10(r13)
 134         mfspr   r10,SPRN_DAR
 135         mfspr   r9,SPRN_DSISR
 136         srdi    r10,r10,60
 137         rlwimi  r10,r9,16,0x20
 138         mfcr    r9
 139         cmpwi   r10,0x2c
 140         beq     .do_stab_bolted_iSeries
 141         ld      r10,PACA_EXSLB+EX_R10(r13)
 142         std     r11,PACA_EXGEN+EX_R11(r13)
 143         ld      r11,PACA_EXSLB+EX_R9(r13)
 144         std     r12,PACA_EXGEN+EX_R12(r13)
 145         mfspr   r12,SPRN_SPRG_SCRATCH0
 146         std     r10,PACA_EXGEN+EX_R10(r13)
 147         std     r11,PACA_EXGEN+EX_R9(r13)
 148         std     r12,PACA_EXGEN+EX_R13(r13)
 149         EXCEPTION_PROLOG_ISERIES_1
 150 FTR_SECTION_ELSE
 151         EXCEPTION_PROLOG_1(PACA_EXGEN)
 152         EXCEPTION_PROLOG_ISERIES_1
 153 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_SLB)
 154         b       data_access_common
 155
 156 .do_stab_bolted_iSeries:
 157         std     r11,PACA_EXSLB+EX_R11(r13)
 158         std     r12,PACA_EXSLB+EX_R12(r13)
 159         mfspr   r10,SPRN_SPRG_SCRATCH0
 160         std     r10,PACA_EXSLB+EX_R13(r13)
 161         EXCEPTION_PROLOG_ISERIES_1
 162         b       .do_stab_bolted
 163
 164         .globl  data_access_slb_iSeries
 165 data_access_slb_iSeries:
 166         mtspr   SPRN_SPRG_SCRATCH0,r13  /* save r13 */
 167         mfspr   r13,SPRN_SPRG_PACA      /* get paca address into r13 */
 168         std     r3,PACA_EXSLB+EX_R3(r13)
 169         mfspr   r3,SPRN_DAR
 170         std     r9,PACA_EXSLB+EX_R9(r13)
 171         mfcr    r9
 172 #ifdef __DISABLED__
 173         cmpdi   r3,0
 174         bge     slb_miss_user_iseries
 175 #endif
 176         std     r10,PACA_EXSLB+EX_R10(r13)
 177         std     r11,PACA_EXSLB+EX_R11(r13)
 178         std     r12,PACA_EXSLB+EX_R12(r13)
 179         mfspr   r10,SPRN_SPRG_SCRATCH0
 180         std     r10,PACA_EXSLB+EX_R13(r13)
 181         ld      r12,PACALPPACAPTR(r13)
 182         ld      r12,LPPACASRR1(r12)
 183         b       .slb_miss_realmode
 184
 185         STD_EXCEPTION_ISERIES(instruction_access, PACA_EXGEN)
 186
 187         .globl  instruction_access_slb_iSeries
 188 instruction_access_slb_iSeries:
 189         mtspr   SPRN_SPRG_SCRATCH0,r13  /* save r13 */
 190         mfspr   r13,SPRN_SPRG_PACA      /* get paca address into r13 */
 191         std     r3,PACA_EXSLB+EX_R3(r13)
 192         ld      r3,PACALPPACAPTR(r13)
 193         ld      r3,LPPACASRR0(r3)       /* get SRR0 value */
 194         std     r9,PACA_EXSLB+EX_R9(r13)
 195         mfcr    r9
 196 #ifdef __DISABLED__
 197         cmpdi   r3,0
 198         bge     slb_miss_user_iseries
 199 #endif
 200         std     r10,PACA_EXSLB+EX_R10(r13)
 201         std     r11,PACA_EXSLB+EX_R11(r13)
 202         std     r12,PACA_EXSLB+EX_R12(r13)
 203         mfspr   r10,SPRN_SPRG_SCRATCH0
 204         std     r10,PACA_EXSLB+EX_R13(r13)
 205         ld      r12,PACALPPACAPTR(r13)
 206         ld      r12,LPPACASRR1(r12)
 207         b       .slb_miss_realmode
 208
 209 #ifdef __DISABLED__
 210 slb_miss_user_iseries:
 211         std     r10,PACA_EXGEN+EX_R10(r13)
 212         std     r11,PACA_EXGEN+EX_R11(r13)
 213         std     r12,PACA_EXGEN+EX_R12(r13)
 214         mfspr   r10,SPRG_SCRATCH0
 215         ld      r11,PACA_EXSLB+EX_R9(r13)
 216         ld      r12,PACA_EXSLB+EX_R3(r13)
 217         std     r10,PACA_EXGEN+EX_R13(r13)
 218         std     r11,PACA_EXGEN+EX_R9(r13)
 219         std     r12,PACA_EXGEN+EX_R3(r13)
 220         EXCEPTION_PROLOG_ISERIES_1
 221         b       slb_miss_user_common
 222 #endif
 223
 224         MASKABLE_EXCEPTION_ISERIES(hardware_interrupt)
 225         STD_EXCEPTION_ISERIES(alignment, PACA_EXGEN)
 226         STD_EXCEPTION_ISERIES(program_check, PACA_EXGEN)
 227         STD_EXCEPTION_ISERIES(fp_unavailable, PACA_EXGEN)
 228         MASKABLE_EXCEPTION_ISERIES(decrementer)
 229         STD_EXCEPTION_ISERIES(trap_0a, PACA_EXGEN)
 230         STD_EXCEPTION_ISERIES(trap_0b, PACA_EXGEN)
 231
 232         .globl  system_call_iSeries
 233 system_call_iSeries:
 234         mr      r9,r13
 235         mfspr   r13,SPRN_SPRG_PACA
 236         EXCEPTION_PROLOG_ISERIES_1
 237         b       system_call_common
 238
 239         STD_EXCEPTION_ISERIES(single_step, PACA_EXGEN)
 240         STD_EXCEPTION_ISERIES(trap_0e, PACA_EXGEN)
 241         STD_EXCEPTION_ISERIES(performance_monitor, PACA_EXGEN)
 242
 243 decrementer_iSeries_masked:
 244         /* We may not have a valid TOC pointer in here. */
 245         li      r11,1
 246         ld      r12,PACALPPACAPTR(r13)
 247         stb     r11,LPPACADECRINT(r12)
 248         LOAD_REG_IMMEDIATE(r12, tb_ticks_per_jiffy)
 249         lwz     r12,0(r12)
 250         mtspr   SPRN_DEC,r12
 251         /* fall through */
 252
 253 hardware_interrupt_iSeries_masked:
 254         mtcrf   0x80,r9         /* Restore regs */
 255         ld      r12,PACALPPACAPTR(r13)
 256         ld      r11,LPPACASRR0(r12)
 257         ld      r12,LPPACASRR1(r12)
 258         mtspr   SPRN_SRR0,r11
 259         mtspr   SPRN_SRR1,r12
 260         ld      r9,PACA_EXGEN+EX_R9(r13)
 261         ld      r10,PACA_EXGEN+EX_R10(r13)
 262         ld      r11,PACA_EXGEN+EX_R11(r13)
 263         ld      r12,PACA_EXGEN+EX_R12(r13)
 264         ld      r13,PACA_EXGEN+EX_R13(r13)
 265         rfid
 266         b       .       /* prevent speculative execution */
 267
 268 _INIT_STATIC(__start_initialization_iSeries)
 269         /* Clear out the BSS */
 270         LOAD_REG_ADDR(r11,__bss_stop)
 271         LOAD_REG_ADDR(r8,__bss_start)
 272         sub     r11,r11,r8              /* bss size                     */
 273         addi    r11,r11,7               /* round up to an even double word */
 274         rldicl. r11,r11,61,3            /* shift right by 3             */
 275         beq     4f
 276         addi    r8,r8,-8
 277         li      r0,0
 278         mtctr   r11                     /* zero this many doublewords   */
 279 3:      stdu    r0,8(r8)
 280         bdnz    3b
 281 4:
 282         LOAD_REG_ADDR(r1,init_thread_union)
 283         addi    r1,r1,THREAD_SIZE
 284         li      r0,0
 285         stdu    r0,-STACK_FRAME_OVERHEAD(r1)
 286
 287         bl      .iSeries_early_setup
 288         bl      .early_setup
 289
 290         /* relocation is on at this point */
 291
 292         b       .start_here_common