2 * arch/powerpc/sysdev/ipic.c
4 * IPIC routines implementations.
6 * Copyright 2005 Freescale Semiconductor, Inc.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/errno.h>
16 #include <linux/reboot.h>
17 #include <linux/slab.h>
18 #include <linux/stddef.h>
19 #include <linux/sched.h>
20 #include <linux/signal.h>
21 #include <linux/sysdev.h>
22 #include <linux/device.h>
23 #include <linux/bootmem.h>
24 #include <linux/spinlock.h>
25 #include <linux/fsl_devices.h>
33 static struct ipic
* primary_ipic
;
34 static struct irq_chip ipic_level_irq_chip
, ipic_edge_irq_chip
;
35 static DEFINE_SPINLOCK(ipic_lock
);
37 static struct ipic_info ipic_info
[] = {
41 .force
= IPIC_SIFCR_H
,
48 .force
= IPIC_SIFCR_H
,
55 .force
= IPIC_SIFCR_H
,
62 .force
= IPIC_SIFCR_H
,
69 .force
= IPIC_SIFCR_H
,
76 .force
= IPIC_SIFCR_H
,
83 .force
= IPIC_SIFCR_H
,
90 .force
= IPIC_SIFCR_H
,
97 .force
= IPIC_SIFCR_H
,
102 .mask
= IPIC_SIMSR_H
,
103 .prio
= IPIC_SIPRR_D
,
104 .force
= IPIC_SIFCR_H
,
109 .mask
= IPIC_SIMSR_H
,
110 .prio
= IPIC_SIPRR_D
,
111 .force
= IPIC_SIFCR_H
,
116 .mask
= IPIC_SIMSR_H
,
117 .prio
= IPIC_SIPRR_D
,
118 .force
= IPIC_SIFCR_H
,
123 .mask
= IPIC_SIMSR_H
,
124 .prio
= IPIC_SIPRR_D
,
125 .force
= IPIC_SIFCR_H
,
130 .mask
= IPIC_SIMSR_H
,
131 .prio
= IPIC_SIPRR_D
,
132 .force
= IPIC_SIFCR_H
,
137 .mask
= IPIC_SIMSR_H
,
138 .prio
= IPIC_SIPRR_D
,
139 .force
= IPIC_SIFCR_H
,
144 .mask
= IPIC_SIMSR_H
,
145 .prio
= IPIC_SIPRR_D
,
146 .force
= IPIC_SIFCR_H
,
153 .prio
= IPIC_SMPRR_A
,
161 .prio
= IPIC_SMPRR_A
,
169 .prio
= IPIC_SMPRR_A
,
177 .prio
= IPIC_SMPRR_B
,
185 .prio
= IPIC_SMPRR_B
,
193 .prio
= IPIC_SMPRR_B
,
201 .prio
= IPIC_SMPRR_B
,
207 .mask
= IPIC_SIMSR_H
,
208 .prio
= IPIC_SIPRR_A
,
209 .force
= IPIC_SIFCR_H
,
214 .mask
= IPIC_SIMSR_H
,
215 .prio
= IPIC_SIPRR_A
,
216 .force
= IPIC_SIFCR_H
,
221 .mask
= IPIC_SIMSR_H
,
222 .prio
= IPIC_SIPRR_A
,
223 .force
= IPIC_SIFCR_H
,
228 .mask
= IPIC_SIMSR_H
,
229 .prio
= IPIC_SIPRR_A
,
230 .force
= IPIC_SIFCR_H
,
235 .mask
= IPIC_SIMSR_H
,
236 .prio
= IPIC_SIPRR_A
,
237 .force
= IPIC_SIFCR_H
,
242 .mask
= IPIC_SIMSR_H
,
243 .prio
= IPIC_SIPRR_A
,
244 .force
= IPIC_SIFCR_H
,
249 .mask
= IPIC_SIMSR_H
,
250 .prio
= IPIC_SIPRR_A
,
251 .force
= IPIC_SIFCR_H
,
256 .mask
= IPIC_SIMSR_H
,
257 .prio
= IPIC_SIPRR_A
,
258 .force
= IPIC_SIFCR_H
,
263 .mask
= IPIC_SIMSR_H
,
264 .prio
= IPIC_SIPRR_B
,
265 .force
= IPIC_SIFCR_H
,
270 .mask
= IPIC_SIMSR_H
,
271 .prio
= IPIC_SIPRR_B
,
272 .force
= IPIC_SIFCR_H
,
277 .mask
= IPIC_SIMSR_H
,
278 .prio
= IPIC_SIPRR_B
,
279 .force
= IPIC_SIFCR_H
,
284 .mask
= IPIC_SIMSR_H
,
285 .prio
= IPIC_SIPRR_B
,
286 .force
= IPIC_SIFCR_H
,
291 .mask
= IPIC_SIMSR_H
,
292 .prio
= IPIC_SIPRR_B
,
293 .force
= IPIC_SIFCR_H
,
298 .mask
= IPIC_SIMSR_H
,
299 .prio
= IPIC_SIPRR_B
,
300 .force
= IPIC_SIFCR_H
,
305 .mask
= IPIC_SIMSR_H
,
306 .prio
= IPIC_SIPRR_B
,
307 .force
= IPIC_SIFCR_H
,
312 .mask
= IPIC_SIMSR_H
,
313 .prio
= IPIC_SIPRR_B
,
314 .force
= IPIC_SIFCR_H
,
320 .prio
= IPIC_SMPRR_A
,
326 .mask
= IPIC_SIMSR_L
,
327 .prio
= IPIC_SMPRR_A
,
328 .force
= IPIC_SIFCR_L
,
333 .mask
= IPIC_SIMSR_L
,
334 .prio
= IPIC_SMPRR_A
,
335 .force
= IPIC_SIFCR_L
,
340 .mask
= IPIC_SIMSR_L
,
341 .prio
= IPIC_SMPRR_A
,
342 .force
= IPIC_SIFCR_L
,
347 .mask
= IPIC_SIMSR_L
,
348 .prio
= IPIC_SMPRR_A
,
349 .force
= IPIC_SIFCR_L
,
354 .mask
= IPIC_SIMSR_L
,
355 .prio
= IPIC_SMPRR_B
,
356 .force
= IPIC_SIFCR_L
,
361 .mask
= IPIC_SIMSR_L
,
362 .prio
= IPIC_SMPRR_B
,
363 .force
= IPIC_SIFCR_L
,
368 .mask
= IPIC_SIMSR_L
,
369 .prio
= IPIC_SMPRR_B
,
370 .force
= IPIC_SIFCR_L
,
375 .mask
= IPIC_SIMSR_L
,
376 .prio
= IPIC_SMPRR_B
,
377 .force
= IPIC_SIFCR_L
,
382 .mask
= IPIC_SIMSR_L
,
384 .force
= IPIC_SIFCR_L
,
388 .mask
= IPIC_SIMSR_L
,
390 .force
= IPIC_SIFCR_L
,
394 .mask
= IPIC_SIMSR_L
,
396 .force
= IPIC_SIFCR_L
,
400 .mask
= IPIC_SIMSR_L
,
402 .force
= IPIC_SIFCR_L
,
406 .mask
= IPIC_SIMSR_L
,
408 .force
= IPIC_SIFCR_L
,
412 .mask
= IPIC_SIMSR_L
,
414 .force
= IPIC_SIFCR_L
,
418 .mask
= IPIC_SIMSR_L
,
420 .force
= IPIC_SIFCR_L
,
424 .mask
= IPIC_SIMSR_L
,
426 .force
= IPIC_SIFCR_L
,
430 .mask
= IPIC_SIMSR_L
,
432 .force
= IPIC_SIFCR_L
,
436 .mask
= IPIC_SIMSR_L
,
438 .force
= IPIC_SIFCR_L
,
442 .mask
= IPIC_SIMSR_L
,
444 .force
= IPIC_SIFCR_L
,
448 .mask
= IPIC_SIMSR_L
,
450 .force
= IPIC_SIFCR_L
,
454 .mask
= IPIC_SIMSR_L
,
456 .force
= IPIC_SIFCR_L
,
460 .mask
= IPIC_SIMSR_L
,
462 .force
= IPIC_SIFCR_L
,
466 .mask
= IPIC_SIMSR_L
,
468 .force
= IPIC_SIFCR_L
,
472 .mask
= IPIC_SIMSR_L
,
474 .force
= IPIC_SIFCR_L
,
478 .mask
= IPIC_SIMSR_L
,
480 .force
= IPIC_SIFCR_L
,
484 .mask
= IPIC_SIMSR_L
,
486 .force
= IPIC_SIFCR_L
,
490 .mask
= IPIC_SIMSR_L
,
492 .force
= IPIC_SIFCR_L
,
496 .mask
= IPIC_SIMSR_L
,
498 .force
= IPIC_SIFCR_L
,
502 .mask
= IPIC_SIMSR_L
,
504 .force
= IPIC_SIFCR_L
,
509 static inline u32
ipic_read(volatile u32 __iomem
*base
, unsigned int reg
)
511 return in_be32(base
+ (reg
>> 2));
514 static inline void ipic_write(volatile u32 __iomem
*base
, unsigned int reg
, u32 value
)
516 out_be32(base
+ (reg
>> 2), value
);
519 static inline struct ipic
* ipic_from_irq(unsigned int virq
)
524 #define ipic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
526 static void ipic_unmask_irq(unsigned int virq
)
528 struct ipic
*ipic
= ipic_from_irq(virq
);
529 unsigned int src
= ipic_irq_to_hw(virq
);
533 spin_lock_irqsave(&ipic_lock
, flags
);
535 temp
= ipic_read(ipic
->regs
, ipic_info
[src
].mask
);
536 temp
|= (1 << (31 - ipic_info
[src
].bit
));
537 ipic_write(ipic
->regs
, ipic_info
[src
].mask
, temp
);
539 spin_unlock_irqrestore(&ipic_lock
, flags
);
542 static void ipic_mask_irq(unsigned int virq
)
544 struct ipic
*ipic
= ipic_from_irq(virq
);
545 unsigned int src
= ipic_irq_to_hw(virq
);
549 spin_lock_irqsave(&ipic_lock
, flags
);
551 temp
= ipic_read(ipic
->regs
, ipic_info
[src
].mask
);
552 temp
&= ~(1 << (31 - ipic_info
[src
].bit
));
553 ipic_write(ipic
->regs
, ipic_info
[src
].mask
, temp
);
555 /* mb() can't guarantee that masking is finished. But it does finish
556 * for nearly all cases. */
559 spin_unlock_irqrestore(&ipic_lock
, flags
);
562 static void ipic_ack_irq(unsigned int virq
)
564 struct ipic
*ipic
= ipic_from_irq(virq
);
565 unsigned int src
= ipic_irq_to_hw(virq
);
569 spin_lock_irqsave(&ipic_lock
, flags
);
571 temp
= 1 << (31 - ipic_info
[src
].bit
);
572 ipic_write(ipic
->regs
, ipic_info
[src
].ack
, temp
);
574 /* mb() can't guarantee that ack is finished. But it does finish
575 * for nearly all cases. */
578 spin_unlock_irqrestore(&ipic_lock
, flags
);
581 static void ipic_mask_irq_and_ack(unsigned int virq
)
583 struct ipic
*ipic
= ipic_from_irq(virq
);
584 unsigned int src
= ipic_irq_to_hw(virq
);
588 spin_lock_irqsave(&ipic_lock
, flags
);
590 temp
= ipic_read(ipic
->regs
, ipic_info
[src
].mask
);
591 temp
&= ~(1 << (31 - ipic_info
[src
].bit
));
592 ipic_write(ipic
->regs
, ipic_info
[src
].mask
, temp
);
594 temp
= 1 << (31 - ipic_info
[src
].bit
);
595 ipic_write(ipic
->regs
, ipic_info
[src
].ack
, temp
);
597 /* mb() can't guarantee that ack is finished. But it does finish
598 * for nearly all cases. */
601 spin_unlock_irqrestore(&ipic_lock
, flags
);
604 static int ipic_set_irq_type(unsigned int virq
, unsigned int flow_type
)
606 struct ipic
*ipic
= ipic_from_irq(virq
);
607 unsigned int src
= ipic_irq_to_hw(virq
);
608 struct irq_desc
*desc
= get_irq_desc(virq
);
609 unsigned int vold
, vnew
, edibit
;
611 if (flow_type
== IRQ_TYPE_NONE
)
612 flow_type
= IRQ_TYPE_LEVEL_LOW
;
614 /* ipic supports only low assertion and high-to-low change senses
616 if (!(flow_type
& (IRQ_TYPE_LEVEL_LOW
| IRQ_TYPE_EDGE_FALLING
))) {
617 printk(KERN_ERR
"ipic: sense type 0x%x not supported\n",
621 /* ipic supports only edge mode on external interrupts */
622 if ((flow_type
& IRQ_TYPE_EDGE_FALLING
) && !ipic_info
[src
].ack
) {
623 printk(KERN_ERR
"ipic: edge sense not supported on internal "
628 desc
->status
&= ~(IRQ_TYPE_SENSE_MASK
| IRQ_LEVEL
);
629 desc
->status
|= flow_type
& IRQ_TYPE_SENSE_MASK
;
630 if (flow_type
& IRQ_TYPE_LEVEL_LOW
) {
631 desc
->status
|= IRQ_LEVEL
;
632 desc
->handle_irq
= handle_level_irq
;
633 desc
->chip
= &ipic_level_irq_chip
;
635 desc
->handle_irq
= handle_edge_irq
;
636 desc
->chip
= &ipic_edge_irq_chip
;
639 /* only EXT IRQ senses are programmable on ipic
640 * internal IRQ senses are LEVEL_LOW
642 if (src
== IPIC_IRQ_EXT0
)
645 if (src
>= IPIC_IRQ_EXT1
&& src
<= IPIC_IRQ_EXT7
)
646 edibit
= (14 - (src
- IPIC_IRQ_EXT1
));
648 return (flow_type
& IRQ_TYPE_LEVEL_LOW
) ? 0 : -EINVAL
;
650 vold
= ipic_read(ipic
->regs
, IPIC_SECNR
);
651 if ((flow_type
& IRQ_TYPE_SENSE_MASK
) == IRQ_TYPE_EDGE_FALLING
) {
652 vnew
= vold
| (1 << edibit
);
654 vnew
= vold
& ~(1 << edibit
);
657 ipic_write(ipic
->regs
, IPIC_SECNR
, vnew
);
661 /* level interrupts and edge interrupts have different ack operations */
662 static struct irq_chip ipic_level_irq_chip
= {
663 .typename
= " IPIC ",
664 .unmask
= ipic_unmask_irq
,
665 .mask
= ipic_mask_irq
,
666 .mask_ack
= ipic_mask_irq
,
667 .set_type
= ipic_set_irq_type
,
670 static struct irq_chip ipic_edge_irq_chip
= {
671 .typename
= " IPIC ",
672 .unmask
= ipic_unmask_irq
,
673 .mask
= ipic_mask_irq
,
674 .mask_ack
= ipic_mask_irq_and_ack
,
676 .set_type
= ipic_set_irq_type
,
679 static int ipic_host_match(struct irq_host
*h
, struct device_node
*node
)
681 /* Exact match, unless ipic node is NULL */
682 return h
->of_node
== NULL
|| h
->of_node
== node
;
685 static int ipic_host_map(struct irq_host
*h
, unsigned int virq
,
688 struct ipic
*ipic
= h
->host_data
;
690 set_irq_chip_data(virq
, ipic
);
691 set_irq_chip_and_handler(virq
, &ipic_level_irq_chip
, handle_level_irq
);
693 /* Set default irq type */
694 set_irq_type(virq
, IRQ_TYPE_NONE
);
699 static int ipic_host_xlate(struct irq_host
*h
, struct device_node
*ct
,
700 u32
*intspec
, unsigned int intsize
,
701 irq_hw_number_t
*out_hwirq
, unsigned int *out_flags
)
704 /* interrupt sense values coming from the device tree equal either
705 * LEVEL_LOW (low assertion) or EDGE_FALLING (high-to-low change)
707 *out_hwirq
= intspec
[0];
709 *out_flags
= intspec
[1];
711 *out_flags
= IRQ_TYPE_NONE
;
715 static struct irq_host_ops ipic_host_ops
= {
716 .match
= ipic_host_match
,
717 .map
= ipic_host_map
,
718 .xlate
= ipic_host_xlate
,
721 struct ipic
* __init
ipic_init(struct device_node
*node
, unsigned int flags
)
727 ret
= of_address_to_resource(node
, 0, &res
);
731 ipic
= kzalloc(sizeof(*ipic
), GFP_KERNEL
);
735 ipic
->irqhost
= irq_alloc_host(node
, IRQ_HOST_MAP_LINEAR
,
738 if (ipic
->irqhost
== NULL
) {
743 ipic
->regs
= ioremap(res
.start
, res
.end
- res
.start
+ 1);
745 ipic
->irqhost
->host_data
= ipic
;
748 ipic_write(ipic
->regs
, IPIC_SICNR
, 0x0);
750 /* default priority scheme is grouped. If spread mode is required
751 * configure SICFR accordingly */
752 if (flags
& IPIC_SPREADMODE_GRP_A
)
754 if (flags
& IPIC_SPREADMODE_GRP_B
)
756 if (flags
& IPIC_SPREADMODE_GRP_C
)
758 if (flags
& IPIC_SPREADMODE_GRP_D
)
760 if (flags
& IPIC_SPREADMODE_MIX_A
)
762 if (flags
& IPIC_SPREADMODE_MIX_B
)
765 ipic_write(ipic
->regs
, IPIC_SICFR
, temp
);
767 /* handle MCP route */
769 if (flags
& IPIC_DISABLE_MCP_OUT
)
771 ipic_write(ipic
->regs
, IPIC_SERCR
, temp
);
773 /* handle routing of IRQ0 to MCP */
774 temp
= ipic_read(ipic
->regs
, IPIC_SEMSR
);
776 if (flags
& IPIC_IRQ0_MCP
)
779 temp
&= ~SEMSR_SIRQ0
;
781 ipic_write(ipic
->regs
, IPIC_SEMSR
, temp
);
784 irq_set_default_host(primary_ipic
->irqhost
);
786 ipic_write(ipic
->regs
, IPIC_SIMSR_H
, 0);
787 ipic_write(ipic
->regs
, IPIC_SIMSR_L
, 0);
789 printk ("IPIC (%d IRQ sources) at %p\n", NR_IPIC_INTS
,
795 int ipic_set_priority(unsigned int virq
, unsigned int priority
)
797 struct ipic
*ipic
= ipic_from_irq(virq
);
798 unsigned int src
= ipic_irq_to_hw(virq
);
805 if (ipic_info
[src
].prio
== 0)
808 temp
= ipic_read(ipic
->regs
, ipic_info
[src
].prio
);
811 temp
&= ~(0x7 << (20 + (3 - priority
) * 3));
812 temp
|= ipic_info
[src
].prio_mask
<< (20 + (3 - priority
) * 3);
814 temp
&= ~(0x7 << (4 + (7 - priority
) * 3));
815 temp
|= ipic_info
[src
].prio_mask
<< (4 + (7 - priority
) * 3);
818 ipic_write(ipic
->regs
, ipic_info
[src
].prio
, temp
);
823 void ipic_set_highest_priority(unsigned int virq
)
825 struct ipic
*ipic
= ipic_from_irq(virq
);
826 unsigned int src
= ipic_irq_to_hw(virq
);
829 temp
= ipic_read(ipic
->regs
, IPIC_SICFR
);
831 /* clear and set HPI */
833 temp
|= (src
& 0x7f) << 24;
835 ipic_write(ipic
->regs
, IPIC_SICFR
, temp
);
838 void ipic_set_default_priority(void)
840 ipic_write(primary_ipic
->regs
, IPIC_SIPRR_A
, IPIC_PRIORITY_DEFAULT
);
841 ipic_write(primary_ipic
->regs
, IPIC_SIPRR_B
, IPIC_PRIORITY_DEFAULT
);
842 ipic_write(primary_ipic
->regs
, IPIC_SIPRR_C
, IPIC_PRIORITY_DEFAULT
);
843 ipic_write(primary_ipic
->regs
, IPIC_SIPRR_D
, IPIC_PRIORITY_DEFAULT
);
844 ipic_write(primary_ipic
->regs
, IPIC_SMPRR_A
, IPIC_PRIORITY_DEFAULT
);
845 ipic_write(primary_ipic
->regs
, IPIC_SMPRR_B
, IPIC_PRIORITY_DEFAULT
);
848 void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq
)
850 struct ipic
*ipic
= primary_ipic
;
853 temp
= ipic_read(ipic
->regs
, IPIC_SERMR
);
854 temp
|= (1 << (31 - mcp_irq
));
855 ipic_write(ipic
->regs
, IPIC_SERMR
, temp
);
858 void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq
)
860 struct ipic
*ipic
= primary_ipic
;
863 temp
= ipic_read(ipic
->regs
, IPIC_SERMR
);
864 temp
&= (1 << (31 - mcp_irq
));
865 ipic_write(ipic
->regs
, IPIC_SERMR
, temp
);
868 u32
ipic_get_mcp_status(void)
870 return ipic_read(primary_ipic
->regs
, IPIC_SERMR
);
873 void ipic_clear_mcp_status(u32 mask
)
875 ipic_write(primary_ipic
->regs
, IPIC_SERMR
, mask
);
878 /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
879 unsigned int ipic_get_irq(void)
883 BUG_ON(primary_ipic
== NULL
);
885 #define IPIC_SIVCR_VECTOR_MASK 0x7f
886 irq
= ipic_read(primary_ipic
->regs
, IPIC_SIVCR
) & IPIC_SIVCR_VECTOR_MASK
;
888 if (irq
== 0) /* 0 --> no irq is pending */
891 return irq_linear_revmap(primary_ipic
->irqhost
, irq
);
894 #ifdef CONFIG_SUSPEND
907 static int ipic_suspend(struct sys_device
*sdev
, pm_message_t state
)
909 struct ipic
*ipic
= primary_ipic
;
911 ipic_saved_state
.sicfr
= ipic_read(ipic
->regs
, IPIC_SICFR
);
912 ipic_saved_state
.siprr
[0] = ipic_read(ipic
->regs
, IPIC_SIPRR_A
);
913 ipic_saved_state
.siprr
[1] = ipic_read(ipic
->regs
, IPIC_SIPRR_D
);
914 ipic_saved_state
.simsr
[0] = ipic_read(ipic
->regs
, IPIC_SIMSR_H
);
915 ipic_saved_state
.simsr
[1] = ipic_read(ipic
->regs
, IPIC_SIMSR_L
);
916 ipic_saved_state
.sicnr
= ipic_read(ipic
->regs
, IPIC_SICNR
);
917 ipic_saved_state
.smprr
[0] = ipic_read(ipic
->regs
, IPIC_SMPRR_A
);
918 ipic_saved_state
.smprr
[1] = ipic_read(ipic
->regs
, IPIC_SMPRR_B
);
919 ipic_saved_state
.semsr
= ipic_read(ipic
->regs
, IPIC_SEMSR
);
920 ipic_saved_state
.secnr
= ipic_read(ipic
->regs
, IPIC_SECNR
);
921 ipic_saved_state
.sermr
= ipic_read(ipic
->regs
, IPIC_SERMR
);
922 ipic_saved_state
.sercr
= ipic_read(ipic
->regs
, IPIC_SERCR
);
924 if (fsl_deep_sleep()) {
925 /* In deep sleep, make sure there can be no
926 * pending interrupts, as this can cause
929 ipic_write(ipic
->regs
, IPIC_SIMSR_H
, 0);
930 ipic_write(ipic
->regs
, IPIC_SIMSR_L
, 0);
931 ipic_write(ipic
->regs
, IPIC_SEMSR
, 0);
932 ipic_write(ipic
->regs
, IPIC_SERMR
, 0);
938 static int ipic_resume(struct sys_device
*sdev
)
940 struct ipic
*ipic
= primary_ipic
;
942 ipic_write(ipic
->regs
, IPIC_SICFR
, ipic_saved_state
.sicfr
);
943 ipic_write(ipic
->regs
, IPIC_SIPRR_A
, ipic_saved_state
.siprr
[0]);
944 ipic_write(ipic
->regs
, IPIC_SIPRR_D
, ipic_saved_state
.siprr
[1]);
945 ipic_write(ipic
->regs
, IPIC_SIMSR_H
, ipic_saved_state
.simsr
[0]);
946 ipic_write(ipic
->regs
, IPIC_SIMSR_L
, ipic_saved_state
.simsr
[1]);
947 ipic_write(ipic
->regs
, IPIC_SICNR
, ipic_saved_state
.sicnr
);
948 ipic_write(ipic
->regs
, IPIC_SMPRR_A
, ipic_saved_state
.smprr
[0]);
949 ipic_write(ipic
->regs
, IPIC_SMPRR_B
, ipic_saved_state
.smprr
[1]);
950 ipic_write(ipic
->regs
, IPIC_SEMSR
, ipic_saved_state
.semsr
);
951 ipic_write(ipic
->regs
, IPIC_SECNR
, ipic_saved_state
.secnr
);
952 ipic_write(ipic
->regs
, IPIC_SERMR
, ipic_saved_state
.sermr
);
953 ipic_write(ipic
->regs
, IPIC_SERCR
, ipic_saved_state
.sercr
);
958 #define ipic_suspend NULL
959 #define ipic_resume NULL
962 static struct sysdev_class ipic_sysclass
= {
964 .suspend
= ipic_suspend
,
965 .resume
= ipic_resume
,
968 static struct sys_device device_ipic
= {
970 .cls
= &ipic_sysclass
,
973 static int __init
init_ipic_sysfs(void)
977 if (!primary_ipic
|| !primary_ipic
->regs
)
979 printk(KERN_DEBUG
"Registering ipic with sysfs...\n");
981 rc
= sysdev_class_register(&ipic_sysclass
);
983 printk(KERN_ERR
"Failed registering ipic sys class\n");
986 rc
= sysdev_register(&device_ipic
);
988 printk(KERN_ERR
"Failed registering ipic sys device\n");
994 subsys_initcall(init_ipic_sysfs
);