Full support for Ginger Console
[linux-ginger.git] / arch / sh / include / asm / processor.h
blob017e0c1807b263fe864a04d775e0eef502c59985
1 #ifndef __ASM_SH_PROCESSOR_H
2 #define __ASM_SH_PROCESSOR_H
4 #include <asm/cpu-features.h>
5 #include <asm/segment.h>
6 #include <asm/cache.h>
8 #ifndef __ASSEMBLY__
9 /*
10 * CPU type and hardware bug flags. Kept separately for each CPU.
12 * Each one of these also needs a CONFIG_CPU_SUBTYPE_xxx entry
13 * in arch/sh/mm/Kconfig, as well as an entry in arch/sh/kernel/setup.c
14 * for parsing the subtype in get_cpu_subtype().
16 enum cpu_type {
17 /* SH-2 types */
18 CPU_SH7619,
20 /* SH-2A types */
21 CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_MXG,
23 /* SH-3 types */
24 CPU_SH7705, CPU_SH7706, CPU_SH7707,
25 CPU_SH7708, CPU_SH7708S, CPU_SH7708R,
26 CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712,
27 CPU_SH7720, CPU_SH7721, CPU_SH7729,
29 /* SH-4 types */
30 CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R,
31 CPU_SH7760, CPU_SH4_202, CPU_SH4_501,
33 /* SH-4A types */
34 CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786,
35 CPU_SH7723, CPU_SH7724, CPU_SH7757, CPU_SHX3,
37 /* SH4AL-DSP types */
38 CPU_SH7343, CPU_SH7722, CPU_SH7366,
40 /* SH-5 types */
41 CPU_SH5_101, CPU_SH5_103,
43 /* Unknown subtype */
44 CPU_SH_NONE
47 enum cpu_family {
48 CPU_FAMILY_SH2,
49 CPU_FAMILY_SH2A,
50 CPU_FAMILY_SH3,
51 CPU_FAMILY_SH4,
52 CPU_FAMILY_SH4A,
53 CPU_FAMILY_SH4AL_DSP,
54 CPU_FAMILY_SH5,
55 CPU_FAMILY_UNKNOWN,
59 * TLB information structure
61 * Defined for both I and D tlb, per-processor.
63 struct tlb_info {
64 unsigned long long next;
65 unsigned long long first;
66 unsigned long long last;
68 unsigned int entries;
69 unsigned int step;
71 unsigned long flags;
74 struct sh_cpuinfo {
75 unsigned int type, family;
76 int cut_major, cut_minor;
77 unsigned long loops_per_jiffy;
78 unsigned long asid_cache;
80 struct cache_info icache; /* Primary I-cache */
81 struct cache_info dcache; /* Primary D-cache */
82 struct cache_info scache; /* Secondary cache */
84 /* TLB info */
85 struct tlb_info itlb;
86 struct tlb_info dtlb;
88 unsigned long flags;
89 } __attribute__ ((aligned(L1_CACHE_BYTES)));
91 extern struct sh_cpuinfo cpu_data[];
92 #define boot_cpu_data cpu_data[0]
93 #define current_cpu_data cpu_data[smp_processor_id()]
94 #define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
96 #define cpu_sleep() __asm__ __volatile__ ("sleep" : : : "memory")
97 #define cpu_relax() barrier()
99 /* Forward decl */
100 struct seq_operations;
102 extern struct pt_regs fake_swapper_regs;
104 /* arch/sh/kernel/setup.c */
105 const char *get_cpu_subtype(struct sh_cpuinfo *c);
106 extern const struct seq_operations cpuinfo_op;
108 /* processor boot mode configuration */
109 #define MODE_PIN0 (1 << 0)
110 #define MODE_PIN1 (1 << 1)
111 #define MODE_PIN2 (1 << 2)
112 #define MODE_PIN3 (1 << 3)
113 #define MODE_PIN4 (1 << 4)
114 #define MODE_PIN5 (1 << 5)
115 #define MODE_PIN6 (1 << 6)
116 #define MODE_PIN7 (1 << 7)
117 #define MODE_PIN8 (1 << 8)
118 #define MODE_PIN9 (1 << 9)
119 #define MODE_PIN10 (1 << 10)
120 #define MODE_PIN11 (1 << 11)
121 #define MODE_PIN12 (1 << 12)
122 #define MODE_PIN13 (1 << 13)
123 #define MODE_PIN14 (1 << 14)
124 #define MODE_PIN15 (1 << 15)
126 int generic_mode_pins(void);
127 int test_mode_pin(int pin);
129 #ifdef CONFIG_VSYSCALL
130 int vsyscall_init(void);
131 #else
132 #define vsyscall_init() do { } while (0)
133 #endif
135 #endif /* __ASSEMBLY__ */
137 #ifdef CONFIG_SUPERH32
138 # include "processor_32.h"
139 #else
140 # include "processor_64.h"
141 #endif
143 #endif /* __ASM_SH_PROCESSOR_H */