arch/sh/kernel/cpu/sh4a/clock-sh7722.c

   1 /*
   2  * arch/sh/kernel/cpu/sh4a/clock-sh7722.c
   3  *
   4  * SH7722 clock framework support
   5  *
   6  * Copyright (C) 2009 Magnus Damm
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/init.h>
  22 #include <linux/kernel.h>
  23 #include <linux/io.h>
  24 #include <asm/clock.h>
  25 #include <asm/hwblk.h>
  26 #include <cpu/sh7722.h>
  27
  28 /* SH7722 registers */
  29 #define FRQCR           0xa4150000
  30 #define VCLKCR          0xa4150004
  31 #define SCLKACR         0xa4150008
  32 #define SCLKBCR         0xa415000c
  33 #define IRDACLKCR       0xa4150018
  34 #define PLLCR           0xa4150024
  35 #define DLLFRQ          0xa4150050
  36
  37 /* Fixed 32 KHz root clock for RTC and Power Management purposes */
  38 static struct clk r_clk = {
  39         .name           = "rclk",
  40         .id             = -1,
  41         .rate           = 32768,
  42 };
  43
  44 /*
  45  * Default rate for the root input clock, reset this with clk_set_rate()
  46  * from the platform code.
  47  */
  48 struct clk extal_clk = {
  49         .name           = "extal",
  50         .id             = -1,
  51         .rate           = 33333333,
  52 };
  53
  54 /* The dll block multiplies the 32khz r_clk, may be used instead of extal */
  55 static unsigned long dll_recalc(struct clk *clk)
  56 {
  57         unsigned long mult;
  58
  59         if (__raw_readl(PLLCR) & 0x1000)
  60                 mult = __raw_readl(DLLFRQ);
  61         else
  62                 mult = 0;
  63
  64         return clk->parent->rate * mult;
  65 }
  66
  67 static struct clk_ops dll_clk_ops = {
  68         .recalc         = dll_recalc,
  69 };
  70
  71 static struct clk dll_clk = {
  72         .name           = "dll_clk",
  73         .id             = -1,
  74         .ops            = &dll_clk_ops,
  75         .parent         = &r_clk,
  76         .flags          = CLK_ENABLE_ON_INIT,
  77 };
  78
  79 static unsigned long pll_recalc(struct clk *clk)
  80 {
  81         unsigned long mult = 1;
  82         unsigned long div = 1;
  83
  84         if (__raw_readl(PLLCR) & 0x4000)
  85                 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
  86         else
  87                 div = 2;
  88
  89         return (clk->parent->rate * mult) / div;
  90 }
  91
  92 static struct clk_ops pll_clk_ops = {
  93         .recalc         = pll_recalc,
  94 };
  95
  96 static struct clk pll_clk = {
  97         .name           = "pll_clk",
  98         .id             = -1,
  99         .ops            = &pll_clk_ops,
 100         .flags          = CLK_ENABLE_ON_INIT,
 101 };
 102
 103 struct clk *main_clks[] = {
 104         &r_clk,
 105         &extal_clk,
 106         &dll_clk,
 107         &pll_clk,
 108 };
 109
 110 static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
 111 static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
 112
 113 static struct clk_div_mult_table div4_table = {
 114         .divisors = divisors,
 115         .nr_divisors = ARRAY_SIZE(divisors),
 116         .multipliers = multipliers,
 117         .nr_multipliers = ARRAY_SIZE(multipliers),
 118 };
 119
 120 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
 121        DIV4_SIUA, DIV4_SIUB, DIV4_IRDA, DIV4_NR };
 122
 123 #define DIV4(_str, _reg, _bit, _mask, _flags) \
 124   SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
 125
 126 struct clk div4_clks[DIV4_NR] = {
 127         [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
 128         [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
 129         [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
 130         [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
 131         [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
 132         [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),
 133         [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),
 134         [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),
 135         [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x1fff, 0),
 136 };
 137
 138 struct clk div6_clks[] = {
 139         SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
 140 };
 141
 142 #define R_CLK &r_clk
 143 #define P_CLK &div4_clks[DIV4_P]
 144 #define B_CLK &div4_clks[DIV4_B]
 145 #define U_CLK &div4_clks[DIV4_U]
 146
 147 static struct clk mstp_clks[] = {
 148         SH_HWBLK_CLK("uram0", -1, U_CLK, HWBLK_URAM, CLK_ENABLE_ON_INIT),
 149         SH_HWBLK_CLK("xymem0", -1, B_CLK, HWBLK_XYMEM, CLK_ENABLE_ON_INIT),
 150         SH_HWBLK_CLK("tmu0", -1, P_CLK, HWBLK_TMU, 0),
 151         SH_HWBLK_CLK("cmt0", -1, R_CLK, HWBLK_CMT, 0),
 152         SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0),
 153         SH_HWBLK_CLK("flctl0", -1, P_CLK, HWBLK_FLCTL, 0),
 154         SH_HWBLK_CLK("scif0", -1, P_CLK, HWBLK_SCIF0, 0),
 155         SH_HWBLK_CLK("scif1", -1, P_CLK, HWBLK_SCIF1, 0),
 156         SH_HWBLK_CLK("scif2", -1, P_CLK, HWBLK_SCIF2, 0),
 157
 158         SH_HWBLK_CLK("i2c0", -1, P_CLK, HWBLK_IIC, 0),
 159         SH_HWBLK_CLK("rtc0", -1, R_CLK, HWBLK_RTC, 0),
 160
 161         SH_HWBLK_CLK("sdhi0", -1, P_CLK, HWBLK_SDHI, 0),
 162         SH_HWBLK_CLK("keysc0", -1, R_CLK, HWBLK_KEYSC, 0),
 163         SH_HWBLK_CLK("usbf0", -1, P_CLK, HWBLK_USBF, 0),
 164         SH_HWBLK_CLK("2dg0", -1, B_CLK, HWBLK_2DG, 0),
 165         SH_HWBLK_CLK("siu0", -1, B_CLK, HWBLK_SIU, 0),
 166         SH_HWBLK_CLK("vou0", -1, B_CLK, HWBLK_VOU, 0),
 167         SH_HWBLK_CLK("jpu0", -1, B_CLK, HWBLK_JPU, 0),
 168         SH_HWBLK_CLK("beu0", -1, B_CLK, HWBLK_BEU, 0),
 169         SH_HWBLK_CLK("ceu0", -1, B_CLK, HWBLK_CEU, 0),
 170         SH_HWBLK_CLK("veu0", -1, B_CLK, HWBLK_VEU, 0),
 171         SH_HWBLK_CLK("vpu0", -1, B_CLK, HWBLK_VPU, 0),
 172         SH_HWBLK_CLK("lcdc0", -1, P_CLK, HWBLK_LCDC, 0),
 173 };
 174
 175 int __init arch_clk_init(void)
 176 {
 177         int k, ret = 0;
 178
 179         /* autodetect extal or dll configuration */
 180         if (__raw_readl(PLLCR) & 0x1000)
 181                 pll_clk.parent = &dll_clk;
 182         else
 183                 pll_clk.parent = &extal_clk;
 184
 185         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
 186                 ret = clk_register(main_clks[k]);
 187
 188         if (!ret)
 189                 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
 190
 191         if (!ret)
 192                 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
 193
 194         if (!ret)
 195                 ret = sh_hwblk_clk_register(mstp_clks, ARRAY_SIZE(mstp_clks));
 196
 197         return ret;
 198 }