arch/sh/kernel/cpu/sh4a/clock-sh7780.c

   1 /*
   2  * arch/sh/kernel/cpu/sh4a/clock-sh7780.c
   3  *
   4  * SH7780 support for the clock framework
   5  *
   6  *  Copyright (C) 2005  Paul Mundt
   7  *
   8  * This file is subject to the terms and conditions of the GNU General Public
   9  * License.  See the file "COPYING" in the main directory of this archive
  10  * for more details.
  11  */
  12 #include <linux/init.h>
  13 #include <linux/kernel.h>
  14 #include <asm/clock.h>
  15 #include <asm/freq.h>
  16 #include <asm/io.h>
  17
  18 static int ifc_divisors[] = { 2, 4 };
  19 static int bfc_divisors[] = { 1, 1, 1, 8, 12, 16, 24, 1 };
  20 static int pfc_divisors[] = { 1, 24, 24, 1 };
  21 static int cfc_divisors[] = { 1, 1, 4, 1, 6, 1, 1, 1 };
  22
  23 static void master_clk_init(struct clk *clk)
  24 {
  25         clk->rate *= pfc_divisors[ctrl_inl(FRQCR) & 0x0003];
  26 }
  27
  28 static struct clk_ops sh7780_master_clk_ops = {
  29         .init           = master_clk_init,
  30 };
  31
  32 static unsigned long module_clk_recalc(struct clk *clk)
  33 {
  34         int idx = (ctrl_inl(FRQCR) & 0x0003);
  35         return clk->parent->rate / pfc_divisors[idx];
  36 }
  37
  38 static struct clk_ops sh7780_module_clk_ops = {
  39         .recalc         = module_clk_recalc,
  40 };
  41
  42 static unsigned long bus_clk_recalc(struct clk *clk)
  43 {
  44         int idx = ((ctrl_inl(FRQCR) >> 16) & 0x0007);
  45         return clk->parent->rate / bfc_divisors[idx];
  46 }
  47
  48 static struct clk_ops sh7780_bus_clk_ops = {
  49         .recalc         = bus_clk_recalc,
  50 };
  51
  52 static unsigned long cpu_clk_recalc(struct clk *clk)
  53 {
  54         int idx = ((ctrl_inl(FRQCR) >> 24) & 0x0001);
  55         return clk->parent->rate / ifc_divisors[idx];
  56 }
  57
  58 static struct clk_ops sh7780_cpu_clk_ops = {
  59         .recalc         = cpu_clk_recalc,
  60 };
  61
  62 static struct clk_ops *sh7780_clk_ops[] = {
  63         &sh7780_master_clk_ops,
  64         &sh7780_module_clk_ops,
  65         &sh7780_bus_clk_ops,
  66         &sh7780_cpu_clk_ops,
  67 };
  68
  69 void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
  70 {
  71         if (idx < ARRAY_SIZE(sh7780_clk_ops))
  72                 *ops = sh7780_clk_ops[idx];
  73 }
  74
  75 static unsigned long shyway_clk_recalc(struct clk *clk)
  76 {
  77         int idx = ((ctrl_inl(FRQCR) >> 20) & 0x0007);
  78         return clk->parent->rate / cfc_divisors[idx];
  79 }
  80
  81 static struct clk_ops sh7780_shyway_clk_ops = {
  82         .recalc         = shyway_clk_recalc,
  83 };
  84
  85 static struct clk sh7780_shyway_clk = {
  86         .name           = "shyway_clk",
  87         .flags          = CLK_ENABLE_ON_INIT,
  88         .ops            = &sh7780_shyway_clk_ops,
  89 };
  90
  91 /*
  92  * Additional SH7780-specific on-chip clocks that aren't already part of the
  93  * clock framework
  94  */
  95 static struct clk *sh7780_onchip_clocks[] = {
  96         &sh7780_shyway_clk,
  97 };
  98
  99 int __init arch_clk_init(void)
 100 {
 101         struct clk *clk;
 102         int i, ret = 0;
 103
 104         cpg_clk_init();
 105
 106         clk = clk_get(NULL, "master_clk");
 107         for (i = 0; i < ARRAY_SIZE(sh7780_onchip_clocks); i++) {
 108                 struct clk *clkp = sh7780_onchip_clocks[i];
 109
 110                 clkp->parent = clk;
 111                 ret |= clk_register(clkp);
 112         }
 113
 114         clk_put(clk);
 115
 116         return ret;
 117 }