arch/sparc/kernel/sun4c_irq.c

   1 /*  sun4c_irq.c
   2  *  arch/sparc/kernel/sun4c_irq.c:
   3  *
   4  *  djhr: Hacked out of irq.c into a CPU dependent version.
   5  *
   6  *  Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   7  *  Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
   8  *  Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com)
   9  *  Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
  10  */
  11
  12 #include <linux/errno.h>
  13 #include <linux/linkage.h>
  14 #include <linux/kernel_stat.h>
  15 #include <linux/signal.h>
  16 #include <linux/sched.h>
  17 #include <linux/ptrace.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/slab.h>
  20 #include <linux/init.h>
  21 #include <linux/of.h>
  22 #include <linux/of_device.h>
  23 #include "irq.h"
  24
  25 #include <asm/ptrace.h>
  26 #include <asm/processor.h>
  27 #include <asm/system.h>
  28 #include <asm/psr.h>
  29 #include <asm/vaddrs.h>
  30 #include <asm/timer.h>
  31 #include <asm/openprom.h>
  32 #include <asm/oplib.h>
  33 #include <asm/traps.h>
  34 #include <asm/irq.h>
  35 #include <asm/io.h>
  36 #include <asm/idprom.h>
  37 #include <asm/machines.h>
  38
  39 /*
  40  * Bit field defines for the interrupt registers on various
  41  * Sparc machines.
  42  */
  43
  44 /* The sun4c interrupt register. */
  45 #define SUN4C_INT_ENABLE  0x01     /* Allow interrupts. */
  46 #define SUN4C_INT_E14     0x80     /* Enable level 14 IRQ. */
  47 #define SUN4C_INT_E10     0x20     /* Enable level 10 IRQ. */
  48 #define SUN4C_INT_E8      0x10     /* Enable level 8 IRQ. */
  49 #define SUN4C_INT_E6      0x08     /* Enable level 6 IRQ. */
  50 #define SUN4C_INT_E4      0x04     /* Enable level 4 IRQ. */
  51 #define SUN4C_INT_E1      0x02     /* Enable level 1 IRQ. */
  52
  53 /* Pointer to the interrupt enable byte
  54  *
  55  * Dave Redman (djhr@tadpole.co.uk)
  56  * What you may not be aware of is that entry.S requires this variable.
  57  *
  58  *  --- linux_trap_nmi_sun4c --
  59  *
  60  * so don't go making it static, like I tried. sigh.
  61  */
  62 unsigned char __iomem *interrupt_enable = NULL;
  63
  64 static void sun4c_disable_irq(unsigned int irq_nr)
  65 {
  66         unsigned long flags;
  67         unsigned char current_mask, new_mask;
  68
  69         local_irq_save(flags);
  70         irq_nr &= (NR_IRQS - 1);
  71         current_mask = sbus_readb(interrupt_enable);
  72         switch(irq_nr) {
  73         case 1:
  74                 new_mask = ((current_mask) & (~(SUN4C_INT_E1)));
  75                 break;
  76         case 8:
  77                 new_mask = ((current_mask) & (~(SUN4C_INT_E8)));
  78                 break;
  79         case 10:
  80                 new_mask = ((current_mask) & (~(SUN4C_INT_E10)));
  81                 break;
  82         case 14:
  83                 new_mask = ((current_mask) & (~(SUN4C_INT_E14)));
  84                 break;
  85         default:
  86                 local_irq_restore(flags);
  87                 return;
  88         }
  89         sbus_writeb(new_mask, interrupt_enable);
  90         local_irq_restore(flags);
  91 }
  92
  93 static void sun4c_enable_irq(unsigned int irq_nr)
  94 {
  95         unsigned long flags;
  96         unsigned char current_mask, new_mask;
  97
  98         local_irq_save(flags);
  99         irq_nr &= (NR_IRQS - 1);
 100         current_mask = sbus_readb(interrupt_enable);
 101         switch(irq_nr) {
 102         case 1:
 103                 new_mask = ((current_mask) | SUN4C_INT_E1);
 104                 break;
 105         case 8:
 106                 new_mask = ((current_mask) | SUN4C_INT_E8);
 107                 break;
 108         case 10:
 109                 new_mask = ((current_mask) | SUN4C_INT_E10);
 110                 break;
 111         case 14:
 112                 new_mask = ((current_mask) | SUN4C_INT_E14);
 113                 break;
 114         default:
 115                 local_irq_restore(flags);
 116                 return;
 117         }
 118         sbus_writeb(new_mask, interrupt_enable);
 119         local_irq_restore(flags);
 120 }
 121
 122 struct sun4c_timer_info {
 123         u32             l10_count;
 124         u32             l10_limit;
 125         u32             l14_count;
 126         u32             l14_limit;
 127 };
 128
 129 static struct sun4c_timer_info __iomem *sun4c_timers;
 130
 131 static void sun4c_clear_clock_irq(void)
 132 {
 133         sbus_readl(&sun4c_timers->l10_limit);
 134 }
 135
 136 static void sun4c_load_profile_irq(int cpu, unsigned int limit)
 137 {
 138         /* Errm.. not sure how to do this.. */
 139 }
 140
 141 static void __init sun4c_init_timers(irq_handler_t counter_fn)
 142 {
 143         const struct linux_prom_irqs *irq;
 144         struct device_node *dp;
 145         const u32 *addr;
 146         int err;
 147
 148         dp = of_find_node_by_name(NULL, "counter-timer");
 149         if (!dp) {
 150                 prom_printf("sun4c_init_timers: Unable to find counter-timer\n");
 151                 prom_halt();
 152         }
 153
 154         addr = of_get_property(dp, "address", NULL);
 155         if (!addr) {
 156                 prom_printf("sun4c_init_timers: No address property\n");
 157                 prom_halt();
 158         }
 159
 160         sun4c_timers = (void __iomem *) (unsigned long) addr[0];
 161
 162         irq = of_get_property(dp, "intr", NULL);
 163         of_node_put(dp);
 164         if (!irq) {
 165                 prom_printf("sun4c_init_timers: No intr property\n");
 166                 prom_halt();
 167         }
 168
 169         /* Have the level 10 timer tick at 100HZ.  We don't touch the
 170          * level 14 timer limit since we are letting the prom handle
 171          * them until we have a real console driver so L1-A works.
 172          */
 173         sbus_writel((((1000000/HZ) + 1) << 10), &sun4c_timers->l10_limit);
 174
 175         master_l10_counter = &sun4c_timers->l10_count;
 176
 177         err = request_irq(irq[0].pri, counter_fn,
 178                           (IRQF_DISABLED | SA_STATIC_ALLOC),
 179                           "timer", NULL);
 180         if (err) {
 181                 prom_printf("sun4c_init_timers: request_irq() fails with %d\n", err);
 182                 prom_halt();
 183         }
 184
 185         sun4c_disable_irq(irq[1].pri);
 186 }
 187
 188 #ifdef CONFIG_SMP
 189 static void sun4c_nop(void) {}
 190 #endif
 191
 192 void __init sun4c_init_IRQ(void)
 193 {
 194         struct device_node *dp;
 195         const u32 *addr;
 196
 197         dp = of_find_node_by_name(NULL, "interrupt-enable");
 198         if (!dp) {
 199                 prom_printf("sun4c_init_IRQ: Unable to find interrupt-enable\n");
 200                 prom_halt();
 201         }
 202
 203         addr = of_get_property(dp, "address", NULL);
 204         of_node_put(dp);
 205         if (!addr) {
 206                 prom_printf("sun4c_init_IRQ: No address property\n");
 207                 prom_halt();
 208         }
 209
 210         interrupt_enable = (void __iomem *) (unsigned long) addr[0];
 211
 212         BTFIXUPSET_CALL(enable_irq, sun4c_enable_irq, BTFIXUPCALL_NORM);
 213         BTFIXUPSET_CALL(disable_irq, sun4c_disable_irq, BTFIXUPCALL_NORM);
 214         BTFIXUPSET_CALL(enable_pil_irq, sun4c_enable_irq, BTFIXUPCALL_NORM);
 215         BTFIXUPSET_CALL(disable_pil_irq, sun4c_disable_irq, BTFIXUPCALL_NORM);
 216         BTFIXUPSET_CALL(clear_clock_irq, sun4c_clear_clock_irq, BTFIXUPCALL_NORM);
 217         BTFIXUPSET_CALL(load_profile_irq, sun4c_load_profile_irq, BTFIXUPCALL_NOP);
 218         sparc_init_timers = sun4c_init_timers;
 219 #ifdef CONFIG_SMP
 220         BTFIXUPSET_CALL(set_cpu_int, sun4c_nop, BTFIXUPCALL_NOP);
 221         BTFIXUPSET_CALL(clear_cpu_int, sun4c_nop, BTFIXUPCALL_NOP);
 222         BTFIXUPSET_CALL(set_irq_udt, sun4c_nop, BTFIXUPCALL_NOP);
 223 #endif
 224         sbus_writeb(SUN4C_INT_ENABLE, interrupt_enable);
 225         /* Cannot enable interrupts until OBP ticker is disabled. */
 226 }