arch/x86/kernel/cpu/mcheck/mce_intel.c

   1 /*
   2  * Intel specific MCE features.
   3  * Copyright 2004 Zwane Mwaikambo <zwane@linuxpower.ca>
   4  * Copyright (C) 2008, 2009 Intel Corporation
   5  * Author: Andi Kleen
   6  */
   7
   8 #include <linux/init.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/percpu.h>
  11 #include <linux/sched.h>
  12 #include <asm/apic.h>
  13 #include <asm/processor.h>
  14 #include <asm/msr.h>
  15 #include <asm/mce.h>
  16
  17 /*
  18  * Support for Intel Correct Machine Check Interrupts. This allows
  19  * the CPU to raise an interrupt when a corrected machine check happened.
  20  * Normally we pick those up using a regular polling timer.
  21  * Also supports reliable discovery of shared banks.
  22  */
  23
  24 static DEFINE_PER_CPU(mce_banks_t, mce_banks_owned);
  25
  26 /*
  27  * cmci_discover_lock protects against parallel discovery attempts
  28  * which could race against each other.
  29  */
  30 static DEFINE_SPINLOCK(cmci_discover_lock);
  31
  32 #define CMCI_THRESHOLD 1
  33
  34 static int cmci_supported(int *banks)
  35 {
  36         u64 cap;
  37
  38         if (mce_cmci_disabled || mce_ignore_ce)
  39                 return 0;
  40
  41         /*
  42          * Vendor check is not strictly needed, but the initial
  43          * initialization is vendor keyed and this
  44          * makes sure none of the backdoors are entered otherwise.
  45          */
  46         if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
  47                 return 0;
  48         if (!cpu_has_apic || lapic_get_maxlvt() < 6)
  49                 return 0;
  50         rdmsrl(MSR_IA32_MCG_CAP, cap);
  51         *banks = min_t(unsigned, MAX_NR_BANKS, cap & 0xff);
  52         return !!(cap & MCG_CMCI_P);
  53 }
  54
  55 /*
  56  * The interrupt handler. This is called on every event.
  57  * Just call the poller directly to log any events.
  58  * This could in theory increase the threshold under high load,
  59  * but doesn't for now.
  60  */
  61 static void intel_threshold_interrupt(void)
  62 {
  63         machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned));
  64         mce_notify_irq();
  65 }
  66
  67 static void print_update(char *type, int *hdr, int num)
  68 {
  69         if (*hdr == 0)
  70                 printk(KERN_INFO "CPU %d MCA banks", smp_processor_id());
  71         *hdr = 1;
  72         printk(KERN_CONT " %s:%d", type, num);
  73 }
  74
  75 /*
  76  * Enable CMCI (Corrected Machine Check Interrupt) for available MCE banks
  77  * on this CPU. Use the algorithm recommended in the SDM to discover shared
  78  * banks.
  79  */
  80 static void cmci_discover(int banks, int boot)
  81 {
  82         unsigned long *owned = (void *)&__get_cpu_var(mce_banks_owned);
  83         unsigned long flags;
  84         int hdr = 0;
  85         int i;
  86
  87         spin_lock_irqsave(&cmci_discover_lock, flags);
  88         for (i = 0; i < banks; i++) {
  89                 u64 val;
  90
  91                 if (test_bit(i, owned))
  92                         continue;
  93
  94                 rdmsrl(MSR_IA32_MCx_CTL2(i), val);
  95
  96                 /* Already owned by someone else? */
  97                 if (val & CMCI_EN) {
  98                         if (test_and_clear_bit(i, owned) || boot)
  99                                 print_update("SHD", &hdr, i);
 100                         __clear_bit(i, __get_cpu_var(mce_poll_banks));
 101                         continue;
 102                 }
 103
 104                 val |= CMCI_EN | CMCI_THRESHOLD;
 105                 wrmsrl(MSR_IA32_MCx_CTL2(i), val);
 106                 rdmsrl(MSR_IA32_MCx_CTL2(i), val);
 107
 108                 /* Did the enable bit stick? -- the bank supports CMCI */
 109                 if (val & CMCI_EN) {
 110                         if (!test_and_set_bit(i, owned) || boot)
 111                                 print_update("CMCI", &hdr, i);
 112                         __clear_bit(i, __get_cpu_var(mce_poll_banks));
 113                 } else {
 114                         WARN_ON(!test_bit(i, __get_cpu_var(mce_poll_banks)));
 115                 }
 116         }
 117         spin_unlock_irqrestore(&cmci_discover_lock, flags);
 118         if (hdr)
 119                 printk(KERN_CONT "\n");
 120 }
 121
 122 /*
 123  * Just in case we missed an event during initialization check
 124  * all the CMCI owned banks.
 125  */
 126 void cmci_recheck(void)
 127 {
 128         unsigned long flags;
 129         int banks;
 130
 131         if (!mce_available(&current_cpu_data) || !cmci_supported(&banks))
 132                 return;
 133         local_irq_save(flags);
 134         machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned));
 135         local_irq_restore(flags);
 136 }
 137
 138 /*
 139  * Disable CMCI on this CPU for all banks it owns when it goes down.
 140  * This allows other CPUs to claim the banks on rediscovery.
 141  */
 142 void cmci_clear(void)
 143 {
 144         unsigned long flags;
 145         int i;
 146         int banks;
 147         u64 val;
 148
 149         if (!cmci_supported(&banks))
 150                 return;
 151         spin_lock_irqsave(&cmci_discover_lock, flags);
 152         for (i = 0; i < banks; i++) {
 153                 if (!test_bit(i, __get_cpu_var(mce_banks_owned)))
 154                         continue;
 155                 /* Disable CMCI */
 156                 rdmsrl(MSR_IA32_MCx_CTL2(i), val);
 157                 val &= ~(CMCI_EN|CMCI_THRESHOLD_MASK);
 158                 wrmsrl(MSR_IA32_MCx_CTL2(i), val);
 159                 __clear_bit(i, __get_cpu_var(mce_banks_owned));
 160         }
 161         spin_unlock_irqrestore(&cmci_discover_lock, flags);
 162 }
 163
 164 /*
 165  * After a CPU went down cycle through all the others and rediscover
 166  * Must run in process context.
 167  */
 168 void cmci_rediscover(int dying)
 169 {
 170         int banks;
 171         int cpu;
 172         cpumask_var_t old;
 173
 174         if (!cmci_supported(&banks))
 175                 return;
 176         if (!alloc_cpumask_var(&old, GFP_KERNEL))
 177                 return;
 178         cpumask_copy(old, &current->cpus_allowed);
 179
 180         for_each_online_cpu(cpu) {
 181                 if (cpu == dying)
 182                         continue;
 183                 if (set_cpus_allowed_ptr(current, cpumask_of(cpu)))
 184                         continue;
 185                 /* Recheck banks in case CPUs don't all have the same */
 186                 if (cmci_supported(&banks))
 187                         cmci_discover(banks, 0);
 188         }
 189
 190         set_cpus_allowed_ptr(current, old);
 191         free_cpumask_var(old);
 192 }
 193
 194 /*
 195  * Reenable CMCI on this CPU in case a CPU down failed.
 196  */
 197 void cmci_reenable(void)
 198 {
 199         int banks;
 200         if (cmci_supported(&banks))
 201                 cmci_discover(banks, 0);
 202 }
 203
 204 static void intel_init_cmci(void)
 205 {
 206         int banks;
 207
 208         if (!cmci_supported(&banks))
 209                 return;
 210
 211         mce_threshold_vector = intel_threshold_interrupt;
 212         cmci_discover(banks, 1);
 213         /*
 214          * For CPU #0 this runs with still disabled APIC, but that's
 215          * ok because only the vector is set up. We still do another
 216          * check for the banks later for CPU #0 just to make sure
 217          * to not miss any events.
 218          */
 219         apic_write(APIC_LVTCMCI, THRESHOLD_APIC_VECTOR|APIC_DM_FIXED);
 220         cmci_recheck();
 221 }
 222
 223 void mce_intel_feature_init(struct cpuinfo_x86 *c)
 224 {
 225         intel_init_thermal(c);
 226         intel_init_cmci();
 227 }