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Full support for Ginger Console
[linux-ginger.git] / arch / x86 / kvm / svm.c
blobc17404add91febfd66d12570057a12695e972d9b
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
16 #include <linux/kvm_host.h>
17
18 #include "irq.h"
19 #include "mmu.h"
20 #include "kvm_cache_regs.h"
21 #include "x86.h"
22
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/vmalloc.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/ftrace_event.h>
29
30 #include <asm/desc.h>
31
32 #include <asm/virtext.h>
33 #include "trace.h"
34
35 #define __ex(x) __kvm_handle_fault_on_reboot(x)
36
37 MODULE_AUTHOR("Qumranet");
38 MODULE_LICENSE("GPL");
39
40 #define IOPM_ALLOC_ORDER 2
41 #define MSRPM_ALLOC_ORDER 1
42
43 #define SEG_TYPE_LDT 2
44 #define SEG_TYPE_BUSY_TSS16 3
45
46 #define SVM_FEATURE_NPT (1 << 0)
47 #define SVM_FEATURE_LBRV (1 << 1)
48 #define SVM_FEATURE_SVML (1 << 2)
49
50 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
51 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
52 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
53
54 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
55
56 /* Turn on to get debugging output*/
57 /* #define NESTED_DEBUG */
58
59 #ifdef NESTED_DEBUG
60 #define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
61 #else
62 #define nsvm_printk(fmt, args...) do {} while(0)
63 #endif
64
65 static const u32 host_save_user_msrs[] = {
66 #ifdef CONFIG_X86_64
67 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
68 MSR_FS_BASE,
69 #endif
70 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
71 };
72
73 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
74
75 struct kvm_vcpu;
76
77 struct nested_state {
78 struct vmcb *hsave;
79 u64 hsave_msr;
80 u64 vmcb;
81
82 /* These are the merged vectors */
83 u32 *msrpm;
84
85 /* gpa pointers to the real vectors */
86 u64 vmcb_msrpm;
87
88 /* cache for intercepts of the guest */
89 u16 intercept_cr_read;
90 u16 intercept_cr_write;
91 u16 intercept_dr_read;
92 u16 intercept_dr_write;
93 u32 intercept_exceptions;
94 u64 intercept;
95
96 };
97
98 struct vcpu_svm {
99 struct kvm_vcpu vcpu;
100 struct vmcb *vmcb;
101 unsigned long vmcb_pa;
102 struct svm_cpu_data *svm_data;
103 uint64_t asid_generation;
104 uint64_t sysenter_esp;
105 uint64_t sysenter_eip;
106
107 u64 next_rip;
108
109 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
110 u64 host_gs_base;
111
112 u32 *msrpm;
113
114 struct nested_state nested;
115 };
116
117 /* enable NPT for AMD64 and X86 with PAE */
118 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
119 static bool npt_enabled = true;
120 #else
121 static bool npt_enabled = false;
122 #endif
123 static int npt = 1;
124
125 module_param(npt, int, S_IRUGO);
126
127 static int nested = 1;
128 module_param(nested, int, S_IRUGO);
129
130 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
131 static void svm_complete_interrupts(struct vcpu_svm *svm);
132
133 static int nested_svm_exit_handled(struct vcpu_svm *svm);
134 static int nested_svm_vmexit(struct vcpu_svm *svm);
135 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
136 bool has_error_code, u32 error_code);
137
138 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
139 {
140 return container_of(vcpu, struct vcpu_svm, vcpu);
141 }
142
143 static inline bool is_nested(struct vcpu_svm *svm)
144 {
145 return svm->nested.vmcb;
146 }
147
148 static inline void enable_gif(struct vcpu_svm *svm)
149 {
150 svm->vcpu.arch.hflags |= HF_GIF_MASK;
151 }
152
153 static inline void disable_gif(struct vcpu_svm *svm)
154 {
155 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
156 }
157
158 static inline bool gif_set(struct vcpu_svm *svm)
159 {
160 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
161 }
162
163 static unsigned long iopm_base;
164
165 struct kvm_ldttss_desc {
166 u16 limit0;
167 u16 base0;
168 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
169 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
170 u32 base3;
171 u32 zero1;
172 } __attribute__((packed));
173
174 struct svm_cpu_data {
175 int cpu;
176
177 u64 asid_generation;
178 u32 max_asid;
179 u32 next_asid;
180 struct kvm_ldttss_desc *tss_desc;
181
182 struct page *save_area;
183 };
184
185 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
186 static uint32_t svm_features;
187
188 struct svm_init_data {
189 int cpu;
190 int r;
191 };
192
193 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
194
195 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
196 #define MSRS_RANGE_SIZE 2048
197 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
198
199 #define MAX_INST_SIZE 15
200
201 static inline u32 svm_has(u32 feat)
202 {
203 return svm_features & feat;
204 }
205
206 static inline void clgi(void)
207 {
208 asm volatile (__ex(SVM_CLGI));
209 }
210
211 static inline void stgi(void)
212 {
213 asm volatile (__ex(SVM_STGI));
214 }
215
216 static inline void invlpga(unsigned long addr, u32 asid)
217 {
218 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
219 }
220
221 static inline void force_new_asid(struct kvm_vcpu *vcpu)
222 {
223 to_svm(vcpu)->asid_generation--;
224 }
225
226 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
227 {
228 force_new_asid(vcpu);
229 }
230
231 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
232 {
233 if (!npt_enabled && !(efer & EFER_LMA))
234 efer &= ~EFER_LME;
235
236 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
237 vcpu->arch.shadow_efer = efer;
238 }
239
240 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
241 bool has_error_code, u32 error_code)
242 {
243 struct vcpu_svm *svm = to_svm(vcpu);
244
245 /* If we are within a nested VM we'd better #VMEXIT and let the
246 guest handle the exception */
247 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
248 return;
249
250 svm->vmcb->control.event_inj = nr
251 | SVM_EVTINJ_VALID
252 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
253 | SVM_EVTINJ_TYPE_EXEPT;
254 svm->vmcb->control.event_inj_err = error_code;
255 }
256
257 static int is_external_interrupt(u32 info)
258 {
259 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
260 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
261 }
262
263 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
264 {
265 struct vcpu_svm *svm = to_svm(vcpu);
266 u32 ret = 0;
267
268 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
269 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
270 return ret & mask;
271 }
272
273 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
274 {
275 struct vcpu_svm *svm = to_svm(vcpu);
276
277 if (mask == 0)
278 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
279 else
280 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
281
282 }
283
284 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
285 {
286 struct vcpu_svm *svm = to_svm(vcpu);
287
288 if (!svm->next_rip) {
289 if (emulate_instruction(vcpu, vcpu->run, 0, 0, EMULTYPE_SKIP) !=
290 EMULATE_DONE)
291 printk(KERN_DEBUG "%s: NOP\n", __func__);
292 return;
293 }
294 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
295 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
296 __func__, kvm_rip_read(vcpu), svm->next_rip);
297
298 kvm_rip_write(vcpu, svm->next_rip);
299 svm_set_interrupt_shadow(vcpu, 0);
300 }
301
302 static int has_svm(void)
303 {
304 const char *msg;
305
306 if (!cpu_has_svm(&msg)) {
307 printk(KERN_INFO "has_svm: %s\n", msg);
308 return 0;
309 }
310
311 return 1;
312 }
313
314 static void svm_hardware_disable(void *garbage)
315 {
316 cpu_svm_disable();
317 }
318
319 static void svm_hardware_enable(void *garbage)
320 {
321
322 struct svm_cpu_data *svm_data;
323 uint64_t efer;
324 struct descriptor_table gdt_descr;
325 struct desc_struct *gdt;
326 int me = raw_smp_processor_id();
327
328 if (!has_svm()) {
329 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
330 return;
331 }
332 svm_data = per_cpu(svm_data, me);
333
334 if (!svm_data) {
335 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
336 me);
337 return;
338 }
339
340 svm_data->asid_generation = 1;
341 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
342 svm_data->next_asid = svm_data->max_asid + 1;
343
344 kvm_get_gdt(&gdt_descr);
345 gdt = (struct desc_struct *)gdt_descr.base;
346 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
347
348 rdmsrl(MSR_EFER, efer);
349 wrmsrl(MSR_EFER, efer | EFER_SVME);
350
351 wrmsrl(MSR_VM_HSAVE_PA,
352 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
353 }
354
355 static void svm_cpu_uninit(int cpu)
356 {
357 struct svm_cpu_data *svm_data
358 = per_cpu(svm_data, raw_smp_processor_id());
359
360 if (!svm_data)
361 return;
362
363 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
364 __free_page(svm_data->save_area);
365 kfree(svm_data);
366 }
367
368 static int svm_cpu_init(int cpu)
369 {
370 struct svm_cpu_data *svm_data;
371 int r;
372
373 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
374 if (!svm_data)
375 return -ENOMEM;
376 svm_data->cpu = cpu;
377 svm_data->save_area = alloc_page(GFP_KERNEL);
378 r = -ENOMEM;
379 if (!svm_data->save_area)
380 goto err_1;
381
382 per_cpu(svm_data, cpu) = svm_data;
383
384 return 0;
385
386 err_1:
387 kfree(svm_data);
388 return r;
389
390 }
391
392 static void set_msr_interception(u32 *msrpm, unsigned msr,
393 int read, int write)
394 {
395 int i;
396
397 for (i = 0; i < NUM_MSR_MAPS; i++) {
398 if (msr >= msrpm_ranges[i] &&
399 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
400 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
401 msrpm_ranges[i]) * 2;
402
403 u32 *base = msrpm + (msr_offset / 32);
404 u32 msr_shift = msr_offset % 32;
405 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
406 *base = (*base & ~(0x3 << msr_shift)) |
407 (mask << msr_shift);
408 return;
409 }
410 }
411 BUG();
412 }
413
414 static void svm_vcpu_init_msrpm(u32 *msrpm)
415 {
416 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
417
418 #ifdef CONFIG_X86_64
419 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
420 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
421 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
422 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
423 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
424 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
425 #endif
426 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
427 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
428 }
429
430 static void svm_enable_lbrv(struct vcpu_svm *svm)
431 {
432 u32 *msrpm = svm->msrpm;
433
434 svm->vmcb->control.lbr_ctl = 1;
435 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
436 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
437 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
438 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
439 }
440
441 static void svm_disable_lbrv(struct vcpu_svm *svm)
442 {
443 u32 *msrpm = svm->msrpm;
444
445 svm->vmcb->control.lbr_ctl = 0;
446 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
447 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
448 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
449 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
450 }
451
452 static __init int svm_hardware_setup(void)
453 {
454 int cpu;
455 struct page *iopm_pages;
456 void *iopm_va;
457 int r;
458
459 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
460
461 if (!iopm_pages)
462 return -ENOMEM;
463
464 iopm_va = page_address(iopm_pages);
465 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
466 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
467
468 if (boot_cpu_has(X86_FEATURE_NX))
469 kvm_enable_efer_bits(EFER_NX);
470
471 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
472 kvm_enable_efer_bits(EFER_FFXSR);
473
474 if (nested) {
475 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
476 kvm_enable_efer_bits(EFER_SVME);
477 }
478
479 for_each_online_cpu(cpu) {
480 r = svm_cpu_init(cpu);
481 if (r)
482 goto err;
483 }
484
485 svm_features = cpuid_edx(SVM_CPUID_FUNC);
486
487 if (!svm_has(SVM_FEATURE_NPT))
488 npt_enabled = false;
489
490 if (npt_enabled && !npt) {
491 printk(KERN_INFO "kvm: Nested Paging disabled\n");
492 npt_enabled = false;
493 }
494
495 if (npt_enabled) {
496 printk(KERN_INFO "kvm: Nested Paging enabled\n");
497 kvm_enable_tdp();
498 } else
499 kvm_disable_tdp();
500
501 return 0;
502
503 err:
504 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
505 iopm_base = 0;
506 return r;
507 }
508
509 static __exit void svm_hardware_unsetup(void)
510 {
511 int cpu;
512
513 for_each_online_cpu(cpu)
514 svm_cpu_uninit(cpu);
515
516 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
517 iopm_base = 0;
518 }
519
520 static void init_seg(struct vmcb_seg *seg)
521 {
522 seg->selector = 0;
523 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
524 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
525 seg->limit = 0xffff;
526 seg->base = 0;
527 }
528
529 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
530 {
531 seg->selector = 0;
532 seg->attrib = SVM_SELECTOR_P_MASK | type;
533 seg->limit = 0xffff;
534 seg->base = 0;
535 }
536
537 static void init_vmcb(struct vcpu_svm *svm)
538 {
539 struct vmcb_control_area *control = &svm->vmcb->control;
540 struct vmcb_save_area *save = &svm->vmcb->save;
541
542 control->intercept_cr_read = INTERCEPT_CR0_MASK |
543 INTERCEPT_CR3_MASK |
544 INTERCEPT_CR4_MASK;
545
546 control->intercept_cr_write = INTERCEPT_CR0_MASK |
547 INTERCEPT_CR3_MASK |
548 INTERCEPT_CR4_MASK |
549 INTERCEPT_CR8_MASK;
550
551 control->intercept_dr_read = INTERCEPT_DR0_MASK |
552 INTERCEPT_DR1_MASK |
553 INTERCEPT_DR2_MASK |
554 INTERCEPT_DR3_MASK;
555
556 control->intercept_dr_write = INTERCEPT_DR0_MASK |
557 INTERCEPT_DR1_MASK |
558 INTERCEPT_DR2_MASK |
559 INTERCEPT_DR3_MASK |
560 INTERCEPT_DR5_MASK |
561 INTERCEPT_DR7_MASK;
562
563 control->intercept_exceptions = (1 << PF_VECTOR) |
564 (1 << UD_VECTOR) |
565 (1 << MC_VECTOR);
566
567
568 control->intercept = (1ULL << INTERCEPT_INTR) |
569 (1ULL << INTERCEPT_NMI) |
570 (1ULL << INTERCEPT_SMI) |
571 (1ULL << INTERCEPT_CPUID) |
572 (1ULL << INTERCEPT_INVD) |
573 (1ULL << INTERCEPT_HLT) |
574 (1ULL << INTERCEPT_INVLPG) |
575 (1ULL << INTERCEPT_INVLPGA) |
576 (1ULL << INTERCEPT_IOIO_PROT) |
577 (1ULL << INTERCEPT_MSR_PROT) |
578 (1ULL << INTERCEPT_TASK_SWITCH) |
579 (1ULL << INTERCEPT_SHUTDOWN) |
580 (1ULL << INTERCEPT_VMRUN) |
581 (1ULL << INTERCEPT_VMMCALL) |
582 (1ULL << INTERCEPT_VMLOAD) |
583 (1ULL << INTERCEPT_VMSAVE) |
584 (1ULL << INTERCEPT_STGI) |
585 (1ULL << INTERCEPT_CLGI) |
586 (1ULL << INTERCEPT_SKINIT) |
587 (1ULL << INTERCEPT_WBINVD) |
588 (1ULL << INTERCEPT_MONITOR) |
589 (1ULL << INTERCEPT_MWAIT);
590
591 control->iopm_base_pa = iopm_base;
592 control->msrpm_base_pa = __pa(svm->msrpm);
593 control->tsc_offset = 0;
594 control->int_ctl = V_INTR_MASKING_MASK;
595
596 init_seg(&save->es);
597 init_seg(&save->ss);
598 init_seg(&save->ds);
599 init_seg(&save->fs);
600 init_seg(&save->gs);
601
602 save->cs.selector = 0xf000;
603 /* Executable/Readable Code Segment */
604 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
605 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
606 save->cs.limit = 0xffff;
607 /*
608 * cs.base should really be 0xffff0000, but vmx can't handle that, so
609 * be consistent with it.
610 *
611 * Replace when we have real mode working for vmx.
612 */
613 save->cs.base = 0xf0000;
614
615 save->gdtr.limit = 0xffff;
616 save->idtr.limit = 0xffff;
617
618 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
619 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
620
621 save->efer = EFER_SVME;
622 save->dr6 = 0xffff0ff0;
623 save->dr7 = 0x400;
624 save->rflags = 2;
625 save->rip = 0x0000fff0;
626 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
627
628 /*
629 * cr0 val on cpu init should be 0x60000010, we enable cpu
630 * cache by default. the orderly way is to enable cache in bios.
631 */
632 save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
633 save->cr4 = X86_CR4_PAE;
634 /* rdx = ?? */
635
636 if (npt_enabled) {
637 /* Setup VMCB for Nested Paging */
638 control->nested_ctl = 1;
639 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
640 (1ULL << INTERCEPT_INVLPG));
641 control->intercept_exceptions &= ~(1 << PF_VECTOR);
642 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
643 INTERCEPT_CR3_MASK);
644 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
645 INTERCEPT_CR3_MASK);
646 save->g_pat = 0x0007040600070406ULL;
647 /* enable caching because the QEMU Bios doesn't enable it */
648 save->cr0 = X86_CR0_ET;
649 save->cr3 = 0;
650 save->cr4 = 0;
651 }
652 force_new_asid(&svm->vcpu);
653
654 svm->nested.vmcb = 0;
655 svm->vcpu.arch.hflags = 0;
656
657 enable_gif(svm);
658 }
659
660 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
661 {
662 struct vcpu_svm *svm = to_svm(vcpu);
663
664 init_vmcb(svm);
665
666 if (!kvm_vcpu_is_bsp(vcpu)) {
667 kvm_rip_write(vcpu, 0);
668 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
669 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
670 }
671 vcpu->arch.regs_avail = ~0;
672 vcpu->arch.regs_dirty = ~0;
673
674 return 0;
675 }
676
677 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
678 {
679 struct vcpu_svm *svm;
680 struct page *page;
681 struct page *msrpm_pages;
682 struct page *hsave_page;
683 struct page *nested_msrpm_pages;
684 int err;
685
686 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
687 if (!svm) {
688 err = -ENOMEM;
689 goto out;
690 }
691
692 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
693 if (err)
694 goto free_svm;
695
696 page = alloc_page(GFP_KERNEL);
697 if (!page) {
698 err = -ENOMEM;
699 goto uninit;
700 }
701
702 err = -ENOMEM;
703 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
704 if (!msrpm_pages)
705 goto uninit;
706
707 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
708 if (!nested_msrpm_pages)
709 goto uninit;
710
711 svm->msrpm = page_address(msrpm_pages);
712 svm_vcpu_init_msrpm(svm->msrpm);
713
714 hsave_page = alloc_page(GFP_KERNEL);
715 if (!hsave_page)
716 goto uninit;
717 svm->nested.hsave = page_address(hsave_page);
718
719 svm->nested.msrpm = page_address(nested_msrpm_pages);
720
721 svm->vmcb = page_address(page);
722 clear_page(svm->vmcb);
723 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
724 svm->asid_generation = 0;
725 init_vmcb(svm);
726
727 fx_init(&svm->vcpu);
728 svm->vcpu.fpu_active = 1;
729 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
730 if (kvm_vcpu_is_bsp(&svm->vcpu))
731 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
732
733 return &svm->vcpu;
734
735 uninit:
736 kvm_vcpu_uninit(&svm->vcpu);
737 free_svm:
738 kmem_cache_free(kvm_vcpu_cache, svm);
739 out:
740 return ERR_PTR(err);
741 }
742
743 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
744 {
745 struct vcpu_svm *svm = to_svm(vcpu);
746
747 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
748 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
749 __free_page(virt_to_page(svm->nested.hsave));
750 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
751 kvm_vcpu_uninit(vcpu);
752 kmem_cache_free(kvm_vcpu_cache, svm);
753 }
754
755 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
756 {
757 struct vcpu_svm *svm = to_svm(vcpu);
758 int i;
759
760 if (unlikely(cpu != vcpu->cpu)) {
761 u64 tsc_this, delta;
762
763 /*
764 * Make sure that the guest sees a monotonically
765 * increasing TSC.
766 */
767 rdtscll(tsc_this);
768 delta = vcpu->arch.host_tsc - tsc_this;
769 svm->vmcb->control.tsc_offset += delta;
770 if (is_nested(svm))
771 svm->nested.hsave->control.tsc_offset += delta;
772 vcpu->cpu = cpu;
773 kvm_migrate_timers(vcpu);
774 svm->asid_generation = 0;
775 }
776
777 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
778 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
779 }
780
781 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
782 {
783 struct vcpu_svm *svm = to_svm(vcpu);
784 int i;
785
786 ++vcpu->stat.host_state_reload;
787 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
788 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
789
790 rdtscll(vcpu->arch.host_tsc);
791 }
792
793 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
794 {
795 return to_svm(vcpu)->vmcb->save.rflags;
796 }
797
798 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
799 {
800 to_svm(vcpu)->vmcb->save.rflags = rflags;
801 }
802
803 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
804 {
805 switch (reg) {
806 case VCPU_EXREG_PDPTR:
807 BUG_ON(!npt_enabled);
808 load_pdptrs(vcpu, vcpu->arch.cr3);
809 break;
810 default:
811 BUG();
812 }
813 }
814
815 static void svm_set_vintr(struct vcpu_svm *svm)
816 {
817 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
818 }
819
820 static void svm_clear_vintr(struct vcpu_svm *svm)
821 {
822 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
823 }
824
825 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
826 {
827 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
828
829 switch (seg) {
830 case VCPU_SREG_CS: return &save->cs;
831 case VCPU_SREG_DS: return &save->ds;
832 case VCPU_SREG_ES: return &save->es;
833 case VCPU_SREG_FS: return &save->fs;
834 case VCPU_SREG_GS: return &save->gs;
835 case VCPU_SREG_SS: return &save->ss;
836 case VCPU_SREG_TR: return &save->tr;
837 case VCPU_SREG_LDTR: return &save->ldtr;
838 }
839 BUG();
840 return NULL;
841 }
842
843 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
844 {
845 struct vmcb_seg *s = svm_seg(vcpu, seg);
846
847 return s->base;
848 }
849
850 static void svm_get_segment(struct kvm_vcpu *vcpu,
851 struct kvm_segment *var, int seg)
852 {
853 struct vmcb_seg *s = svm_seg(vcpu, seg);
854
855 var->base = s->base;
856 var->limit = s->limit;
857 var->selector = s->selector;
858 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
859 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
860 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
861 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
862 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
863 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
864 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
865 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
866
867 /* AMD's VMCB does not have an explicit unusable field, so emulate it
868 * for cross vendor migration purposes by "not present"
869 */
870 var->unusable = !var->present || (var->type == 0);
871
872 switch (seg) {
873 case VCPU_SREG_CS:
874 /*
875 * SVM always stores 0 for the 'G' bit in the CS selector in
876 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
877 * Intel's VMENTRY has a check on the 'G' bit.
878 */
879 var->g = s->limit > 0xfffff;
880 break;
881 case VCPU_SREG_TR:
882 /*
883 * Work around a bug where the busy flag in the tr selector
884 * isn't exposed
885 */
886 var->type |= 0x2;
887 break;
888 case VCPU_SREG_DS:
889 case VCPU_SREG_ES:
890 case VCPU_SREG_FS:
891 case VCPU_SREG_GS:
892 /*
893 * The accessed bit must always be set in the segment
894 * descriptor cache, although it can be cleared in the
895 * descriptor, the cached bit always remains at 1. Since
896 * Intel has a check on this, set it here to support
897 * cross-vendor migration.
898 */
899 if (!var->unusable)
900 var->type |= 0x1;
901 break;
902 case VCPU_SREG_SS:
903 /* On AMD CPUs sometimes the DB bit in the segment
904 * descriptor is left as 1, although the whole segment has
905 * been made unusable. Clear it here to pass an Intel VMX
906 * entry check when cross vendor migrating.
907 */
908 if (var->unusable)
909 var->db = 0;
910 break;
911 }
912 }
913
914 static int svm_get_cpl(struct kvm_vcpu *vcpu)
915 {
916 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
917
918 return save->cpl;
919 }
920
921 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
922 {
923 struct vcpu_svm *svm = to_svm(vcpu);
924
925 dt->limit = svm->vmcb->save.idtr.limit;
926 dt->base = svm->vmcb->save.idtr.base;
927 }
928
929 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
930 {
931 struct vcpu_svm *svm = to_svm(vcpu);
932
933 svm->vmcb->save.idtr.limit = dt->limit;
934 svm->vmcb->save.idtr.base = dt->base ;
935 }
936
937 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
938 {
939 struct vcpu_svm *svm = to_svm(vcpu);
940
941 dt->limit = svm->vmcb->save.gdtr.limit;
942 dt->base = svm->vmcb->save.gdtr.base;
943 }
944
945 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
946 {
947 struct vcpu_svm *svm = to_svm(vcpu);
948
949 svm->vmcb->save.gdtr.limit = dt->limit;
950 svm->vmcb->save.gdtr.base = dt->base ;
951 }
952
953 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
954 {
955 }
956
957 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
958 {
959 struct vcpu_svm *svm = to_svm(vcpu);
960
961 #ifdef CONFIG_X86_64
962 if (vcpu->arch.shadow_efer & EFER_LME) {
963 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
964 vcpu->arch.shadow_efer |= EFER_LMA;
965 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
966 }
967
968 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
969 vcpu->arch.shadow_efer &= ~EFER_LMA;
970 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
971 }
972 }
973 #endif
974 if (npt_enabled)
975 goto set;
976
977 if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
978 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
979 vcpu->fpu_active = 1;
980 }
981
982 vcpu->arch.cr0 = cr0;
983 cr0 |= X86_CR0_PG | X86_CR0_WP;
984 if (!vcpu->fpu_active) {
985 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
986 cr0 |= X86_CR0_TS;
987 }
988 set:
989 /*
990 * re-enable caching here because the QEMU bios
991 * does not do it - this results in some delay at
992 * reboot
993 */
994 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
995 svm->vmcb->save.cr0 = cr0;
996 }
997
998 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
999 {
1000 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1001 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1002
1003 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1004 force_new_asid(vcpu);
1005
1006 vcpu->arch.cr4 = cr4;
1007 if (!npt_enabled)
1008 cr4 |= X86_CR4_PAE;
1009 cr4 |= host_cr4_mce;
1010 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1011 }
1012
1013 static void svm_set_segment(struct kvm_vcpu *vcpu,
1014 struct kvm_segment *var, int seg)
1015 {
1016 struct vcpu_svm *svm = to_svm(vcpu);
1017 struct vmcb_seg *s = svm_seg(vcpu, seg);
1018
1019 s->base = var->base;
1020 s->limit = var->limit;
1021 s->selector = var->selector;
1022 if (var->unusable)
1023 s->attrib = 0;
1024 else {
1025 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1026 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1027 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1028 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1029 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1030 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1031 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1032 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1033 }
1034 if (seg == VCPU_SREG_CS)
1035 svm->vmcb->save.cpl
1036 = (svm->vmcb->save.cs.attrib
1037 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1038
1039 }
1040
1041 static void update_db_intercept(struct kvm_vcpu *vcpu)
1042 {
1043 struct vcpu_svm *svm = to_svm(vcpu);
1044
1045 svm->vmcb->control.intercept_exceptions &=
1046 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1047
1048 if (vcpu->arch.singlestep)
1049 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1050
1051 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1052 if (vcpu->guest_debug &
1053 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1054 svm->vmcb->control.intercept_exceptions |=
1055 1 << DB_VECTOR;
1056 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1057 svm->vmcb->control.intercept_exceptions |=
1058 1 << BP_VECTOR;
1059 } else
1060 vcpu->guest_debug = 0;
1061 }
1062
1063 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1064 {
1065 int old_debug = vcpu->guest_debug;
1066 struct vcpu_svm *svm = to_svm(vcpu);
1067
1068 vcpu->guest_debug = dbg->control;
1069
1070 update_db_intercept(vcpu);
1071
1072 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1073 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1074 else
1075 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1076
1077 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1078 svm->vmcb->save.rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1079 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1080 svm->vmcb->save.rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1081
1082 return 0;
1083 }
1084
1085 static void load_host_msrs(struct kvm_vcpu *vcpu)
1086 {
1087 #ifdef CONFIG_X86_64
1088 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1089 #endif
1090 }
1091
1092 static void save_host_msrs(struct kvm_vcpu *vcpu)
1093 {
1094 #ifdef CONFIG_X86_64
1095 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1096 #endif
1097 }
1098
1099 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
1100 {
1101 if (svm_data->next_asid > svm_data->max_asid) {
1102 ++svm_data->asid_generation;
1103 svm_data->next_asid = 1;
1104 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1105 }
1106
1107 svm->asid_generation = svm_data->asid_generation;
1108 svm->vmcb->control.asid = svm_data->next_asid++;
1109 }
1110
1111 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1112 {
1113 struct vcpu_svm *svm = to_svm(vcpu);
1114 unsigned long val;
1115
1116 switch (dr) {
1117 case 0 ... 3:
1118 val = vcpu->arch.db[dr];
1119 break;
1120 case 6:
1121 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1122 val = vcpu->arch.dr6;
1123 else
1124 val = svm->vmcb->save.dr6;
1125 break;
1126 case 7:
1127 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1128 val = vcpu->arch.dr7;
1129 else
1130 val = svm->vmcb->save.dr7;
1131 break;
1132 default:
1133 val = 0;
1134 }
1135
1136 return val;
1137 }
1138
1139 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1140 int *exception)
1141 {
1142 struct vcpu_svm *svm = to_svm(vcpu);
1143
1144 *exception = 0;
1145
1146 switch (dr) {
1147 case 0 ... 3:
1148 vcpu->arch.db[dr] = value;
1149 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1150 vcpu->arch.eff_db[dr] = value;
1151 return;
1152 case 4 ... 5:
1153 if (vcpu->arch.cr4 & X86_CR4_DE)
1154 *exception = UD_VECTOR;
1155 return;
1156 case 6:
1157 if (value & 0xffffffff00000000ULL) {
1158 *exception = GP_VECTOR;
1159 return;
1160 }
1161 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1162 return;
1163 case 7:
1164 if (value & 0xffffffff00000000ULL) {
1165 *exception = GP_VECTOR;
1166 return;
1167 }
1168 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1169 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1170 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1171 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1172 }
1173 return;
1174 default:
1175 /* FIXME: Possible case? */
1176 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1177 __func__, dr);
1178 *exception = UD_VECTOR;
1179 return;
1180 }
1181 }
1182
1183 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1184 {
1185 u64 fault_address;
1186 u32 error_code;
1187
1188 fault_address = svm->vmcb->control.exit_info_2;
1189 error_code = svm->vmcb->control.exit_info_1;
1190
1191 trace_kvm_page_fault(fault_address, error_code);
1192 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1193 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1194 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1195 }
1196
1197 static int db_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1198 {
1199 if (!(svm->vcpu.guest_debug &
1200 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1201 !svm->vcpu.arch.singlestep) {
1202 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1203 return 1;
1204 }
1205
1206 if (svm->vcpu.arch.singlestep) {
1207 svm->vcpu.arch.singlestep = false;
1208 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1209 svm->vmcb->save.rflags &=
1210 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1211 update_db_intercept(&svm->vcpu);
1212 }
1213
1214 if (svm->vcpu.guest_debug &
1215 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1216 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1217 kvm_run->debug.arch.pc =
1218 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1219 kvm_run->debug.arch.exception = DB_VECTOR;
1220 return 0;
1221 }
1222
1223 return 1;
1224 }
1225
1226 static int bp_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1227 {
1228 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1229 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1230 kvm_run->debug.arch.exception = BP_VECTOR;
1231 return 0;
1232 }
1233
1234 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1235 {
1236 int er;
1237
1238 er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1239 if (er != EMULATE_DONE)
1240 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1241 return 1;
1242 }
1243
1244 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1245 {
1246 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1247 if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1248 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1249 svm->vcpu.fpu_active = 1;
1250
1251 return 1;
1252 }
1253
1254 static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1255 {
1256 /*
1257 * On an #MC intercept the MCE handler is not called automatically in
1258 * the host. So do it by hand here.
1259 */
1260 asm volatile (
1261 "int $0x12\n");
1262 /* not sure if we ever come back to this point */
1263
1264 return 1;
1265 }
1266
1267 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1268 {
1269 /*
1270 * VMCB is undefined after a SHUTDOWN intercept
1271 * so reinitialize it.
1272 */
1273 clear_page(svm->vmcb);
1274 init_vmcb(svm);
1275
1276 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1277 return 0;
1278 }
1279
1280 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1281 {
1282 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1283 int size, in, string;
1284 unsigned port;
1285
1286 ++svm->vcpu.stat.io_exits;
1287
1288 svm->next_rip = svm->vmcb->control.exit_info_2;
1289
1290 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1291
1292 if (string) {
1293 if (emulate_instruction(&svm->vcpu,
1294 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1295 return 0;
1296 return 1;
1297 }
1298
1299 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1300 port = io_info >> 16;
1301 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1302
1303 skip_emulated_instruction(&svm->vcpu);
1304 return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1305 }
1306
1307 static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1308 {
1309 return 1;
1310 }
1311
1312 static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1313 {
1314 ++svm->vcpu.stat.irq_exits;
1315 return 1;
1316 }
1317
1318 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1319 {
1320 return 1;
1321 }
1322
1323 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1324 {
1325 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1326 skip_emulated_instruction(&svm->vcpu);
1327 return kvm_emulate_halt(&svm->vcpu);
1328 }
1329
1330 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1331 {
1332 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1333 skip_emulated_instruction(&svm->vcpu);
1334 kvm_emulate_hypercall(&svm->vcpu);
1335 return 1;
1336 }
1337
1338 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1339 {
1340 if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1341 || !is_paging(&svm->vcpu)) {
1342 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1343 return 1;
1344 }
1345
1346 if (svm->vmcb->save.cpl) {
1347 kvm_inject_gp(&svm->vcpu, 0);
1348 return 1;
1349 }
1350
1351 return 0;
1352 }
1353
1354 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1355 bool has_error_code, u32 error_code)
1356 {
1357 if (!is_nested(svm))
1358 return 0;
1359
1360 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1361 svm->vmcb->control.exit_code_hi = 0;
1362 svm->vmcb->control.exit_info_1 = error_code;
1363 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1364
1365 return nested_svm_exit_handled(svm);
1366 }
1367
1368 static inline int nested_svm_intr(struct vcpu_svm *svm)
1369 {
1370 if (!is_nested(svm))
1371 return 0;
1372
1373 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1374 return 0;
1375
1376 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1377 return 0;
1378
1379 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1380
1381 if (nested_svm_exit_handled(svm)) {
1382 nsvm_printk("VMexit -> INTR\n");
1383 return 1;
1384 }
1385
1386 return 0;
1387 }
1388
1389 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, enum km_type idx)
1390 {
1391 struct page *page;
1392
1393 down_read(&current->mm->mmap_sem);
1394 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1395 up_read(&current->mm->mmap_sem);
1396
1397 if (is_error_page(page))
1398 goto error;
1399
1400 return kmap_atomic(page, idx);
1401
1402 error:
1403 kvm_release_page_clean(page);
1404 kvm_inject_gp(&svm->vcpu, 0);
1405
1406 return NULL;
1407 }
1408
1409 static void nested_svm_unmap(void *addr, enum km_type idx)
1410 {
1411 struct page *page;
1412
1413 if (!addr)
1414 return;
1415
1416 page = kmap_atomic_to_page(addr);
1417
1418 kunmap_atomic(addr, idx);
1419 kvm_release_page_dirty(page);
1420 }
1421
1422 static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1423 {
1424 u32 param = svm->vmcb->control.exit_info_1 & 1;
1425 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1426 bool ret = false;
1427 u32 t0, t1;
1428 u8 *msrpm;
1429
1430 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1431 return false;
1432
1433 msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1434
1435 if (!msrpm)
1436 goto out;
1437
1438 switch (msr) {
1439 case 0 ... 0x1fff:
1440 t0 = (msr * 2) % 8;
1441 t1 = msr / 8;
1442 break;
1443 case 0xc0000000 ... 0xc0001fff:
1444 t0 = (8192 + msr - 0xc0000000) * 2;
1445 t1 = (t0 / 8);
1446 t0 %= 8;
1447 break;
1448 case 0xc0010000 ... 0xc0011fff:
1449 t0 = (16384 + msr - 0xc0010000) * 2;
1450 t1 = (t0 / 8);
1451 t0 %= 8;
1452 break;
1453 default:
1454 ret = true;
1455 goto out;
1456 }
1457
1458 ret = msrpm[t1] & ((1 << param) << t0);
1459
1460 out:
1461 nested_svm_unmap(msrpm, KM_USER0);
1462
1463 return ret;
1464 }
1465
1466 static int nested_svm_exit_special(struct vcpu_svm *svm)
1467 {
1468 u32 exit_code = svm->vmcb->control.exit_code;
1469
1470 switch (exit_code) {
1471 case SVM_EXIT_INTR:
1472 case SVM_EXIT_NMI:
1473 return NESTED_EXIT_HOST;
1474 /* For now we are always handling NPFs when using them */
1475 case SVM_EXIT_NPF:
1476 if (npt_enabled)
1477 return NESTED_EXIT_HOST;
1478 break;
1479 /* When we're shadowing, trap PFs */
1480 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1481 if (!npt_enabled)
1482 return NESTED_EXIT_HOST;
1483 break;
1484 default:
1485 break;
1486 }
1487
1488 return NESTED_EXIT_CONTINUE;
1489 }
1490
1491 /*
1492 * If this function returns true, this #vmexit was already handled
1493 */
1494 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1495 {
1496 u32 exit_code = svm->vmcb->control.exit_code;
1497 int vmexit = NESTED_EXIT_HOST;
1498
1499 switch (exit_code) {
1500 case SVM_EXIT_MSR:
1501 vmexit = nested_svm_exit_handled_msr(svm);
1502 break;
1503 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1504 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1505 if (svm->nested.intercept_cr_read & cr_bits)
1506 vmexit = NESTED_EXIT_DONE;
1507 break;
1508 }
1509 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1510 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1511 if (svm->nested.intercept_cr_write & cr_bits)
1512 vmexit = NESTED_EXIT_DONE;
1513 break;
1514 }
1515 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1516 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1517 if (svm->nested.intercept_dr_read & dr_bits)
1518 vmexit = NESTED_EXIT_DONE;
1519 break;
1520 }
1521 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1522 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1523 if (svm->nested.intercept_dr_write & dr_bits)
1524 vmexit = NESTED_EXIT_DONE;
1525 break;
1526 }
1527 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1528 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1529 if (svm->nested.intercept_exceptions & excp_bits)
1530 vmexit = NESTED_EXIT_DONE;
1531 break;
1532 }
1533 default: {
1534 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1535 nsvm_printk("exit code: 0x%x\n", exit_code);
1536 if (svm->nested.intercept & exit_bits)
1537 vmexit = NESTED_EXIT_DONE;
1538 }
1539 }
1540
1541 if (vmexit == NESTED_EXIT_DONE) {
1542 nsvm_printk("#VMEXIT reason=%04x\n", exit_code);
1543 nested_svm_vmexit(svm);
1544 }
1545
1546 return vmexit;
1547 }
1548
1549 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1550 {
1551 struct vmcb_control_area *dst = &dst_vmcb->control;
1552 struct vmcb_control_area *from = &from_vmcb->control;
1553
1554 dst->intercept_cr_read = from->intercept_cr_read;
1555 dst->intercept_cr_write = from->intercept_cr_write;
1556 dst->intercept_dr_read = from->intercept_dr_read;
1557 dst->intercept_dr_write = from->intercept_dr_write;
1558 dst->intercept_exceptions = from->intercept_exceptions;
1559 dst->intercept = from->intercept;
1560 dst->iopm_base_pa = from->iopm_base_pa;
1561 dst->msrpm_base_pa = from->msrpm_base_pa;
1562 dst->tsc_offset = from->tsc_offset;
1563 dst->asid = from->asid;
1564 dst->tlb_ctl = from->tlb_ctl;
1565 dst->int_ctl = from->int_ctl;
1566 dst->int_vector = from->int_vector;
1567 dst->int_state = from->int_state;
1568 dst->exit_code = from->exit_code;
1569 dst->exit_code_hi = from->exit_code_hi;
1570 dst->exit_info_1 = from->exit_info_1;
1571 dst->exit_info_2 = from->exit_info_2;
1572 dst->exit_int_info = from->exit_int_info;
1573 dst->exit_int_info_err = from->exit_int_info_err;
1574 dst->nested_ctl = from->nested_ctl;
1575 dst->event_inj = from->event_inj;
1576 dst->event_inj_err = from->event_inj_err;
1577 dst->nested_cr3 = from->nested_cr3;
1578 dst->lbr_ctl = from->lbr_ctl;
1579 }
1580
1581 static int nested_svm_vmexit(struct vcpu_svm *svm)
1582 {
1583 struct vmcb *nested_vmcb;
1584 struct vmcb *hsave = svm->nested.hsave;
1585 struct vmcb *vmcb = svm->vmcb;
1586
1587 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, KM_USER0);
1588 if (!nested_vmcb)
1589 return 1;
1590
1591 /* Give the current vmcb to the guest */
1592 disable_gif(svm);
1593
1594 nested_vmcb->save.es = vmcb->save.es;
1595 nested_vmcb->save.cs = vmcb->save.cs;
1596 nested_vmcb->save.ss = vmcb->save.ss;
1597 nested_vmcb->save.ds = vmcb->save.ds;
1598 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1599 nested_vmcb->save.idtr = vmcb->save.idtr;
1600 if (npt_enabled)
1601 nested_vmcb->save.cr3 = vmcb->save.cr3;
1602 nested_vmcb->save.cr2 = vmcb->save.cr2;
1603 nested_vmcb->save.rflags = vmcb->save.rflags;
1604 nested_vmcb->save.rip = vmcb->save.rip;
1605 nested_vmcb->save.rsp = vmcb->save.rsp;
1606 nested_vmcb->save.rax = vmcb->save.rax;
1607 nested_vmcb->save.dr7 = vmcb->save.dr7;
1608 nested_vmcb->save.dr6 = vmcb->save.dr6;
1609 nested_vmcb->save.cpl = vmcb->save.cpl;
1610
1611 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1612 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1613 nested_vmcb->control.int_state = vmcb->control.int_state;
1614 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1615 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1616 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1617 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1618 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1619 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1620 nested_vmcb->control.tlb_ctl = 0;
1621 nested_vmcb->control.event_inj = 0;
1622 nested_vmcb->control.event_inj_err = 0;
1623
1624 /* We always set V_INTR_MASKING and remember the old value in hflags */
1625 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1626 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1627
1628 /* Restore the original control entries */
1629 copy_vmcb_control_area(vmcb, hsave);
1630
1631 /* Kill any pending exceptions */
1632 if (svm->vcpu.arch.exception.pending == true)
1633 nsvm_printk("WARNING: Pending Exception\n");
1634
1635 kvm_clear_exception_queue(&svm->vcpu);
1636 kvm_clear_interrupt_queue(&svm->vcpu);
1637
1638 /* Restore selected save entries */
1639 svm->vmcb->save.es = hsave->save.es;
1640 svm->vmcb->save.cs = hsave->save.cs;
1641 svm->vmcb->save.ss = hsave->save.ss;
1642 svm->vmcb->save.ds = hsave->save.ds;
1643 svm->vmcb->save.gdtr = hsave->save.gdtr;
1644 svm->vmcb->save.idtr = hsave->save.idtr;
1645 svm->vmcb->save.rflags = hsave->save.rflags;
1646 svm_set_efer(&svm->vcpu, hsave->save.efer);
1647 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1648 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1649 if (npt_enabled) {
1650 svm->vmcb->save.cr3 = hsave->save.cr3;
1651 svm->vcpu.arch.cr3 = hsave->save.cr3;
1652 } else {
1653 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1654 }
1655 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1656 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1657 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1658 svm->vmcb->save.dr7 = 0;
1659 svm->vmcb->save.cpl = 0;
1660 svm->vmcb->control.exit_int_info = 0;
1661
1662 /* Exit nested SVM mode */
1663 svm->nested.vmcb = 0;
1664
1665 nested_svm_unmap(nested_vmcb, KM_USER0);
1666
1667 kvm_mmu_reset_context(&svm->vcpu);
1668 kvm_mmu_load(&svm->vcpu);
1669
1670 return 0;
1671 }
1672
1673 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
1674 {
1675 u32 *nested_msrpm;
1676 int i;
1677
1678 nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1679 if (!nested_msrpm)
1680 return false;
1681
1682 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1683 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1684
1685 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
1686
1687 nested_svm_unmap(nested_msrpm, KM_USER0);
1688
1689 return true;
1690 }
1691
1692 static bool nested_svm_vmrun(struct vcpu_svm *svm)
1693 {
1694 struct vmcb *nested_vmcb;
1695 struct vmcb *hsave = svm->nested.hsave;
1696 struct vmcb *vmcb = svm->vmcb;
1697
1698 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1699 if (!nested_vmcb)
1700 return false;
1701
1702 /* nested_vmcb is our indicator if nested SVM is activated */
1703 svm->nested.vmcb = svm->vmcb->save.rax;
1704
1705 /* Clear internal status */
1706 kvm_clear_exception_queue(&svm->vcpu);
1707 kvm_clear_interrupt_queue(&svm->vcpu);
1708
1709 /* Save the old vmcb, so we don't need to pick what we save, but
1710 can restore everything when a VMEXIT occurs */
1711 hsave->save.es = vmcb->save.es;
1712 hsave->save.cs = vmcb->save.cs;
1713 hsave->save.ss = vmcb->save.ss;
1714 hsave->save.ds = vmcb->save.ds;
1715 hsave->save.gdtr = vmcb->save.gdtr;
1716 hsave->save.idtr = vmcb->save.idtr;
1717 hsave->save.efer = svm->vcpu.arch.shadow_efer;
1718 hsave->save.cr0 = svm->vcpu.arch.cr0;
1719 hsave->save.cr4 = svm->vcpu.arch.cr4;
1720 hsave->save.rflags = vmcb->save.rflags;
1721 hsave->save.rip = svm->next_rip;
1722 hsave->save.rsp = vmcb->save.rsp;
1723 hsave->save.rax = vmcb->save.rax;
1724 if (npt_enabled)
1725 hsave->save.cr3 = vmcb->save.cr3;
1726 else
1727 hsave->save.cr3 = svm->vcpu.arch.cr3;
1728
1729 copy_vmcb_control_area(hsave, vmcb);
1730
1731 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1732 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1733 else
1734 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1735
1736 /* Load the nested guest state */
1737 svm->vmcb->save.es = nested_vmcb->save.es;
1738 svm->vmcb->save.cs = nested_vmcb->save.cs;
1739 svm->vmcb->save.ss = nested_vmcb->save.ss;
1740 svm->vmcb->save.ds = nested_vmcb->save.ds;
1741 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1742 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1743 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1744 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1745 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1746 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1747 if (npt_enabled) {
1748 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1749 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1750 } else {
1751 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1752 kvm_mmu_reset_context(&svm->vcpu);
1753 }
1754 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
1755 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1756 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1757 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1758 /* In case we don't even reach vcpu_run, the fields are not updated */
1759 svm->vmcb->save.rax = nested_vmcb->save.rax;
1760 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1761 svm->vmcb->save.rip = nested_vmcb->save.rip;
1762 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1763 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1764 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1765
1766 /* We don't want a nested guest to be more powerful than the guest,
1767 so all intercepts are ORed */
1768 svm->vmcb->control.intercept_cr_read |=
1769 nested_vmcb->control.intercept_cr_read;
1770 svm->vmcb->control.intercept_cr_write |=
1771 nested_vmcb->control.intercept_cr_write;
1772 svm->vmcb->control.intercept_dr_read |=
1773 nested_vmcb->control.intercept_dr_read;
1774 svm->vmcb->control.intercept_dr_write |=
1775 nested_vmcb->control.intercept_dr_write;
1776 svm->vmcb->control.intercept_exceptions |=
1777 nested_vmcb->control.intercept_exceptions;
1778
1779 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1780
1781 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1782
1783 /* cache intercepts */
1784 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
1785 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
1786 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
1787 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
1788 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1789 svm->nested.intercept = nested_vmcb->control.intercept;
1790
1791 force_new_asid(&svm->vcpu);
1792 svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info;
1793 svm->vmcb->control.exit_int_info_err = nested_vmcb->control.exit_int_info_err;
1794 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1795 if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1796 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1797 nested_vmcb->control.int_ctl);
1798 }
1799 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1800 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1801 else
1802 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1803
1804 nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1805 nested_vmcb->control.exit_int_info,
1806 nested_vmcb->control.int_state);
1807
1808 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1809 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1810 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1811 if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1812 nsvm_printk("Injecting Event: 0x%x\n",
1813 nested_vmcb->control.event_inj);
1814 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1815 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1816
1817 nested_svm_unmap(nested_vmcb, KM_USER0);
1818
1819 enable_gif(svm);
1820
1821 return true;
1822 }
1823
1824 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1825 {
1826 to_vmcb->save.fs = from_vmcb->save.fs;
1827 to_vmcb->save.gs = from_vmcb->save.gs;
1828 to_vmcb->save.tr = from_vmcb->save.tr;
1829 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1830 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1831 to_vmcb->save.star = from_vmcb->save.star;
1832 to_vmcb->save.lstar = from_vmcb->save.lstar;
1833 to_vmcb->save.cstar = from_vmcb->save.cstar;
1834 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1835 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1836 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1837 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1838 }
1839
1840 static int vmload_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1841 {
1842 struct vmcb *nested_vmcb;
1843
1844 if (nested_svm_check_permissions(svm))
1845 return 1;
1846
1847 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1848 skip_emulated_instruction(&svm->vcpu);
1849
1850 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1851 if (!nested_vmcb)
1852 return 1;
1853
1854 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
1855 nested_svm_unmap(nested_vmcb, KM_USER0);
1856
1857 return 1;
1858 }
1859
1860 static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1861 {
1862 struct vmcb *nested_vmcb;
1863
1864 if (nested_svm_check_permissions(svm))
1865 return 1;
1866
1867 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1868 skip_emulated_instruction(&svm->vcpu);
1869
1870 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1871 if (!nested_vmcb)
1872 return 1;
1873
1874 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
1875 nested_svm_unmap(nested_vmcb, KM_USER0);
1876
1877 return 1;
1878 }
1879
1880 static int vmrun_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1881 {
1882 nsvm_printk("VMrun\n");
1883
1884 if (nested_svm_check_permissions(svm))
1885 return 1;
1886
1887 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1888 skip_emulated_instruction(&svm->vcpu);
1889
1890 if (!nested_svm_vmrun(svm))
1891 return 1;
1892
1893 if (!nested_svm_vmrun_msrpm(svm))
1894 goto failed;
1895
1896 return 1;
1897
1898 failed:
1899
1900 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
1901 svm->vmcb->control.exit_code_hi = 0;
1902 svm->vmcb->control.exit_info_1 = 0;
1903 svm->vmcb->control.exit_info_2 = 0;
1904
1905 nested_svm_vmexit(svm);
1906
1907 return 1;
1908 }
1909
1910 static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1911 {
1912 if (nested_svm_check_permissions(svm))
1913 return 1;
1914
1915 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1916 skip_emulated_instruction(&svm->vcpu);
1917
1918 enable_gif(svm);
1919
1920 return 1;
1921 }
1922
1923 static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1924 {
1925 if (nested_svm_check_permissions(svm))
1926 return 1;
1927
1928 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1929 skip_emulated_instruction(&svm->vcpu);
1930
1931 disable_gif(svm);
1932
1933 /* After a CLGI no interrupts should come */
1934 svm_clear_vintr(svm);
1935 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1936
1937 return 1;
1938 }
1939
1940 static int invlpga_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1941 {
1942 struct kvm_vcpu *vcpu = &svm->vcpu;
1943 nsvm_printk("INVLPGA\n");
1944
1945 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
1946 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
1947
1948 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1949 skip_emulated_instruction(&svm->vcpu);
1950 return 1;
1951 }
1952
1953 static int invalid_op_interception(struct vcpu_svm *svm,
1954 struct kvm_run *kvm_run)
1955 {
1956 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1957 return 1;
1958 }
1959
1960 static int task_switch_interception(struct vcpu_svm *svm,
1961 struct kvm_run *kvm_run)
1962 {
1963 u16 tss_selector;
1964 int reason;
1965 int int_type = svm->vmcb->control.exit_int_info &
1966 SVM_EXITINTINFO_TYPE_MASK;
1967 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
1968 uint32_t type =
1969 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
1970 uint32_t idt_v =
1971 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
1972
1973 tss_selector = (u16)svm->vmcb->control.exit_info_1;
1974
1975 if (svm->vmcb->control.exit_info_2 &
1976 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1977 reason = TASK_SWITCH_IRET;
1978 else if (svm->vmcb->control.exit_info_2 &
1979 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1980 reason = TASK_SWITCH_JMP;
1981 else if (idt_v)
1982 reason = TASK_SWITCH_GATE;
1983 else
1984 reason = TASK_SWITCH_CALL;
1985
1986 if (reason == TASK_SWITCH_GATE) {
1987 switch (type) {
1988 case SVM_EXITINTINFO_TYPE_NMI:
1989 svm->vcpu.arch.nmi_injected = false;
1990 break;
1991 case SVM_EXITINTINFO_TYPE_EXEPT:
1992 kvm_clear_exception_queue(&svm->vcpu);
1993 break;
1994 case SVM_EXITINTINFO_TYPE_INTR:
1995 kvm_clear_interrupt_queue(&svm->vcpu);
1996 break;
1997 default:
1998 break;
1999 }
2000 }
2001
2002 if (reason != TASK_SWITCH_GATE ||
2003 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2004 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2005 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2006 skip_emulated_instruction(&svm->vcpu);
2007
2008 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
2009 }
2010
2011 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2012 {
2013 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2014 kvm_emulate_cpuid(&svm->vcpu);
2015 return 1;
2016 }
2017
2018 static int iret_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2019 {
2020 ++svm->vcpu.stat.nmi_window_exits;
2021 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2022 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2023 return 1;
2024 }
2025
2026 static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2027 {
2028 if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
2029 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2030 return 1;
2031 }
2032
2033 static int emulate_on_interception(struct vcpu_svm *svm,
2034 struct kvm_run *kvm_run)
2035 {
2036 if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
2037 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2038 return 1;
2039 }
2040
2041 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2042 {
2043 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2044 /* instruction emulation calls kvm_set_cr8() */
2045 emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
2046 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2047 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2048 return 1;
2049 }
2050 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2051 return 1;
2052 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2053 return 0;
2054 }
2055
2056 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2057 {
2058 struct vcpu_svm *svm = to_svm(vcpu);
2059
2060 switch (ecx) {
2061 case MSR_IA32_TSC: {
2062 u64 tsc_offset;
2063
2064 if (is_nested(svm))
2065 tsc_offset = svm->nested.hsave->control.tsc_offset;
2066 else
2067 tsc_offset = svm->vmcb->control.tsc_offset;
2068
2069 *data = tsc_offset + native_read_tsc();
2070 break;
2071 }
2072 case MSR_K6_STAR:
2073 *data = svm->vmcb->save.star;
2074 break;
2075 #ifdef CONFIG_X86_64
2076 case MSR_LSTAR:
2077 *data = svm->vmcb->save.lstar;
2078 break;
2079 case MSR_CSTAR:
2080 *data = svm->vmcb->save.cstar;
2081 break;
2082 case MSR_KERNEL_GS_BASE:
2083 *data = svm->vmcb->save.kernel_gs_base;
2084 break;
2085 case MSR_SYSCALL_MASK:
2086 *data = svm->vmcb->save.sfmask;
2087 break;
2088 #endif
2089 case MSR_IA32_SYSENTER_CS:
2090 *data = svm->vmcb->save.sysenter_cs;
2091 break;
2092 case MSR_IA32_SYSENTER_EIP:
2093 *data = svm->sysenter_eip;
2094 break;
2095 case MSR_IA32_SYSENTER_ESP:
2096 *data = svm->sysenter_esp;
2097 break;
2098 /* Nobody will change the following 5 values in the VMCB so
2099 we can safely return them on rdmsr. They will always be 0
2100 until LBRV is implemented. */
2101 case MSR_IA32_DEBUGCTLMSR:
2102 *data = svm->vmcb->save.dbgctl;
2103 break;
2104 case MSR_IA32_LASTBRANCHFROMIP:
2105 *data = svm->vmcb->save.br_from;
2106 break;
2107 case MSR_IA32_LASTBRANCHTOIP:
2108 *data = svm->vmcb->save.br_to;
2109 break;
2110 case MSR_IA32_LASTINTFROMIP:
2111 *data = svm->vmcb->save.last_excp_from;
2112 break;
2113 case MSR_IA32_LASTINTTOIP:
2114 *data = svm->vmcb->save.last_excp_to;
2115 break;
2116 case MSR_VM_HSAVE_PA:
2117 *data = svm->nested.hsave_msr;
2118 break;
2119 case MSR_VM_CR:
2120 *data = 0;
2121 break;
2122 case MSR_IA32_UCODE_REV:
2123 *data = 0x01000065;
2124 break;
2125 default:
2126 return kvm_get_msr_common(vcpu, ecx, data);
2127 }
2128 return 0;
2129 }
2130
2131 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2132 {
2133 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2134 u64 data;
2135
2136 if (svm_get_msr(&svm->vcpu, ecx, &data))
2137 kvm_inject_gp(&svm->vcpu, 0);
2138 else {
2139 trace_kvm_msr_read(ecx, data);
2140
2141 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2142 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2143 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2144 skip_emulated_instruction(&svm->vcpu);
2145 }
2146 return 1;
2147 }
2148
2149 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2150 {
2151 struct vcpu_svm *svm = to_svm(vcpu);
2152
2153 switch (ecx) {
2154 case MSR_IA32_TSC: {
2155 u64 tsc_offset = data - native_read_tsc();
2156 u64 g_tsc_offset = 0;
2157
2158 if (is_nested(svm)) {
2159 g_tsc_offset = svm->vmcb->control.tsc_offset -
2160 svm->nested.hsave->control.tsc_offset;
2161 svm->nested.hsave->control.tsc_offset = tsc_offset;
2162 }
2163
2164 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
2165
2166 break;
2167 }
2168 case MSR_K6_STAR:
2169 svm->vmcb->save.star = data;
2170 break;
2171 #ifdef CONFIG_X86_64
2172 case MSR_LSTAR:
2173 svm->vmcb->save.lstar = data;
2174 break;
2175 case MSR_CSTAR:
2176 svm->vmcb->save.cstar = data;
2177 break;
2178 case MSR_KERNEL_GS_BASE:
2179 svm->vmcb->save.kernel_gs_base = data;
2180 break;
2181 case MSR_SYSCALL_MASK:
2182 svm->vmcb->save.sfmask = data;
2183 break;
2184 #endif
2185 case MSR_IA32_SYSENTER_CS:
2186 svm->vmcb->save.sysenter_cs = data;
2187 break;
2188 case MSR_IA32_SYSENTER_EIP:
2189 svm->sysenter_eip = data;
2190 svm->vmcb->save.sysenter_eip = data;
2191 break;
2192 case MSR_IA32_SYSENTER_ESP:
2193 svm->sysenter_esp = data;
2194 svm->vmcb->save.sysenter_esp = data;
2195 break;
2196 case MSR_IA32_DEBUGCTLMSR:
2197 if (!svm_has(SVM_FEATURE_LBRV)) {
2198 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2199 __func__, data);
2200 break;
2201 }
2202 if (data & DEBUGCTL_RESERVED_BITS)
2203 return 1;
2204
2205 svm->vmcb->save.dbgctl = data;
2206 if (data & (1ULL<<0))
2207 svm_enable_lbrv(svm);
2208 else
2209 svm_disable_lbrv(svm);
2210 break;
2211 case MSR_VM_HSAVE_PA:
2212 svm->nested.hsave_msr = data;
2213 break;
2214 case MSR_VM_CR:
2215 case MSR_VM_IGNNE:
2216 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2217 break;
2218 default:
2219 return kvm_set_msr_common(vcpu, ecx, data);
2220 }
2221 return 0;
2222 }
2223
2224 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2225 {
2226 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2227 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2228 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2229
2230 trace_kvm_msr_write(ecx, data);
2231
2232 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2233 if (svm_set_msr(&svm->vcpu, ecx, data))
2234 kvm_inject_gp(&svm->vcpu, 0);
2235 else
2236 skip_emulated_instruction(&svm->vcpu);
2237 return 1;
2238 }
2239
2240 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2241 {
2242 if (svm->vmcb->control.exit_info_1)
2243 return wrmsr_interception(svm, kvm_run);
2244 else
2245 return rdmsr_interception(svm, kvm_run);
2246 }
2247
2248 static int interrupt_window_interception(struct vcpu_svm *svm,
2249 struct kvm_run *kvm_run)
2250 {
2251 svm_clear_vintr(svm);
2252 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2253 /*
2254 * If the user space waits to inject interrupts, exit as soon as
2255 * possible
2256 */
2257 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2258 kvm_run->request_interrupt_window &&
2259 !kvm_cpu_has_interrupt(&svm->vcpu)) {
2260 ++svm->vcpu.stat.irq_window_exits;
2261 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2262 return 0;
2263 }
2264
2265 return 1;
2266 }
2267
2268 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
2269 struct kvm_run *kvm_run) = {
2270 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2271 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2272 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2273 [SVM_EXIT_READ_CR8] = emulate_on_interception,
2274 /* for now: */
2275 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2276 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2277 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2278 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2279 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2280 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2281 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2282 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2283 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2284 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2285 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2286 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2287 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2288 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
2289 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2290 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
2291 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
2292 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2293 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2294 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2295 [SVM_EXIT_INTR] = intr_interception,
2296 [SVM_EXIT_NMI] = nmi_interception,
2297 [SVM_EXIT_SMI] = nop_on_interception,
2298 [SVM_EXIT_INIT] = nop_on_interception,
2299 [SVM_EXIT_VINTR] = interrupt_window_interception,
2300 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2301 [SVM_EXIT_CPUID] = cpuid_interception,
2302 [SVM_EXIT_IRET] = iret_interception,
2303 [SVM_EXIT_INVD] = emulate_on_interception,
2304 [SVM_EXIT_HLT] = halt_interception,
2305 [SVM_EXIT_INVLPG] = invlpg_interception,
2306 [SVM_EXIT_INVLPGA] = invlpga_interception,
2307 [SVM_EXIT_IOIO] = io_interception,
2308 [SVM_EXIT_MSR] = msr_interception,
2309 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
2310 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
2311 [SVM_EXIT_VMRUN] = vmrun_interception,
2312 [SVM_EXIT_VMMCALL] = vmmcall_interception,
2313 [SVM_EXIT_VMLOAD] = vmload_interception,
2314 [SVM_EXIT_VMSAVE] = vmsave_interception,
2315 [SVM_EXIT_STGI] = stgi_interception,
2316 [SVM_EXIT_CLGI] = clgi_interception,
2317 [SVM_EXIT_SKINIT] = invalid_op_interception,
2318 [SVM_EXIT_WBINVD] = emulate_on_interception,
2319 [SVM_EXIT_MONITOR] = invalid_op_interception,
2320 [SVM_EXIT_MWAIT] = invalid_op_interception,
2321 [SVM_EXIT_NPF] = pf_interception,
2322 };
2323
2324 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2325 {
2326 struct vcpu_svm *svm = to_svm(vcpu);
2327 u32 exit_code = svm->vmcb->control.exit_code;
2328
2329 trace_kvm_exit(exit_code, svm->vmcb->save.rip);
2330
2331 if (is_nested(svm)) {
2332 int vmexit;
2333
2334 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2335 exit_code, svm->vmcb->control.exit_info_1,
2336 svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
2337
2338 vmexit = nested_svm_exit_special(svm);
2339
2340 if (vmexit == NESTED_EXIT_CONTINUE)
2341 vmexit = nested_svm_exit_handled(svm);
2342
2343 if (vmexit == NESTED_EXIT_DONE)
2344 return 1;
2345 }
2346
2347 svm_complete_interrupts(svm);
2348
2349 if (npt_enabled) {
2350 int mmu_reload = 0;
2351 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2352 svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2353 mmu_reload = 1;
2354 }
2355 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2356 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2357 if (mmu_reload) {
2358 kvm_mmu_reset_context(vcpu);
2359 kvm_mmu_load(vcpu);
2360 }
2361 }
2362
2363
2364 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2365 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2366 kvm_run->fail_entry.hardware_entry_failure_reason
2367 = svm->vmcb->control.exit_code;
2368 return 0;
2369 }
2370
2371 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2372 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2373 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2374 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2375 "exit_code 0x%x\n",
2376 __func__, svm->vmcb->control.exit_int_info,
2377 exit_code);
2378
2379 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2380 || !svm_exit_handlers[exit_code]) {
2381 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2382 kvm_run->hw.hardware_exit_reason = exit_code;
2383 return 0;
2384 }
2385
2386 return svm_exit_handlers[exit_code](svm, kvm_run);
2387 }
2388
2389 static void reload_tss(struct kvm_vcpu *vcpu)
2390 {
2391 int cpu = raw_smp_processor_id();
2392
2393 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2394 svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
2395 load_TR_desc();
2396 }
2397
2398 static void pre_svm_run(struct vcpu_svm *svm)
2399 {
2400 int cpu = raw_smp_processor_id();
2401
2402 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2403
2404 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2405 /* FIXME: handle wraparound of asid_generation */
2406 if (svm->asid_generation != svm_data->asid_generation)
2407 new_asid(svm, svm_data);
2408 }
2409
2410 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2411 {
2412 struct vcpu_svm *svm = to_svm(vcpu);
2413
2414 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2415 vcpu->arch.hflags |= HF_NMI_MASK;
2416 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2417 ++vcpu->stat.nmi_injections;
2418 }
2419
2420 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2421 {
2422 struct vmcb_control_area *control;
2423
2424 trace_kvm_inj_virq(irq);
2425
2426 ++svm->vcpu.stat.irq_injections;
2427 control = &svm->vmcb->control;
2428 control->int_vector = irq;
2429 control->int_ctl &= ~V_INTR_PRIO_MASK;
2430 control->int_ctl |= V_IRQ_MASK |
2431 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2432 }
2433
2434 static void svm_set_irq(struct kvm_vcpu *vcpu)
2435 {
2436 struct vcpu_svm *svm = to_svm(vcpu);
2437
2438 BUG_ON(!(gif_set(svm)));
2439
2440 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2441 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2442 }
2443
2444 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2445 {
2446 struct vcpu_svm *svm = to_svm(vcpu);
2447
2448 if (irr == -1)
2449 return;
2450
2451 if (tpr >= irr)
2452 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2453 }
2454
2455 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2456 {
2457 struct vcpu_svm *svm = to_svm(vcpu);
2458 struct vmcb *vmcb = svm->vmcb;
2459 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2460 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2461 }
2462
2463 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2464 {
2465 struct vcpu_svm *svm = to_svm(vcpu);
2466 struct vmcb *vmcb = svm->vmcb;
2467 return (vmcb->save.rflags & X86_EFLAGS_IF) &&
2468 !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2469 gif_set(svm) &&
2470 !(is_nested(svm) && (svm->vcpu.arch.hflags & HF_VINTR_MASK));
2471 }
2472
2473 static void enable_irq_window(struct kvm_vcpu *vcpu)
2474 {
2475 struct vcpu_svm *svm = to_svm(vcpu);
2476 nsvm_printk("Trying to open IRQ window\n");
2477
2478 nested_svm_intr(svm);
2479
2480 /* In case GIF=0 we can't rely on the CPU to tell us when
2481 * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2482 * The next time we get that intercept, this function will be
2483 * called again though and we'll get the vintr intercept. */
2484 if (gif_set(svm)) {
2485 svm_set_vintr(svm);
2486 svm_inject_irq(svm, 0x0);
2487 }
2488 }
2489
2490 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2491 {
2492 struct vcpu_svm *svm = to_svm(vcpu);
2493
2494 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2495 == HF_NMI_MASK)
2496 return; /* IRET will cause a vm exit */
2497
2498 /* Something prevents NMI from been injected. Single step over
2499 possible problem (IRET or exception injection or interrupt
2500 shadow) */
2501 vcpu->arch.singlestep = true;
2502 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2503 update_db_intercept(vcpu);
2504 }
2505
2506 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2507 {
2508 return 0;
2509 }
2510
2511 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2512 {
2513 force_new_asid(vcpu);
2514 }
2515
2516 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2517 {
2518 }
2519
2520 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2521 {
2522 struct vcpu_svm *svm = to_svm(vcpu);
2523
2524 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2525 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2526 kvm_set_cr8(vcpu, cr8);
2527 }
2528 }
2529
2530 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2531 {
2532 struct vcpu_svm *svm = to_svm(vcpu);
2533 u64 cr8;
2534
2535 cr8 = kvm_get_cr8(vcpu);
2536 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2537 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2538 }
2539
2540 static void svm_complete_interrupts(struct vcpu_svm *svm)
2541 {
2542 u8 vector;
2543 int type;
2544 u32 exitintinfo = svm->vmcb->control.exit_int_info;
2545
2546 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2547 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2548
2549 svm->vcpu.arch.nmi_injected = false;
2550 kvm_clear_exception_queue(&svm->vcpu);
2551 kvm_clear_interrupt_queue(&svm->vcpu);
2552
2553 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2554 return;
2555
2556 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2557 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2558
2559 switch (type) {
2560 case SVM_EXITINTINFO_TYPE_NMI:
2561 svm->vcpu.arch.nmi_injected = true;
2562 break;
2563 case SVM_EXITINTINFO_TYPE_EXEPT:
2564 /* In case of software exception do not reinject an exception
2565 vector, but re-execute and instruction instead */
2566 if (is_nested(svm))
2567 break;
2568 if (kvm_exception_is_soft(vector))
2569 break;
2570 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2571 u32 err = svm->vmcb->control.exit_int_info_err;
2572 kvm_queue_exception_e(&svm->vcpu, vector, err);
2573
2574 } else
2575 kvm_queue_exception(&svm->vcpu, vector);
2576 break;
2577 case SVM_EXITINTINFO_TYPE_INTR:
2578 kvm_queue_interrupt(&svm->vcpu, vector, false);
2579 break;
2580 default:
2581 break;
2582 }
2583 }
2584
2585 #ifdef CONFIG_X86_64
2586 #define R "r"
2587 #else
2588 #define R "e"
2589 #endif
2590
2591 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2592 {
2593 struct vcpu_svm *svm = to_svm(vcpu);
2594 u16 fs_selector;
2595 u16 gs_selector;
2596 u16 ldt_selector;
2597
2598 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2599 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2600 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2601
2602 pre_svm_run(svm);
2603
2604 sync_lapic_to_cr8(vcpu);
2605
2606 save_host_msrs(vcpu);
2607 fs_selector = kvm_read_fs();
2608 gs_selector = kvm_read_gs();
2609 ldt_selector = kvm_read_ldt();
2610 svm->vmcb->save.cr2 = vcpu->arch.cr2;
2611 /* required for live migration with NPT */
2612 if (npt_enabled)
2613 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2614
2615 clgi();
2616
2617 local_irq_enable();
2618
2619 asm volatile (
2620 "push %%"R"bp; \n\t"
2621 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2622 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2623 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2624 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2625 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2626 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2627 #ifdef CONFIG_X86_64
2628 "mov %c[r8](%[svm]), %%r8 \n\t"
2629 "mov %c[r9](%[svm]), %%r9 \n\t"
2630 "mov %c[r10](%[svm]), %%r10 \n\t"
2631 "mov %c[r11](%[svm]), %%r11 \n\t"
2632 "mov %c[r12](%[svm]), %%r12 \n\t"
2633 "mov %c[r13](%[svm]), %%r13 \n\t"
2634 "mov %c[r14](%[svm]), %%r14 \n\t"
2635 "mov %c[r15](%[svm]), %%r15 \n\t"
2636 #endif
2637
2638 /* Enter guest mode */
2639 "push %%"R"ax \n\t"
2640 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2641 __ex(SVM_VMLOAD) "\n\t"
2642 __ex(SVM_VMRUN) "\n\t"
2643 __ex(SVM_VMSAVE) "\n\t"
2644 "pop %%"R"ax \n\t"
2645
2646 /* Save guest registers, load host registers */
2647 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2648 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2649 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2650 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2651 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2652 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2653 #ifdef CONFIG_X86_64
2654 "mov %%r8, %c[r8](%[svm]) \n\t"
2655 "mov %%r9, %c[r9](%[svm]) \n\t"
2656 "mov %%r10, %c[r10](%[svm]) \n\t"
2657 "mov %%r11, %c[r11](%[svm]) \n\t"
2658 "mov %%r12, %c[r12](%[svm]) \n\t"
2659 "mov %%r13, %c[r13](%[svm]) \n\t"
2660 "mov %%r14, %c[r14](%[svm]) \n\t"
2661 "mov %%r15, %c[r15](%[svm]) \n\t"
2662 #endif
2663 "pop %%"R"bp"
2664 :
2665 : [svm]"a"(svm),
2666 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2667 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2668 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2669 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2670 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2671 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2672 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2673 #ifdef CONFIG_X86_64
2674 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2675 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2676 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2677 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2678 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2679 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2680 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2681 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2682 #endif
2683 : "cc", "memory"
2684 , R"bx", R"cx", R"dx", R"si", R"di"
2685 #ifdef CONFIG_X86_64
2686 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2687 #endif
2688 );
2689
2690 vcpu->arch.cr2 = svm->vmcb->save.cr2;
2691 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2692 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2693 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2694
2695 kvm_load_fs(fs_selector);
2696 kvm_load_gs(gs_selector);
2697 kvm_load_ldt(ldt_selector);
2698 load_host_msrs(vcpu);
2699
2700 reload_tss(vcpu);
2701
2702 local_irq_disable();
2703
2704 stgi();
2705
2706 sync_cr8_to_lapic(vcpu);
2707
2708 svm->next_rip = 0;
2709
2710 if (npt_enabled) {
2711 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2712 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2713 }
2714 }
2715
2716 #undef R
2717
2718 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2719 {
2720 struct vcpu_svm *svm = to_svm(vcpu);
2721
2722 if (npt_enabled) {
2723 svm->vmcb->control.nested_cr3 = root;
2724 force_new_asid(vcpu);
2725 return;
2726 }
2727
2728 svm->vmcb->save.cr3 = root;
2729 force_new_asid(vcpu);
2730
2731 if (vcpu->fpu_active) {
2732 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2733 svm->vmcb->save.cr0 |= X86_CR0_TS;
2734 vcpu->fpu_active = 0;
2735 }
2736 }
2737
2738 static int is_disabled(void)
2739 {
2740 u64 vm_cr;
2741
2742 rdmsrl(MSR_VM_CR, vm_cr);
2743 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2744 return 1;
2745
2746 return 0;
2747 }
2748
2749 static void
2750 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2751 {
2752 /*
2753 * Patch in the VMMCALL instruction:
2754 */
2755 hypercall[0] = 0x0f;
2756 hypercall[1] = 0x01;
2757 hypercall[2] = 0xd9;
2758 }
2759
2760 static void svm_check_processor_compat(void *rtn)
2761 {
2762 *(int *)rtn = 0;
2763 }
2764
2765 static bool svm_cpu_has_accelerated_tpr(void)
2766 {
2767 return false;
2768 }
2769
2770 static int get_npt_level(void)
2771 {
2772 #ifdef CONFIG_X86_64
2773 return PT64_ROOT_LEVEL;
2774 #else
2775 return PT32E_ROOT_LEVEL;
2776 #endif
2777 }
2778
2779 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
2780 {
2781 return 0;
2782 }
2783
2784 static const struct trace_print_flags svm_exit_reasons_str[] = {
2785 { SVM_EXIT_READ_CR0, "read_cr0" },
2786 { SVM_EXIT_READ_CR3, "read_cr3" },
2787 { SVM_EXIT_READ_CR4, "read_cr4" },
2788 { SVM_EXIT_READ_CR8, "read_cr8" },
2789 { SVM_EXIT_WRITE_CR0, "write_cr0" },
2790 { SVM_EXIT_WRITE_CR3, "write_cr3" },
2791 { SVM_EXIT_WRITE_CR4, "write_cr4" },
2792 { SVM_EXIT_WRITE_CR8, "write_cr8" },
2793 { SVM_EXIT_READ_DR0, "read_dr0" },
2794 { SVM_EXIT_READ_DR1, "read_dr1" },
2795 { SVM_EXIT_READ_DR2, "read_dr2" },
2796 { SVM_EXIT_READ_DR3, "read_dr3" },
2797 { SVM_EXIT_WRITE_DR0, "write_dr0" },
2798 { SVM_EXIT_WRITE_DR1, "write_dr1" },
2799 { SVM_EXIT_WRITE_DR2, "write_dr2" },
2800 { SVM_EXIT_WRITE_DR3, "write_dr3" },
2801 { SVM_EXIT_WRITE_DR5, "write_dr5" },
2802 { SVM_EXIT_WRITE_DR7, "write_dr7" },
2803 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
2804 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
2805 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
2806 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
2807 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
2808 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
2809 { SVM_EXIT_INTR, "interrupt" },
2810 { SVM_EXIT_NMI, "nmi" },
2811 { SVM_EXIT_SMI, "smi" },
2812 { SVM_EXIT_INIT, "init" },
2813 { SVM_EXIT_VINTR, "vintr" },
2814 { SVM_EXIT_CPUID, "cpuid" },
2815 { SVM_EXIT_INVD, "invd" },
2816 { SVM_EXIT_HLT, "hlt" },
2817 { SVM_EXIT_INVLPG, "invlpg" },
2818 { SVM_EXIT_INVLPGA, "invlpga" },
2819 { SVM_EXIT_IOIO, "io" },
2820 { SVM_EXIT_MSR, "msr" },
2821 { SVM_EXIT_TASK_SWITCH, "task_switch" },
2822 { SVM_EXIT_SHUTDOWN, "shutdown" },
2823 { SVM_EXIT_VMRUN, "vmrun" },
2824 { SVM_EXIT_VMMCALL, "hypercall" },
2825 { SVM_EXIT_VMLOAD, "vmload" },
2826 { SVM_EXIT_VMSAVE, "vmsave" },
2827 { SVM_EXIT_STGI, "stgi" },
2828 { SVM_EXIT_CLGI, "clgi" },
2829 { SVM_EXIT_SKINIT, "skinit" },
2830 { SVM_EXIT_WBINVD, "wbinvd" },
2831 { SVM_EXIT_MONITOR, "monitor" },
2832 { SVM_EXIT_MWAIT, "mwait" },
2833 { SVM_EXIT_NPF, "npf" },
2834 { -1, NULL }
2835 };
2836
2837 static bool svm_gb_page_enable(void)
2838 {
2839 return true;
2840 }
2841
2842 static struct kvm_x86_ops svm_x86_ops = {
2843 .cpu_has_kvm_support = has_svm,
2844 .disabled_by_bios = is_disabled,
2845 .hardware_setup = svm_hardware_setup,
2846 .hardware_unsetup = svm_hardware_unsetup,
2847 .check_processor_compatibility = svm_check_processor_compat,
2848 .hardware_enable = svm_hardware_enable,
2849 .hardware_disable = svm_hardware_disable,
2850 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
2851
2852 .vcpu_create = svm_create_vcpu,
2853 .vcpu_free = svm_free_vcpu,
2854 .vcpu_reset = svm_vcpu_reset,
2855
2856 .prepare_guest_switch = svm_prepare_guest_switch,
2857 .vcpu_load = svm_vcpu_load,
2858 .vcpu_put = svm_vcpu_put,
2859
2860 .set_guest_debug = svm_guest_debug,
2861 .get_msr = svm_get_msr,
2862 .set_msr = svm_set_msr,
2863 .get_segment_base = svm_get_segment_base,
2864 .get_segment = svm_get_segment,
2865 .set_segment = svm_set_segment,
2866 .get_cpl = svm_get_cpl,
2867 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
2868 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
2869 .set_cr0 = svm_set_cr0,
2870 .set_cr3 = svm_set_cr3,
2871 .set_cr4 = svm_set_cr4,
2872 .set_efer = svm_set_efer,
2873 .get_idt = svm_get_idt,
2874 .set_idt = svm_set_idt,
2875 .get_gdt = svm_get_gdt,
2876 .set_gdt = svm_set_gdt,
2877 .get_dr = svm_get_dr,
2878 .set_dr = svm_set_dr,
2879 .cache_reg = svm_cache_reg,
2880 .get_rflags = svm_get_rflags,
2881 .set_rflags = svm_set_rflags,
2882
2883 .tlb_flush = svm_flush_tlb,
2884
2885 .run = svm_vcpu_run,
2886 .handle_exit = handle_exit,
2887 .skip_emulated_instruction = skip_emulated_instruction,
2888 .set_interrupt_shadow = svm_set_interrupt_shadow,
2889 .get_interrupt_shadow = svm_get_interrupt_shadow,
2890 .patch_hypercall = svm_patch_hypercall,
2891 .set_irq = svm_set_irq,
2892 .set_nmi = svm_inject_nmi,
2893 .queue_exception = svm_queue_exception,
2894 .interrupt_allowed = svm_interrupt_allowed,
2895 .nmi_allowed = svm_nmi_allowed,
2896 .enable_nmi_window = enable_nmi_window,
2897 .enable_irq_window = enable_irq_window,
2898 .update_cr8_intercept = update_cr8_intercept,
2899
2900 .set_tss_addr = svm_set_tss_addr,
2901 .get_tdp_level = get_npt_level,
2902 .get_mt_mask = svm_get_mt_mask,
2903
2904 .exit_reasons_str = svm_exit_reasons_str,
2905 .gb_page_enable = svm_gb_page_enable,
2906 };
2907
2908 static int __init svm_init(void)
2909 {
2910 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
2911 THIS_MODULE);
2912 }
2913
2914 static void __exit svm_exit(void)
2915 {
2916 kvm_exit();
2917 }
2918
2919 module_init(svm_init)
2920 module_exit(svm_exit)
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