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Full support for Ginger Console
[linux-ginger.git] / drivers / ata / ata_piix.c
blob9ac4e378992ef60d71634121379b91479c8660f2
1 /*
2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below, going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 * ICH7 errata #16 - MWDMA1 timings are incorrect
76 *
77 * Should have been BIOS fixed:
78 * 450NX: errata #19 - DMA hangs on old 450NX
79 * 450NX: errata #20 - DMA hangs on old 450NX
80 * 450NX: errata #25 - Corruption with DMA on old 450NX
81 * ICH3 errata #15 - IDE deadlock under high load
82 * (BIOS must set dev 31 fn 0 bit 23)
83 * ICH3 errata #18 - Don't use native mode
84 */
85
86 #include <linux/kernel.h>
87 #include <linux/module.h>
88 #include <linux/pci.h>
89 #include <linux/init.h>
90 #include <linux/blkdev.h>
91 #include <linux/delay.h>
92 #include <linux/device.h>
93 #include <scsi/scsi_host.h>
94 #include <linux/libata.h>
95 #include <linux/dmi.h>
96
97 #define DRV_NAME "ata_piix"
98 #define DRV_VERSION "2.13"
99
100 enum {
101 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
102 ICH5_PMR = 0x90, /* port mapping register */
103 ICH5_PCS = 0x92, /* port control and status */
104 PIIX_SIDPR_BAR = 5,
105 PIIX_SIDPR_LEN = 16,
106 PIIX_SIDPR_IDX = 0,
107 PIIX_SIDPR_DATA = 4,
108
109 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
110 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */
111
112 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
113 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
114
115 PIIX_80C_PRI = (1 << 5) | (1 << 4),
116 PIIX_80C_SEC = (1 << 7) | (1 << 6),
117
118 /* constants for mapping table */
119 P0 = 0, /* port 0 */
120 P1 = 1, /* port 1 */
121 P2 = 2, /* port 2 */
122 P3 = 3, /* port 3 */
123 IDE = -1, /* IDE */
124 NA = -2, /* not avaliable */
125 RV = -3, /* reserved */
126
127 PIIX_AHCI_DEVICE = 6,
128
129 /* host->flags bits */
130 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
131 };
132
133 enum piix_controller_ids {
134 /* controller IDs */
135 piix_pata_mwdma, /* PIIX3 MWDMA only */
136 piix_pata_33, /* PIIX4 at 33Mhz */
137 ich_pata_33, /* ICH up to UDMA 33 only */
138 ich_pata_66, /* ICH up to 66 Mhz */
139 ich_pata_100, /* ICH up to UDMA 100 */
140 ich_pata_100_nomwdma1, /* ICH up to UDMA 100 but with no MWDMA1*/
141 ich5_sata,
142 ich6_sata,
143 ich6m_sata,
144 ich8_sata,
145 ich8_2port_sata,
146 ich8m_apple_sata, /* locks up on second port enable */
147 tolapai_sata,
148 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
149 };
150
151 struct piix_map_db {
152 const u32 mask;
153 const u16 port_enable;
154 const int map[][4];
155 };
156
157 struct piix_host_priv {
158 const int *map;
159 u32 saved_iocfg;
160 void __iomem *sidpr;
161 };
162
163 static int piix_init_one(struct pci_dev *pdev,
164 const struct pci_device_id *ent);
165 static void piix_remove_one(struct pci_dev *pdev);
166 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline);
167 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
168 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
169 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
170 static int ich_pata_cable_detect(struct ata_port *ap);
171 static u8 piix_vmw_bmdma_status(struct ata_port *ap);
172 static int piix_sidpr_scr_read(struct ata_link *link,
173 unsigned int reg, u32 *val);
174 static int piix_sidpr_scr_write(struct ata_link *link,
175 unsigned int reg, u32 val);
176 #ifdef CONFIG_PM
177 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
178 static int piix_pci_device_resume(struct pci_dev *pdev);
179 #endif
180
181 static unsigned int in_module_init = 1;
182
183 static const struct pci_device_id piix_pci_tbl[] = {
184 /* Intel PIIX3 for the 430HX etc */
185 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
186 /* VMware ICH4 */
187 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
188 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
189 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
190 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
191 /* Intel PIIX4 */
192 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
193 /* Intel PIIX4 */
194 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
195 /* Intel PIIX */
196 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
197 /* Intel ICH (i810, i815, i840) UDMA 66*/
198 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
199 /* Intel ICH0 : UDMA 33*/
200 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
201 /* Intel ICH2M */
202 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
203 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
204 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
205 /* Intel ICH3M */
206 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
207 /* Intel ICH3 (E7500/1) UDMA 100 */
208 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
209 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
210 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
211 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
212 /* Intel ICH5 */
213 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
214 /* C-ICH (i810E2) */
215 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
216 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
217 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
218 /* ICH6 (and 6) (i915) UDMA 100 */
219 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
220 /* ICH7/7-R (i945, i975) UDMA 100*/
221 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
222 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
223 /* ICH8 Mobile PATA Controller */
224 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
225
226 /* SATA ports */
227
228 /* 82801EB (ICH5) */
229 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
230 /* 82801EB (ICH5) */
231 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
232 /* 6300ESB (ICH5 variant with broken PCS present bits) */
233 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
234 /* 6300ESB pretending RAID */
235 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
236 /* 82801FB/FW (ICH6/ICH6W) */
237 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
238 /* 82801FR/FRW (ICH6R/ICH6RW) */
239 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
240 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
241 * Attach iff the controller is in IDE mode. */
242 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
243 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
244 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
245 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
246 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
247 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
248 /* Enterprise Southbridge 2 (631xESB/632xESB) */
249 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
250 /* SATA Controller 1 IDE (ICH8) */
251 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
252 /* SATA Controller 2 IDE (ICH8) */
253 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
254 /* Mobile SATA Controller IDE (ICH8M), Apple */
255 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
256 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
257 { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata },
258 /* Mobile SATA Controller IDE (ICH8M) */
259 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
260 /* SATA Controller IDE (ICH9) */
261 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
262 /* SATA Controller IDE (ICH9) */
263 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
264 /* SATA Controller IDE (ICH9) */
265 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
266 /* SATA Controller IDE (ICH9M) */
267 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
268 /* SATA Controller IDE (ICH9M) */
269 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
270 /* SATA Controller IDE (ICH9M) */
271 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
272 /* SATA Controller IDE (Tolapai) */
273 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
274 /* SATA Controller IDE (ICH10) */
275 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
276 /* SATA Controller IDE (ICH10) */
277 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
278 /* SATA Controller IDE (ICH10) */
279 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
280 /* SATA Controller IDE (ICH10) */
281 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
282 /* SATA Controller IDE (PCH) */
283 { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
284 /* SATA Controller IDE (PCH) */
285 { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
286 /* SATA Controller IDE (PCH) */
287 { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
288 /* SATA Controller IDE (PCH) */
289 { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
290 /* SATA Controller IDE (PCH) */
291 { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
292 /* SATA Controller IDE (PCH) */
293 { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
294 { } /* terminate list */
295 };
296
297 static struct pci_driver piix_pci_driver = {
298 .name = DRV_NAME,
299 .id_table = piix_pci_tbl,
300 .probe = piix_init_one,
301 .remove = piix_remove_one,
302 #ifdef CONFIG_PM
303 .suspend = piix_pci_device_suspend,
304 .resume = piix_pci_device_resume,
305 #endif
306 };
307
308 static struct scsi_host_template piix_sht = {
309 ATA_BMDMA_SHT(DRV_NAME),
310 };
311
312 static struct ata_port_operations piix_pata_ops = {
313 .inherits = &ata_bmdma32_port_ops,
314 .cable_detect = ata_cable_40wire,
315 .set_piomode = piix_set_piomode,
316 .set_dmamode = piix_set_dmamode,
317 .prereset = piix_pata_prereset,
318 };
319
320 static struct ata_port_operations piix_vmw_ops = {
321 .inherits = &piix_pata_ops,
322 .bmdma_status = piix_vmw_bmdma_status,
323 };
324
325 static struct ata_port_operations ich_pata_ops = {
326 .inherits = &piix_pata_ops,
327 .cable_detect = ich_pata_cable_detect,
328 .set_dmamode = ich_set_dmamode,
329 };
330
331 static struct ata_port_operations piix_sata_ops = {
332 .inherits = &ata_bmdma_port_ops,
333 };
334
335 static struct ata_port_operations piix_sidpr_sata_ops = {
336 .inherits = &piix_sata_ops,
337 .hardreset = sata_std_hardreset,
338 .scr_read = piix_sidpr_scr_read,
339 .scr_write = piix_sidpr_scr_write,
340 };
341
342 static const struct piix_map_db ich5_map_db = {
343 .mask = 0x7,
344 .port_enable = 0x3,
345 .map = {
346 /* PM PS SM SS MAP */
347 { P0, NA, P1, NA }, /* 000b */
348 { P1, NA, P0, NA }, /* 001b */
349 { RV, RV, RV, RV },
350 { RV, RV, RV, RV },
351 { P0, P1, IDE, IDE }, /* 100b */
352 { P1, P0, IDE, IDE }, /* 101b */
353 { IDE, IDE, P0, P1 }, /* 110b */
354 { IDE, IDE, P1, P0 }, /* 111b */
355 },
356 };
357
358 static const struct piix_map_db ich6_map_db = {
359 .mask = 0x3,
360 .port_enable = 0xf,
361 .map = {
362 /* PM PS SM SS MAP */
363 { P0, P2, P1, P3 }, /* 00b */
364 { IDE, IDE, P1, P3 }, /* 01b */
365 { P0, P2, IDE, IDE }, /* 10b */
366 { RV, RV, RV, RV },
367 },
368 };
369
370 static const struct piix_map_db ich6m_map_db = {
371 .mask = 0x3,
372 .port_enable = 0x5,
373
374 /* Map 01b isn't specified in the doc but some notebooks use
375 * it anyway. MAP 01b have been spotted on both ICH6M and
376 * ICH7M.
377 */
378 .map = {
379 /* PM PS SM SS MAP */
380 { P0, P2, NA, NA }, /* 00b */
381 { IDE, IDE, P1, P3 }, /* 01b */
382 { P0, P2, IDE, IDE }, /* 10b */
383 { RV, RV, RV, RV },
384 },
385 };
386
387 static const struct piix_map_db ich8_map_db = {
388 .mask = 0x3,
389 .port_enable = 0xf,
390 .map = {
391 /* PM PS SM SS MAP */
392 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
393 { RV, RV, RV, RV },
394 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
395 { RV, RV, RV, RV },
396 },
397 };
398
399 static const struct piix_map_db ich8_2port_map_db = {
400 .mask = 0x3,
401 .port_enable = 0x3,
402 .map = {
403 /* PM PS SM SS MAP */
404 { P0, NA, P1, NA }, /* 00b */
405 { RV, RV, RV, RV }, /* 01b */
406 { RV, RV, RV, RV }, /* 10b */
407 { RV, RV, RV, RV },
408 },
409 };
410
411 static const struct piix_map_db ich8m_apple_map_db = {
412 .mask = 0x3,
413 .port_enable = 0x1,
414 .map = {
415 /* PM PS SM SS MAP */
416 { P0, NA, NA, NA }, /* 00b */
417 { RV, RV, RV, RV },
418 { P0, P2, IDE, IDE }, /* 10b */
419 { RV, RV, RV, RV },
420 },
421 };
422
423 static const struct piix_map_db tolapai_map_db = {
424 .mask = 0x3,
425 .port_enable = 0x3,
426 .map = {
427 /* PM PS SM SS MAP */
428 { P0, NA, P1, NA }, /* 00b */
429 { RV, RV, RV, RV }, /* 01b */
430 { RV, RV, RV, RV }, /* 10b */
431 { RV, RV, RV, RV },
432 },
433 };
434
435 static const struct piix_map_db *piix_map_db_table[] = {
436 [ich5_sata] = &ich5_map_db,
437 [ich6_sata] = &ich6_map_db,
438 [ich6m_sata] = &ich6m_map_db,
439 [ich8_sata] = &ich8_map_db,
440 [ich8_2port_sata] = &ich8_2port_map_db,
441 [ich8m_apple_sata] = &ich8m_apple_map_db,
442 [tolapai_sata] = &tolapai_map_db,
443 };
444
445 static struct ata_port_info piix_port_info[] = {
446 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
447 {
448 .flags = PIIX_PATA_FLAGS,
449 .pio_mask = ATA_PIO4,
450 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
451 .port_ops = &piix_pata_ops,
452 },
453
454 [piix_pata_33] = /* PIIX4 at 33MHz */
455 {
456 .flags = PIIX_PATA_FLAGS,
457 .pio_mask = ATA_PIO4,
458 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
459 .udma_mask = ATA_UDMA2,
460 .port_ops = &piix_pata_ops,
461 },
462
463 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
464 {
465 .flags = PIIX_PATA_FLAGS,
466 .pio_mask = ATA_PIO4,
467 .mwdma_mask = ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok */
468 .udma_mask = ATA_UDMA2,
469 .port_ops = &ich_pata_ops,
470 },
471
472 [ich_pata_66] = /* ICH controllers up to 66MHz */
473 {
474 .flags = PIIX_PATA_FLAGS,
475 .pio_mask = ATA_PIO4,
476 .mwdma_mask = ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */
477 .udma_mask = ATA_UDMA4,
478 .port_ops = &ich_pata_ops,
479 },
480
481 [ich_pata_100] =
482 {
483 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
484 .pio_mask = ATA_PIO4,
485 .mwdma_mask = ATA_MWDMA12_ONLY,
486 .udma_mask = ATA_UDMA5,
487 .port_ops = &ich_pata_ops,
488 },
489
490 [ich_pata_100_nomwdma1] =
491 {
492 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
493 .pio_mask = ATA_PIO4,
494 .mwdma_mask = ATA_MWDMA2_ONLY,
495 .udma_mask = ATA_UDMA5,
496 .port_ops = &ich_pata_ops,
497 },
498
499 [ich5_sata] =
500 {
501 .flags = PIIX_SATA_FLAGS,
502 .pio_mask = ATA_PIO4,
503 .mwdma_mask = ATA_MWDMA2,
504 .udma_mask = ATA_UDMA6,
505 .port_ops = &piix_sata_ops,
506 },
507
508 [ich6_sata] =
509 {
510 .flags = PIIX_SATA_FLAGS,
511 .pio_mask = ATA_PIO4,
512 .mwdma_mask = ATA_MWDMA2,
513 .udma_mask = ATA_UDMA6,
514 .port_ops = &piix_sata_ops,
515 },
516
517 [ich6m_sata] =
518 {
519 .flags = PIIX_SATA_FLAGS,
520 .pio_mask = ATA_PIO4,
521 .mwdma_mask = ATA_MWDMA2,
522 .udma_mask = ATA_UDMA6,
523 .port_ops = &piix_sata_ops,
524 },
525
526 [ich8_sata] =
527 {
528 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
529 .pio_mask = ATA_PIO4,
530 .mwdma_mask = ATA_MWDMA2,
531 .udma_mask = ATA_UDMA6,
532 .port_ops = &piix_sata_ops,
533 },
534
535 [ich8_2port_sata] =
536 {
537 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
538 .pio_mask = ATA_PIO4,
539 .mwdma_mask = ATA_MWDMA2,
540 .udma_mask = ATA_UDMA6,
541 .port_ops = &piix_sata_ops,
542 },
543
544 [tolapai_sata] =
545 {
546 .flags = PIIX_SATA_FLAGS,
547 .pio_mask = ATA_PIO4,
548 .mwdma_mask = ATA_MWDMA2,
549 .udma_mask = ATA_UDMA6,
550 .port_ops = &piix_sata_ops,
551 },
552
553 [ich8m_apple_sata] =
554 {
555 .flags = PIIX_SATA_FLAGS,
556 .pio_mask = ATA_PIO4,
557 .mwdma_mask = ATA_MWDMA2,
558 .udma_mask = ATA_UDMA6,
559 .port_ops = &piix_sata_ops,
560 },
561
562 [piix_pata_vmw] =
563 {
564 .flags = PIIX_PATA_FLAGS,
565 .pio_mask = ATA_PIO4,
566 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
567 .udma_mask = ATA_UDMA2,
568 .port_ops = &piix_vmw_ops,
569 },
570
571 };
572
573 static struct pci_bits piix_enable_bits[] = {
574 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
575 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
576 };
577
578 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
579 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
580 MODULE_LICENSE("GPL");
581 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
582 MODULE_VERSION(DRV_VERSION);
583
584 struct ich_laptop {
585 u16 device;
586 u16 subvendor;
587 u16 subdevice;
588 };
589
590 /*
591 * List of laptops that use short cables rather than 80 wire
592 */
593
594 static const struct ich_laptop ich_laptop[] = {
595 /* devid, subvendor, subdev */
596 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
597 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
598 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
599 { 0x27DF, 0x1028, 0x02b0 }, /* ICH7 on unknown Dell */
600 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
601 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
602 { 0x27DF, 0x103C, 0x361a }, /* ICH7 on unkown HP */
603 { 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */
604 { 0x27DF, 0x152D, 0x0778 }, /* ICH7 on unknown Intel */
605 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
606 { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */
607 { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */
608 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
609 { 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */
610 /* end marker */
611 { 0, }
612 };
613
614 /**
615 * ich_pata_cable_detect - Probe host controller cable detect info
616 * @ap: Port for which cable detect info is desired
617 *
618 * Read 80c cable indicator from ATA PCI device's PCI config
619 * register. This register is normally set by firmware (BIOS).
620 *
621 * LOCKING:
622 * None (inherited from caller).
623 */
624
625 static int ich_pata_cable_detect(struct ata_port *ap)
626 {
627 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
628 struct piix_host_priv *hpriv = ap->host->private_data;
629 const struct ich_laptop *lap = &ich_laptop[0];
630 u8 mask;
631
632 /* Check for specials - Acer Aspire 5602WLMi */
633 while (lap->device) {
634 if (lap->device == pdev->device &&
635 lap->subvendor == pdev->subsystem_vendor &&
636 lap->subdevice == pdev->subsystem_device)
637 return ATA_CBL_PATA40_SHORT;
638
639 lap++;
640 }
641
642 /* check BIOS cable detect results */
643 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
644 if ((hpriv->saved_iocfg & mask) == 0)
645 return ATA_CBL_PATA40;
646 return ATA_CBL_PATA80;
647 }
648
649 /**
650 * piix_pata_prereset - prereset for PATA host controller
651 * @link: Target link
652 * @deadline: deadline jiffies for the operation
653 *
654 * LOCKING:
655 * None (inherited from caller).
656 */
657 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
658 {
659 struct ata_port *ap = link->ap;
660 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
661
662 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
663 return -ENOENT;
664 return ata_sff_prereset(link, deadline);
665 }
666
667 static DEFINE_SPINLOCK(piix_lock);
668
669 /**
670 * piix_set_piomode - Initialize host controller PATA PIO timings
671 * @ap: Port whose timings we are configuring
672 * @adev: um
673 *
674 * Set PIO mode for device, in host controller PCI config space.
675 *
676 * LOCKING:
677 * None (inherited from caller).
678 */
679
680 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
681 {
682 struct pci_dev *dev = to_pci_dev(ap->host->dev);
683 unsigned long flags;
684 unsigned int pio = adev->pio_mode - XFER_PIO_0;
685 unsigned int is_slave = (adev->devno != 0);
686 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
687 unsigned int slave_port = 0x44;
688 u16 master_data;
689 u8 slave_data;
690 u8 udma_enable;
691 int control = 0;
692
693 /*
694 * See Intel Document 298600-004 for the timing programing rules
695 * for ICH controllers.
696 */
697
698 static const /* ISP RTC */
699 u8 timings[][2] = { { 0, 0 },
700 { 0, 0 },
701 { 1, 0 },
702 { 2, 1 },
703 { 2, 3 }, };
704
705 if (pio >= 2)
706 control |= 1; /* TIME1 enable */
707 if (ata_pio_need_iordy(adev))
708 control |= 2; /* IE enable */
709
710 /* Intel specifies that the PPE functionality is for disk only */
711 if (adev->class == ATA_DEV_ATA)
712 control |= 4; /* PPE enable */
713
714 spin_lock_irqsave(&piix_lock, flags);
715
716 /* PIO configuration clears DTE unconditionally. It will be
717 * programmed in set_dmamode which is guaranteed to be called
718 * after set_piomode if any DMA mode is available.
719 */
720 pci_read_config_word(dev, master_port, &master_data);
721 if (is_slave) {
722 /* clear TIME1|IE1|PPE1|DTE1 */
723 master_data &= 0xff0f;
724 /* Enable SITRE (separate slave timing register) */
725 master_data |= 0x4000;
726 /* enable PPE1, IE1 and TIME1 as needed */
727 master_data |= (control << 4);
728 pci_read_config_byte(dev, slave_port, &slave_data);
729 slave_data &= (ap->port_no ? 0x0f : 0xf0);
730 /* Load the timing nibble for this slave */
731 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
732 << (ap->port_no ? 4 : 0);
733 } else {
734 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
735 master_data &= 0xccf0;
736 /* Enable PPE, IE and TIME as appropriate */
737 master_data |= control;
738 /* load ISP and RCT */
739 master_data |=
740 (timings[pio][0] << 12) |
741 (timings[pio][1] << 8);
742 }
743 pci_write_config_word(dev, master_port, master_data);
744 if (is_slave)
745 pci_write_config_byte(dev, slave_port, slave_data);
746
747 /* Ensure the UDMA bit is off - it will be turned back on if
748 UDMA is selected */
749
750 if (ap->udma_mask) {
751 pci_read_config_byte(dev, 0x48, &udma_enable);
752 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
753 pci_write_config_byte(dev, 0x48, udma_enable);
754 }
755
756 spin_unlock_irqrestore(&piix_lock, flags);
757 }
758
759 /**
760 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
761 * @ap: Port whose timings we are configuring
762 * @adev: Drive in question
763 * @isich: set if the chip is an ICH device
764 *
765 * Set UDMA mode for device, in host controller PCI config space.
766 *
767 * LOCKING:
768 * None (inherited from caller).
769 */
770
771 static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
772 {
773 struct pci_dev *dev = to_pci_dev(ap->host->dev);
774 unsigned long flags;
775 u8 master_port = ap->port_no ? 0x42 : 0x40;
776 u16 master_data;
777 u8 speed = adev->dma_mode;
778 int devid = adev->devno + 2 * ap->port_no;
779 u8 udma_enable = 0;
780
781 static const /* ISP RTC */
782 u8 timings[][2] = { { 0, 0 },
783 { 0, 0 },
784 { 1, 0 },
785 { 2, 1 },
786 { 2, 3 }, };
787
788 spin_lock_irqsave(&piix_lock, flags);
789
790 pci_read_config_word(dev, master_port, &master_data);
791 if (ap->udma_mask)
792 pci_read_config_byte(dev, 0x48, &udma_enable);
793
794 if (speed >= XFER_UDMA_0) {
795 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
796 u16 udma_timing;
797 u16 ideconf;
798 int u_clock, u_speed;
799
800 /*
801 * UDMA is handled by a combination of clock switching and
802 * selection of dividers
803 *
804 * Handy rule: Odd modes are UDMATIMx 01, even are 02
805 * except UDMA0 which is 00
806 */
807 u_speed = min(2 - (udma & 1), udma);
808 if (udma == 5)
809 u_clock = 0x1000; /* 100Mhz */
810 else if (udma > 2)
811 u_clock = 1; /* 66Mhz */
812 else
813 u_clock = 0; /* 33Mhz */
814
815 udma_enable |= (1 << devid);
816
817 /* Load the CT/RP selection */
818 pci_read_config_word(dev, 0x4A, &udma_timing);
819 udma_timing &= ~(3 << (4 * devid));
820 udma_timing |= u_speed << (4 * devid);
821 pci_write_config_word(dev, 0x4A, udma_timing);
822
823 if (isich) {
824 /* Select a 33/66/100Mhz clock */
825 pci_read_config_word(dev, 0x54, &ideconf);
826 ideconf &= ~(0x1001 << devid);
827 ideconf |= u_clock << devid;
828 /* For ICH or later we should set bit 10 for better
829 performance (WR_PingPong_En) */
830 pci_write_config_word(dev, 0x54, ideconf);
831 }
832 } else {
833 /*
834 * MWDMA is driven by the PIO timings. We must also enable
835 * IORDY unconditionally along with TIME1. PPE has already
836 * been set when the PIO timing was set.
837 */
838 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
839 unsigned int control;
840 u8 slave_data;
841 const unsigned int needed_pio[3] = {
842 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
843 };
844 int pio = needed_pio[mwdma] - XFER_PIO_0;
845
846 control = 3; /* IORDY|TIME1 */
847
848 /* If the drive MWDMA is faster than it can do PIO then
849 we must force PIO into PIO0 */
850
851 if (adev->pio_mode < needed_pio[mwdma])
852 /* Enable DMA timing only */
853 control |= 8; /* PIO cycles in PIO0 */
854
855 if (adev->devno) { /* Slave */
856 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
857 master_data |= control << 4;
858 pci_read_config_byte(dev, 0x44, &slave_data);
859 slave_data &= (ap->port_no ? 0x0f : 0xf0);
860 /* Load the matching timing */
861 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
862 pci_write_config_byte(dev, 0x44, slave_data);
863 } else { /* Master */
864 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
865 and master timing bits */
866 master_data |= control;
867 master_data |=
868 (timings[pio][0] << 12) |
869 (timings[pio][1] << 8);
870 }
871
872 if (ap->udma_mask) {
873 udma_enable &= ~(1 << devid);
874 pci_write_config_word(dev, master_port, master_data);
875 }
876 }
877 /* Don't scribble on 0x48 if the controller does not support UDMA */
878 if (ap->udma_mask)
879 pci_write_config_byte(dev, 0x48, udma_enable);
880
881 spin_unlock_irqrestore(&piix_lock, flags);
882 }
883
884 /**
885 * piix_set_dmamode - Initialize host controller PATA DMA timings
886 * @ap: Port whose timings we are configuring
887 * @adev: um
888 *
889 * Set MW/UDMA mode for device, in host controller PCI config space.
890 *
891 * LOCKING:
892 * None (inherited from caller).
893 */
894
895 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
896 {
897 do_pata_set_dmamode(ap, adev, 0);
898 }
899
900 /**
901 * ich_set_dmamode - Initialize host controller PATA DMA timings
902 * @ap: Port whose timings we are configuring
903 * @adev: um
904 *
905 * Set MW/UDMA mode for device, in host controller PCI config space.
906 *
907 * LOCKING:
908 * None (inherited from caller).
909 */
910
911 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
912 {
913 do_pata_set_dmamode(ap, adev, 1);
914 }
915
916 /*
917 * Serial ATA Index/Data Pair Superset Registers access
918 *
919 * Beginning from ICH8, there's a sane way to access SCRs using index
920 * and data register pair located at BAR5 which means that we have
921 * separate SCRs for master and slave. This is handled using libata
922 * slave_link facility.
923 */
924 static const int piix_sidx_map[] = {
925 [SCR_STATUS] = 0,
926 [SCR_ERROR] = 2,
927 [SCR_CONTROL] = 1,
928 };
929
930 static void piix_sidpr_sel(struct ata_link *link, unsigned int reg)
931 {
932 struct ata_port *ap = link->ap;
933 struct piix_host_priv *hpriv = ap->host->private_data;
934
935 iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg],
936 hpriv->sidpr + PIIX_SIDPR_IDX);
937 }
938
939 static int piix_sidpr_scr_read(struct ata_link *link,
940 unsigned int reg, u32 *val)
941 {
942 struct piix_host_priv *hpriv = link->ap->host->private_data;
943
944 if (reg >= ARRAY_SIZE(piix_sidx_map))
945 return -EINVAL;
946
947 piix_sidpr_sel(link, reg);
948 *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
949 return 0;
950 }
951
952 static int piix_sidpr_scr_write(struct ata_link *link,
953 unsigned int reg, u32 val)
954 {
955 struct piix_host_priv *hpriv = link->ap->host->private_data;
956
957 if (reg >= ARRAY_SIZE(piix_sidx_map))
958 return -EINVAL;
959
960 piix_sidpr_sel(link, reg);
961 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
962 return 0;
963 }
964
965 #ifdef CONFIG_PM
966 static int piix_broken_suspend(void)
967 {
968 static const struct dmi_system_id sysids[] = {
969 {
970 .ident = "TECRA M3",
971 .matches = {
972 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
973 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
974 },
975 },
976 {
977 .ident = "TECRA M3",
978 .matches = {
979 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
980 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
981 },
982 },
983 {
984 .ident = "TECRA M4",
985 .matches = {
986 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
987 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
988 },
989 },
990 {
991 .ident = "TECRA M4",
992 .matches = {
993 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
994 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
995 },
996 },
997 {
998 .ident = "TECRA M5",
999 .matches = {
1000 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1001 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
1002 },
1003 },
1004 {
1005 .ident = "TECRA M6",
1006 .matches = {
1007 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1008 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
1009 },
1010 },
1011 {
1012 .ident = "TECRA M7",
1013 .matches = {
1014 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1015 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
1016 },
1017 },
1018 {
1019 .ident = "TECRA A8",
1020 .matches = {
1021 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1022 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
1023 },
1024 },
1025 {
1026 .ident = "Satellite R20",
1027 .matches = {
1028 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1029 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
1030 },
1031 },
1032 {
1033 .ident = "Satellite R25",
1034 .matches = {
1035 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1036 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
1037 },
1038 },
1039 {
1040 .ident = "Satellite U200",
1041 .matches = {
1042 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1043 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
1044 },
1045 },
1046 {
1047 .ident = "Satellite U200",
1048 .matches = {
1049 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1050 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
1051 },
1052 },
1053 {
1054 .ident = "Satellite Pro U200",
1055 .matches = {
1056 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1057 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
1058 },
1059 },
1060 {
1061 .ident = "Satellite U205",
1062 .matches = {
1063 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1064 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
1065 },
1066 },
1067 {
1068 .ident = "SATELLITE U205",
1069 .matches = {
1070 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1071 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
1072 },
1073 },
1074 {
1075 .ident = "Portege M500",
1076 .matches = {
1077 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1078 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
1079 },
1080 },
1081 {
1082 .ident = "VGN-BX297XP",
1083 .matches = {
1084 DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"),
1085 DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"),
1086 },
1087 },
1088
1089 { } /* terminate list */
1090 };
1091 static const char *oemstrs[] = {
1092 "Tecra M3,",
1093 };
1094 int i;
1095
1096 if (dmi_check_system(sysids))
1097 return 1;
1098
1099 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
1100 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
1101 return 1;
1102
1103 /* TECRA M4 sometimes forgets its identify and reports bogus
1104 * DMI information. As the bogus information is a bit
1105 * generic, match as many entries as possible. This manual
1106 * matching is necessary because dmi_system_id.matches is
1107 * limited to four entries.
1108 */
1109 if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") &&
1110 dmi_match(DMI_PRODUCT_NAME, "000000") &&
1111 dmi_match(DMI_PRODUCT_VERSION, "000000") &&
1112 dmi_match(DMI_PRODUCT_SERIAL, "000000") &&
1113 dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") &&
1114 dmi_match(DMI_BOARD_NAME, "Portable PC") &&
1115 dmi_match(DMI_BOARD_VERSION, "Version A0"))
1116 return 1;
1117
1118 return 0;
1119 }
1120
1121 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1122 {
1123 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1124 unsigned long flags;
1125 int rc = 0;
1126
1127 rc = ata_host_suspend(host, mesg);
1128 if (rc)
1129 return rc;
1130
1131 /* Some braindamaged ACPI suspend implementations expect the
1132 * controller to be awake on entry; otherwise, it burns cpu
1133 * cycles and power trying to do something to the sleeping
1134 * beauty.
1135 */
1136 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
1137 pci_save_state(pdev);
1138
1139 /* mark its power state as "unknown", since we don't
1140 * know if e.g. the BIOS will change its device state
1141 * when we suspend.
1142 */
1143 if (pdev->current_state == PCI_D0)
1144 pdev->current_state = PCI_UNKNOWN;
1145
1146 /* tell resume that it's waking up from broken suspend */
1147 spin_lock_irqsave(&host->lock, flags);
1148 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1149 spin_unlock_irqrestore(&host->lock, flags);
1150 } else
1151 ata_pci_device_do_suspend(pdev, mesg);
1152
1153 return 0;
1154 }
1155
1156 static int piix_pci_device_resume(struct pci_dev *pdev)
1157 {
1158 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1159 unsigned long flags;
1160 int rc;
1161
1162 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1163 spin_lock_irqsave(&host->lock, flags);
1164 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1165 spin_unlock_irqrestore(&host->lock, flags);
1166
1167 pci_set_power_state(pdev, PCI_D0);
1168 pci_restore_state(pdev);
1169
1170 /* PCI device wasn't disabled during suspend. Use
1171 * pci_reenable_device() to avoid affecting the enable
1172 * count.
1173 */
1174 rc = pci_reenable_device(pdev);
1175 if (rc)
1176 dev_printk(KERN_ERR, &pdev->dev, "failed to enable "
1177 "device after resume (%d)\n", rc);
1178 } else
1179 rc = ata_pci_device_do_resume(pdev);
1180
1181 if (rc == 0)
1182 ata_host_resume(host);
1183
1184 return rc;
1185 }
1186 #endif
1187
1188 static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1189 {
1190 return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1191 }
1192
1193 #define AHCI_PCI_BAR 5
1194 #define AHCI_GLOBAL_CTL 0x04
1195 #define AHCI_ENABLE (1 << 31)
1196 static int piix_disable_ahci(struct pci_dev *pdev)
1197 {
1198 void __iomem *mmio;
1199 u32 tmp;
1200 int rc = 0;
1201
1202 /* BUG: pci_enable_device has not yet been called. This
1203 * works because this device is usually set up by BIOS.
1204 */
1205
1206 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1207 !pci_resource_len(pdev, AHCI_PCI_BAR))
1208 return 0;
1209
1210 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1211 if (!mmio)
1212 return -ENOMEM;
1213
1214 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1215 if (tmp & AHCI_ENABLE) {
1216 tmp &= ~AHCI_ENABLE;
1217 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
1218
1219 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1220 if (tmp & AHCI_ENABLE)
1221 rc = -EIO;
1222 }
1223
1224 pci_iounmap(pdev, mmio);
1225 return rc;
1226 }
1227
1228 /**
1229 * piix_check_450nx_errata - Check for problem 450NX setup
1230 * @ata_dev: the PCI device to check
1231 *
1232 * Check for the present of 450NX errata #19 and errata #25. If
1233 * they are found return an error code so we can turn off DMA
1234 */
1235
1236 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1237 {
1238 struct pci_dev *pdev = NULL;
1239 u16 cfg;
1240 int no_piix_dma = 0;
1241
1242 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
1243 /* Look for 450NX PXB. Check for problem configurations
1244 A PCI quirk checks bit 6 already */
1245 pci_read_config_word(pdev, 0x41, &cfg);
1246 /* Only on the original revision: IDE DMA can hang */
1247 if (pdev->revision == 0x00)
1248 no_piix_dma = 1;
1249 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1250 else if (cfg & (1<<14) && pdev->revision < 5)
1251 no_piix_dma = 2;
1252 }
1253 if (no_piix_dma)
1254 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
1255 if (no_piix_dma == 2)
1256 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
1257 return no_piix_dma;
1258 }
1259
1260 static void __devinit piix_init_pcs(struct ata_host *host,
1261 const struct piix_map_db *map_db)
1262 {
1263 struct pci_dev *pdev = to_pci_dev(host->dev);
1264 u16 pcs, new_pcs;
1265
1266 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1267
1268 new_pcs = pcs | map_db->port_enable;
1269
1270 if (new_pcs != pcs) {
1271 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1272 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1273 msleep(150);
1274 }
1275 }
1276
1277 static const int *__devinit piix_init_sata_map(struct pci_dev *pdev,
1278 struct ata_port_info *pinfo,
1279 const struct piix_map_db *map_db)
1280 {
1281 const int *map;
1282 int i, invalid_map = 0;
1283 u8 map_value;
1284
1285 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1286
1287 map = map_db->map[map_value & map_db->mask];
1288
1289 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1290 for (i = 0; i < 4; i++) {
1291 switch (map[i]) {
1292 case RV:
1293 invalid_map = 1;
1294 printk(" XX");
1295 break;
1296
1297 case NA:
1298 printk(" --");
1299 break;
1300
1301 case IDE:
1302 WARN_ON((i & 1) || map[i + 1] != IDE);
1303 pinfo[i / 2] = piix_port_info[ich_pata_100];
1304 i++;
1305 printk(" IDE IDE");
1306 break;
1307
1308 default:
1309 printk(" P%d", map[i]);
1310 if (i & 1)
1311 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1312 break;
1313 }
1314 }
1315 printk(" ]\n");
1316
1317 if (invalid_map)
1318 dev_printk(KERN_ERR, &pdev->dev,
1319 "invalid MAP value %u\n", map_value);
1320
1321 return map;
1322 }
1323
1324 static bool piix_no_sidpr(struct ata_host *host)
1325 {
1326 struct pci_dev *pdev = to_pci_dev(host->dev);
1327
1328 /*
1329 * Samsung DB-P70 only has three ATA ports exposed and
1330 * curiously the unconnected first port reports link online
1331 * while not responding to SRST protocol causing excessive
1332 * detection delay.
1333 *
1334 * Unfortunately, the system doesn't carry enough DMI
1335 * information to identify the machine but does have subsystem
1336 * vendor and device set. As it's unclear whether the
1337 * subsystem vendor/device is used only for this specific
1338 * board, the port can't be disabled solely with the
1339 * information; however, turning off SIDPR access works around
1340 * the problem. Turn it off.
1341 *
1342 * This problem is reported in bnc#441240.
1343 *
1344 * https://bugzilla.novell.com/show_bug.cgi?id=441420
1345 */
1346 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 &&
1347 pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG &&
1348 pdev->subsystem_device == 0xb049) {
1349 dev_printk(KERN_WARNING, host->dev,
1350 "Samsung DB-P70 detected, disabling SIDPR\n");
1351 return true;
1352 }
1353
1354 return false;
1355 }
1356
1357 static int __devinit piix_init_sidpr(struct ata_host *host)
1358 {
1359 struct pci_dev *pdev = to_pci_dev(host->dev);
1360 struct piix_host_priv *hpriv = host->private_data;
1361 struct ata_link *link0 = &host->ports[0]->link;
1362 u32 scontrol;
1363 int i, rc;
1364
1365 /* check for availability */
1366 for (i = 0; i < 4; i++)
1367 if (hpriv->map[i] == IDE)
1368 return 0;
1369
1370 /* is it blacklisted? */
1371 if (piix_no_sidpr(host))
1372 return 0;
1373
1374 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
1375 return 0;
1376
1377 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
1378 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
1379 return 0;
1380
1381 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
1382 return 0;
1383
1384 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
1385
1386 /* SCR access via SIDPR doesn't work on some configurations.
1387 * Give it a test drive by inhibiting power save modes which
1388 * we'll do anyway.
1389 */
1390 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1391
1392 /* if IPM is already 3, SCR access is probably working. Don't
1393 * un-inhibit power save modes as BIOS might have inhibited
1394 * them for a reason.
1395 */
1396 if ((scontrol & 0xf00) != 0x300) {
1397 scontrol |= 0x300;
1398 piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol);
1399 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1400
1401 if ((scontrol & 0xf00) != 0x300) {
1402 dev_printk(KERN_INFO, host->dev, "SCR access via "
1403 "SIDPR is available but doesn't work\n");
1404 return 0;
1405 }
1406 }
1407
1408 /* okay, SCRs available, set ops and ask libata for slave_link */
1409 for (i = 0; i < 2; i++) {
1410 struct ata_port *ap = host->ports[i];
1411
1412 ap->ops = &piix_sidpr_sata_ops;
1413
1414 if (ap->flags & ATA_FLAG_SLAVE_POSS) {
1415 rc = ata_slave_link_init(ap);
1416 if (rc)
1417 return rc;
1418 }
1419 }
1420
1421 return 0;
1422 }
1423
1424 static void piix_iocfg_bit18_quirk(struct ata_host *host)
1425 {
1426 static const struct dmi_system_id sysids[] = {
1427 {
1428 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1429 * isn't used to boot the system which
1430 * disables the channel.
1431 */
1432 .ident = "M570U",
1433 .matches = {
1434 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1435 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1436 },
1437 },
1438
1439 { } /* terminate list */
1440 };
1441 struct pci_dev *pdev = to_pci_dev(host->dev);
1442 struct piix_host_priv *hpriv = host->private_data;
1443
1444 if (!dmi_check_system(sysids))
1445 return;
1446
1447 /* The datasheet says that bit 18 is NOOP but certain systems
1448 * seem to use it to disable a channel. Clear the bit on the
1449 * affected systems.
1450 */
1451 if (hpriv->saved_iocfg & (1 << 18)) {
1452 dev_printk(KERN_INFO, &pdev->dev,
1453 "applying IOCFG bit18 quirk\n");
1454 pci_write_config_dword(pdev, PIIX_IOCFG,
1455 hpriv->saved_iocfg & ~(1 << 18));
1456 }
1457 }
1458
1459 static bool piix_broken_system_poweroff(struct pci_dev *pdev)
1460 {
1461 static const struct dmi_system_id broken_systems[] = {
1462 {
1463 .ident = "HP Compaq 2510p",
1464 .matches = {
1465 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1466 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"),
1467 },
1468 /* PCI slot number of the controller */
1469 .driver_data = (void *)0x1FUL,
1470 },
1471 {
1472 .ident = "HP Compaq nc6000",
1473 .matches = {
1474 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1475 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"),
1476 },
1477 /* PCI slot number of the controller */
1478 .driver_data = (void *)0x1FUL,
1479 },
1480
1481 { } /* terminate list */
1482 };
1483 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1484
1485 if (dmi) {
1486 unsigned long slot = (unsigned long)dmi->driver_data;
1487 /* apply the quirk only to on-board controllers */
1488 return slot == PCI_SLOT(pdev->devfn);
1489 }
1490
1491 return false;
1492 }
1493
1494 /**
1495 * piix_init_one - Register PIIX ATA PCI device with kernel services
1496 * @pdev: PCI device to register
1497 * @ent: Entry in piix_pci_tbl matching with @pdev
1498 *
1499 * Called from kernel PCI layer. We probe for combined mode (sigh),
1500 * and then hand over control to libata, for it to do the rest.
1501 *
1502 * LOCKING:
1503 * Inherited from PCI layer (may sleep).
1504 *
1505 * RETURNS:
1506 * Zero on success, or -ERRNO value.
1507 */
1508
1509 static int __devinit piix_init_one(struct pci_dev *pdev,
1510 const struct pci_device_id *ent)
1511 {
1512 static int printed_version;
1513 struct device *dev = &pdev->dev;
1514 struct ata_port_info port_info[2];
1515 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1516 unsigned long port_flags;
1517 struct ata_host *host;
1518 struct piix_host_priv *hpriv;
1519 int rc;
1520
1521 if (!printed_version++)
1522 dev_printk(KERN_DEBUG, &pdev->dev,
1523 "version " DRV_VERSION "\n");
1524
1525 /* no hotplugging support for later devices (FIXME) */
1526 if (!in_module_init && ent->driver_data >= ich5_sata)
1527 return -ENODEV;
1528
1529 if (piix_broken_system_poweroff(pdev)) {
1530 piix_port_info[ent->driver_data].flags |=
1531 ATA_FLAG_NO_POWEROFF_SPINDOWN |
1532 ATA_FLAG_NO_HIBERNATE_SPINDOWN;
1533 dev_info(&pdev->dev, "quirky BIOS, skipping spindown "
1534 "on poweroff and hibernation\n");
1535 }
1536
1537 port_info[0] = piix_port_info[ent->driver_data];
1538 port_info[1] = piix_port_info[ent->driver_data];
1539
1540 port_flags = port_info[0].flags;
1541
1542 /* enable device and prepare host */
1543 rc = pcim_enable_device(pdev);
1544 if (rc)
1545 return rc;
1546
1547 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1548 if (!hpriv)
1549 return -ENOMEM;
1550
1551 /* Save IOCFG, this will be used for cable detection, quirk
1552 * detection and restoration on detach. This is necessary
1553 * because some ACPI implementations mess up cable related
1554 * bits on _STM. Reported on kernel bz#11879.
1555 */
1556 pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg);
1557
1558 /* ICH6R may be driven by either ata_piix or ahci driver
1559 * regardless of BIOS configuration. Make sure AHCI mode is
1560 * off.
1561 */
1562 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
1563 rc = piix_disable_ahci(pdev);
1564 if (rc)
1565 return rc;
1566 }
1567
1568 /* SATA map init can change port_info, do it before prepping host */
1569 if (port_flags & ATA_FLAG_SATA)
1570 hpriv->map = piix_init_sata_map(pdev, port_info,
1571 piix_map_db_table[ent->driver_data]);
1572
1573 rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
1574 if (rc)
1575 return rc;
1576 host->private_data = hpriv;
1577
1578 /* initialize controller */
1579 if (port_flags & ATA_FLAG_SATA) {
1580 piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
1581 rc = piix_init_sidpr(host);
1582 if (rc)
1583 return rc;
1584 }
1585
1586 /* apply IOCFG bit18 quirk */
1587 piix_iocfg_bit18_quirk(host);
1588
1589 /* On ICH5, some BIOSen disable the interrupt using the
1590 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1591 * On ICH6, this bit has the same effect, but only when
1592 * MSI is disabled (and it is disabled, as we don't use
1593 * message-signalled interrupts currently).
1594 */
1595 if (port_flags & PIIX_FLAG_CHECKINTR)
1596 pci_intx(pdev, 1);
1597
1598 if (piix_check_450nx_errata(pdev)) {
1599 /* This writes into the master table but it does not
1600 really matter for this errata as we will apply it to
1601 all the PIIX devices on the board */
1602 host->ports[0]->mwdma_mask = 0;
1603 host->ports[0]->udma_mask = 0;
1604 host->ports[1]->mwdma_mask = 0;
1605 host->ports[1]->udma_mask = 0;
1606 }
1607 host->flags |= ATA_HOST_PARALLEL_SCAN;
1608
1609 pci_set_master(pdev);
1610 return ata_pci_sff_activate_host(host, ata_sff_interrupt, &piix_sht);
1611 }
1612
1613 static void piix_remove_one(struct pci_dev *pdev)
1614 {
1615 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1616 struct piix_host_priv *hpriv = host->private_data;
1617
1618 pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg);
1619
1620 ata_pci_remove_one(pdev);
1621 }
1622
1623 static int __init piix_init(void)
1624 {
1625 int rc;
1626
1627 DPRINTK("pci_register_driver\n");
1628 rc = pci_register_driver(&piix_pci_driver);
1629 if (rc)
1630 return rc;
1631
1632 in_module_init = 0;
1633
1634 DPRINTK("done\n");
1635 return 0;
1636 }
1637
1638 static void __exit piix_exit(void)
1639 {
1640 pci_unregister_driver(&piix_pci_driver);
1641 }
1642
1643 module_init(piix_init);
1644 module_exit(piix_exit);
Linux for Ginger Game Console