drivers/gpu/drm/i830/i830_drv.h

   1 /* i830_drv.h -- Private header for the I830 driver -*- linux-c -*-
   2  * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
   3  *
   4  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
   5  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
   6  * All rights reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  *
  27  * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
  28  *          Jeff Hartmann <jhartmann@valinux.com>
  29  *
  30  */
  31
  32 #ifndef _I830_DRV_H_
  33 #define _I830_DRV_H_
  34
  35 /* General customization:
  36  */
  37
  38 #define DRIVER_AUTHOR           "VA Linux Systems Inc."
  39
  40 #define DRIVER_NAME             "i830"
  41 #define DRIVER_DESC             "Intel 830M"
  42 #define DRIVER_DATE             "20021108"
  43
  44 /* Interface history:
  45  *
  46  * 1.1: Original.
  47  * 1.2: ?
  48  * 1.3: New irq emit/wait ioctls.
  49  *      New pageflip ioctl.
  50  *      New getparam ioctl.
  51  *      State for texunits 3&4 in sarea.
  52  *      New (alternative) layout for texture state.
  53  */
  54 #define DRIVER_MAJOR            1
  55 #define DRIVER_MINOR            3
  56 #define DRIVER_PATCHLEVEL       2
  57
  58 /* Driver will work either way: IRQ's save cpu time when waiting for
  59  * the card, but are subject to subtle interactions between bios,
  60  * hardware and the driver.
  61  */
  62 /* XXX: Add vblank support? */
  63 #define USE_IRQS 0
  64
  65 typedef struct drm_i830_buf_priv {
  66         u32 *in_use;
  67         int my_use_idx;
  68         int currently_mapped;
  69         void __user *virtual;
  70         void *kernel_virtual;
  71         drm_local_map_t map;
  72 } drm_i830_buf_priv_t;
  73
  74 typedef struct _drm_i830_ring_buffer {
  75         int tail_mask;
  76         unsigned long Start;
  77         unsigned long End;
  78         unsigned long Size;
  79         u8 *virtual_start;
  80         int head;
  81         int tail;
  82         int space;
  83         drm_local_map_t map;
  84 } drm_i830_ring_buffer_t;
  85
  86 typedef struct drm_i830_private {
  87         struct drm_local_map *sarea_map;
  88         struct drm_local_map *mmio_map;
  89
  90         drm_i830_sarea_t *sarea_priv;
  91         drm_i830_ring_buffer_t ring;
  92
  93         void *hw_status_page;
  94         unsigned long counter;
  95
  96         dma_addr_t dma_status_page;
  97
  98         struct drm_buf *mmap_buffer;
  99
 100         u32 front_di1, back_di1, zi1;
 101
 102         int back_offset;
 103         int depth_offset;
 104         int front_offset;
 105         int w, h;
 106         int pitch;
 107         int back_pitch;
 108         int depth_pitch;
 109         unsigned int cpp;
 110
 111         int do_boxes;
 112         int dma_used;
 113
 114         int current_page;
 115         int page_flipping;
 116
 117         wait_queue_head_t irq_queue;
 118         atomic_t irq_received;
 119         atomic_t irq_emitted;
 120
 121         int use_mi_batchbuffer_start;
 122
 123 } drm_i830_private_t;
 124
 125 extern struct drm_ioctl_desc i830_ioctls[];
 126 extern int i830_max_ioctl;
 127
 128 /* i830_irq.c */
 129 extern int i830_irq_emit(struct drm_device *dev, void *data,
 130                          struct drm_file *file_priv);
 131 extern int i830_irq_wait(struct drm_device *dev, void *data,
 132                          struct drm_file *file_priv);
 133
 134 extern irqreturn_t i830_driver_irq_handler(DRM_IRQ_ARGS);
 135 extern void i830_driver_irq_preinstall(struct drm_device * dev);
 136 extern void i830_driver_irq_postinstall(struct drm_device * dev);
 137 extern void i830_driver_irq_uninstall(struct drm_device * dev);
 138 extern int i830_driver_load(struct drm_device *, unsigned long flags);
 139 extern void i830_driver_preclose(struct drm_device * dev,
 140                                  struct drm_file *file_priv);
 141 extern void i830_driver_lastclose(struct drm_device * dev);
 142 extern void i830_driver_reclaim_buffers_locked(struct drm_device * dev,
 143                                                struct drm_file *file_priv);
 144 extern int i830_driver_dma_quiescent(struct drm_device * dev);
 145 extern int i830_driver_device_is_agp(struct drm_device * dev);
 146
 147 #define I830_READ(reg)          DRM_READ32(dev_priv->mmio_map, reg)
 148 #define I830_WRITE(reg,val)     DRM_WRITE32(dev_priv->mmio_map, reg, val)
 149 #define I830_READ16(reg)        DRM_READ16(dev_priv->mmio_map, reg)
 150 #define I830_WRITE16(reg,val)   DRM_WRITE16(dev_priv->mmio_map, reg, val)
 151
 152 #define I830_VERBOSE 0
 153
 154 #define RING_LOCALS     unsigned int outring, ringmask, outcount; \
 155                         volatile char *virt;
 156
 157 #define BEGIN_LP_RING(n) do {                           \
 158         if (I830_VERBOSE)                               \
 159                 printk("BEGIN_LP_RING(%d)\n", (n));     \
 160         if (dev_priv->ring.space < n*4)                 \
 161                 i830_wait_ring(dev, n*4, __func__);             \
 162         outcount = 0;                                   \
 163         outring = dev_priv->ring.tail;                  \
 164         ringmask = dev_priv->ring.tail_mask;            \
 165         virt = dev_priv->ring.virtual_start;            \
 166 } while (0)
 167
 168 #define OUT_RING(n) do {                                        \
 169         if (I830_VERBOSE) printk("   OUT_RING %x\n", (int)(n)); \
 170         *(volatile unsigned int *)(virt + outring) = n;         \
 171         outcount++;                                             \
 172         outring += 4;                                           \
 173         outring &= ringmask;                                    \
 174 } while (0)
 175
 176 #define ADVANCE_LP_RING() do {                                          \
 177         if (I830_VERBOSE) printk("ADVANCE_LP_RING %x\n", outring);      \
 178         dev_priv->ring.tail = outring;                                  \
 179         dev_priv->ring.space -= outcount * 4;                           \
 180         I830_WRITE(LP_RING + RING_TAIL, outring);                       \
 181 } while(0)
 182
 183 extern int i830_wait_ring(struct drm_device * dev, int n, const char *caller);
 184
 185 #define GFX_OP_USER_INTERRUPT           ((0<<29)|(2<<23))
 186 #define GFX_OP_BREAKPOINT_INTERRUPT     ((0<<29)|(1<<23))
 187 #define CMD_REPORT_HEAD                 (7<<23)
 188 #define CMD_STORE_DWORD_IDX             ((0x21<<23) | 0x1)
 189 #define CMD_OP_BATCH_BUFFER  ((0x0<<29)|(0x30<<23)|0x1)
 190
 191 #define STATE3D_LOAD_STATE_IMMEDIATE_2      ((0x3<<29)|(0x1d<<24)|(0x03<<16))
 192 #define LOAD_TEXTURE_MAP0                   (1<<11)
 193
 194 #define INST_PARSER_CLIENT   0x00000000
 195 #define INST_OP_FLUSH        0x02000000
 196 #define INST_FLUSH_MAP_CACHE 0x00000001
 197
 198 #define BB1_START_ADDR_MASK   (~0x7)
 199 #define BB1_PROTECTED         (1<<0)
 200 #define BB1_UNPROTECTED       (0<<0)
 201 #define BB2_END_ADDR_MASK     (~0x7)
 202
 203 #define I830REG_HWSTAM          0x02098
 204 #define I830REG_INT_IDENTITY_R  0x020a4
 205 #define I830REG_INT_MASK_R      0x020a8
 206 #define I830REG_INT_ENABLE_R    0x020a0
 207
 208 #define I830_IRQ_RESERVED ((1<<13)|(3<<2))
 209
 210 #define LP_RING                 0x2030
 211 #define HP_RING                 0x2040
 212 #define RING_TAIL               0x00
 213 #define TAIL_ADDR               0x001FFFF8
 214 #define RING_HEAD               0x04
 215 #define HEAD_WRAP_COUNT         0xFFE00000
 216 #define HEAD_WRAP_ONE           0x00200000
 217 #define HEAD_ADDR               0x001FFFFC
 218 #define RING_START              0x08
 219 #define START_ADDR              0x0xFFFFF000
 220 #define RING_LEN                0x0C
 221 #define RING_NR_PAGES           0x001FF000
 222 #define RING_REPORT_MASK        0x00000006
 223 #define RING_REPORT_64K         0x00000002
 224 #define RING_REPORT_128K        0x00000004
 225 #define RING_NO_REPORT          0x00000000
 226 #define RING_VALID_MASK         0x00000001
 227 #define RING_VALID              0x00000001
 228 #define RING_INVALID            0x00000000
 229
 230 #define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
 231 #define SC_UPDATE_SCISSOR       (0x1<<1)
 232 #define SC_ENABLE_MASK          (0x1<<0)
 233 #define SC_ENABLE               (0x1<<0)
 234
 235 #define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
 236 #define SCI_YMIN_MASK      (0xffff<<16)
 237 #define SCI_XMIN_MASK      (0xffff<<0)
 238 #define SCI_YMAX_MASK      (0xffff<<16)
 239 #define SCI_XMAX_MASK      (0xffff<<0)
 240
 241 #define GFX_OP_SCISSOR_ENABLE    ((0x3<<29)|(0x1c<<24)|(0x10<<19))
 242 #define GFX_OP_SCISSOR_RECT      ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
 243 #define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
 244 #define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
 245 #define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
 246 #define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
 247 #define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
 248 #define GFX_OP_PRIMITIVE         ((0x3<<29)|(0x1f<<24))
 249
 250 #define CMD_OP_DESTBUFFER_INFO   ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
 251
 252 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
 253 #define ASYNC_FLIP                (1<<22)
 254
 255 #define CMD_3D                          (0x3<<29)
 256 #define STATE3D_CONST_BLEND_COLOR_CMD   (CMD_3D|(0x1d<<24)|(0x88<<16))
 257 #define STATE3D_MAP_COORD_SETBIND_CMD   (CMD_3D|(0x1d<<24)|(0x02<<16))
 258
 259 #define BR00_BITBLT_CLIENT   0x40000000
 260 #define BR00_OP_COLOR_BLT    0x10000000
 261 #define BR00_OP_SRC_COPY_BLT 0x10C00000
 262 #define BR13_SOLID_PATTERN   0x80000000
 263
 264 #define BUF_3D_ID_COLOR_BACK    (0x3<<24)
 265 #define BUF_3D_ID_DEPTH         (0x7<<24)
 266 #define BUF_3D_USE_FENCE        (1<<23)
 267 #define BUF_3D_PITCH(x)         (((x)/4)<<2)
 268
 269 #define CMD_OP_MAP_PALETTE_LOAD ((3<<29)|(0x1d<<24)|(0x82<<16)|255)
 270 #define MAP_PALETTE_NUM(x)      ((x<<8) & (1<<8))
 271 #define MAP_PALETTE_BOTH        (1<<11)
 272
 273 #define XY_COLOR_BLT_CMD                ((2<<29)|(0x50<<22)|0x4)
 274 #define XY_COLOR_BLT_WRITE_ALPHA        (1<<21)
 275 #define XY_COLOR_BLT_WRITE_RGB          (1<<20)
 276
 277 #define XY_SRC_COPY_BLT_CMD             ((2<<29)|(0x53<<22)|6)
 278 #define XY_SRC_COPY_BLT_WRITE_ALPHA     (1<<21)
 279 #define XY_SRC_COPY_BLT_WRITE_RGB       (1<<20)
 280
 281 #define MI_BATCH_BUFFER         ((0x30<<23)|1)
 282 #define MI_BATCH_BUFFER_START   (0x31<<23)
 283 #define MI_BATCH_BUFFER_END     (0xA<<23)
 284 #define MI_BATCH_NON_SECURE     (1)
 285
 286 #define MI_WAIT_FOR_EVENT       ((0x3<<23))
 287 #define MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)
 288 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
 289
 290 #define MI_LOAD_SCAN_LINES_INCL  ((0x12<<23))
 291
 292 #endif