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Full support for Ginger Console
[linux-ginger.git] / drivers / gpu / drm / i915 / i915_drv.h
blob6035d3dae851c498147fda561f35fe92d8369c74
1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #ifndef _I915_DRV_H_
31 #define _I915_DRV_H_
32
33 #include "i915_reg.h"
34 #include "intel_bios.h"
35 #include <linux/io-mapping.h>
36
37 /* General customization:
38 */
39
40 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
41
42 #define DRIVER_NAME "i915"
43 #define DRIVER_DESC "Intel Graphics"
44 #define DRIVER_DATE "20080730"
45
46 enum pipe {
47 PIPE_A = 0,
48 PIPE_B,
49 };
50
51 enum plane {
52 PLANE_A = 0,
53 PLANE_B,
54 };
55
56 #define I915_NUM_PIPE 2
57
58 /* Interface history:
59 *
60 * 1.1: Original.
61 * 1.2: Add Power Management
62 * 1.3: Add vblank support
63 * 1.4: Fix cmdbuffer path, add heap destroy
64 * 1.5: Add vblank pipe configuration
65 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
66 * - Support vertical blank on secondary display pipe
67 */
68 #define DRIVER_MAJOR 1
69 #define DRIVER_MINOR 6
70 #define DRIVER_PATCHLEVEL 0
71
72 #define WATCH_COHERENCY 0
73 #define WATCH_BUF 0
74 #define WATCH_EXEC 0
75 #define WATCH_LRU 0
76 #define WATCH_RELOC 0
77 #define WATCH_INACTIVE 0
78 #define WATCH_PWRITE 0
79
80 #define I915_GEM_PHYS_CURSOR_0 1
81 #define I915_GEM_PHYS_CURSOR_1 2
82 #define I915_GEM_PHYS_OVERLAY_REGS 3
83 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
84
85 struct drm_i915_gem_phys_object {
86 int id;
87 struct page **page_list;
88 drm_dma_handle_t *handle;
89 struct drm_gem_object *cur_obj;
90 };
91
92 typedef struct _drm_i915_ring_buffer {
93 unsigned long Size;
94 u8 *virtual_start;
95 int head;
96 int tail;
97 int space;
98 drm_local_map_t map;
99 struct drm_gem_object *ring_obj;
100 } drm_i915_ring_buffer_t;
101
102 struct mem_block {
103 struct mem_block *next;
104 struct mem_block *prev;
105 int start;
106 int size;
107 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
108 };
109
110 struct opregion_header;
111 struct opregion_acpi;
112 struct opregion_swsci;
113 struct opregion_asle;
114
115 struct intel_opregion {
116 struct opregion_header *header;
117 struct opregion_acpi *acpi;
118 struct opregion_swsci *swsci;
119 struct opregion_asle *asle;
120 int enabled;
121 };
122
123 struct drm_i915_master_private {
124 drm_local_map_t *sarea;
125 struct _drm_i915_sarea *sarea_priv;
126 };
127 #define I915_FENCE_REG_NONE -1
128
129 struct drm_i915_fence_reg {
130 struct drm_gem_object *obj;
131 };
132
133 struct sdvo_device_mapping {
134 u8 dvo_port;
135 u8 slave_addr;
136 u8 dvo_wiring;
137 u8 initialized;
138 };
139
140 struct drm_i915_error_state {
141 u32 eir;
142 u32 pgtbl_er;
143 u32 pipeastat;
144 u32 pipebstat;
145 u32 ipeir;
146 u32 ipehr;
147 u32 instdone;
148 u32 acthd;
149 u32 instpm;
150 u32 instps;
151 u32 instdone1;
152 u32 seqno;
153 struct timeval time;
154 };
155
156 struct drm_i915_display_funcs {
157 void (*dpms)(struct drm_crtc *crtc, int mode);
158 bool (*fbc_enabled)(struct drm_crtc *crtc);
159 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
160 void (*disable_fbc)(struct drm_device *dev);
161 int (*get_display_clock_speed)(struct drm_device *dev);
162 int (*get_fifo_size)(struct drm_device *dev, int plane);
163 void (*update_wm)(struct drm_device *dev, int planea_clock,
164 int planeb_clock, int sr_hdisplay, int pixel_size);
165 /* clock updates for mode set */
166 /* cursor updates */
167 /* render clock increase/decrease */
168 /* display clock increase/decrease */
169 /* pll clock increase/decrease */
170 /* clock gating init */
171 };
172
173 typedef struct drm_i915_private {
174 struct drm_device *dev;
175
176 int has_gem;
177
178 void __iomem *regs;
179
180 struct pci_dev *bridge_dev;
181 drm_i915_ring_buffer_t ring;
182
183 drm_dma_handle_t *status_page_dmah;
184 void *hw_status_page;
185 dma_addr_t dma_status_page;
186 uint32_t counter;
187 unsigned int status_gfx_addr;
188 drm_local_map_t hws_map;
189 struct drm_gem_object *hws_obj;
190
191 struct resource mch_res;
192
193 unsigned int cpp;
194 int back_offset;
195 int front_offset;
196 int current_page;
197 int page_flipping;
198
199 wait_queue_head_t irq_queue;
200 atomic_t irq_received;
201 /** Protects user_irq_refcount and irq_mask_reg */
202 spinlock_t user_irq_lock;
203 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
204 int user_irq_refcount;
205 u32 trace_irq_seqno;
206 /** Cached value of IMR to avoid reads in updating the bitfield */
207 u32 irq_mask_reg;
208 u32 pipestat[2];
209 /** splitted irq regs for graphics and display engine on IGDNG,
210 irq_mask_reg is still used for display irq. */
211 u32 gt_irq_mask_reg;
212 u32 gt_irq_enable_reg;
213 u32 de_irq_enable_reg;
214
215 u32 hotplug_supported_mask;
216 struct work_struct hotplug_work;
217
218 int tex_lru_log_granularity;
219 int allow_batchbuffer;
220 struct mem_block *agp_heap;
221 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
222 int vblank_pipe;
223
224 /* For hangcheck timer */
225 #define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */
226 struct timer_list hangcheck_timer;
227 int hangcheck_count;
228 uint32_t last_acthd;
229
230 bool cursor_needs_physical;
231
232 struct drm_mm vram;
233
234 unsigned long cfb_size;
235 unsigned long cfb_pitch;
236 int cfb_fence;
237 int cfb_plane;
238
239 int irq_enabled;
240
241 struct intel_opregion opregion;
242
243 /* LVDS info */
244 int backlight_duty_cycle; /* restore backlight to this value */
245 bool panel_wants_dither;
246 struct drm_display_mode *panel_fixed_mode;
247 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
248 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
249
250 /* Feature bits from the VBIOS */
251 unsigned int int_tv_support:1;
252 unsigned int lvds_dither:1;
253 unsigned int lvds_vbt:1;
254 unsigned int int_crt_support:1;
255 unsigned int lvds_use_ssc:1;
256 unsigned int edp_support:1;
257 int lvds_ssc_freq;
258
259 struct notifier_block lid_notifier;
260
261 int crt_ddc_bus; /* -1 = unknown, else GPIO to use for CRT DDC */
262 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
263 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
264 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
265
266 unsigned int fsb_freq, mem_freq;
267
268 spinlock_t error_lock;
269 struct drm_i915_error_state *first_error;
270 struct work_struct error_work;
271 struct workqueue_struct *wq;
272
273 /* Display functions */
274 struct drm_i915_display_funcs display;
275
276 /* Register state */
277 bool suspended;
278 u8 saveLBB;
279 u32 saveDSPACNTR;
280 u32 saveDSPBCNTR;
281 u32 saveDSPARB;
282 u32 saveRENDERSTANDBY;
283 u32 saveHWS;
284 u32 savePIPEACONF;
285 u32 savePIPEBCONF;
286 u32 savePIPEASRC;
287 u32 savePIPEBSRC;
288 u32 saveFPA0;
289 u32 saveFPA1;
290 u32 saveDPLL_A;
291 u32 saveDPLL_A_MD;
292 u32 saveHTOTAL_A;
293 u32 saveHBLANK_A;
294 u32 saveHSYNC_A;
295 u32 saveVTOTAL_A;
296 u32 saveVBLANK_A;
297 u32 saveVSYNC_A;
298 u32 saveBCLRPAT_A;
299 u32 savePIPEASTAT;
300 u32 saveDSPASTRIDE;
301 u32 saveDSPASIZE;
302 u32 saveDSPAPOS;
303 u32 saveDSPAADDR;
304 u32 saveDSPASURF;
305 u32 saveDSPATILEOFF;
306 u32 savePFIT_PGM_RATIOS;
307 u32 saveBLC_PWM_CTL;
308 u32 saveBLC_PWM_CTL2;
309 u32 saveFPB0;
310 u32 saveFPB1;
311 u32 saveDPLL_B;
312 u32 saveDPLL_B_MD;
313 u32 saveHTOTAL_B;
314 u32 saveHBLANK_B;
315 u32 saveHSYNC_B;
316 u32 saveVTOTAL_B;
317 u32 saveVBLANK_B;
318 u32 saveVSYNC_B;
319 u32 saveBCLRPAT_B;
320 u32 savePIPEBSTAT;
321 u32 saveDSPBSTRIDE;
322 u32 saveDSPBSIZE;
323 u32 saveDSPBPOS;
324 u32 saveDSPBADDR;
325 u32 saveDSPBSURF;
326 u32 saveDSPBTILEOFF;
327 u32 saveVGA0;
328 u32 saveVGA1;
329 u32 saveVGA_PD;
330 u32 saveVGACNTRL;
331 u32 saveADPA;
332 u32 saveLVDS;
333 u32 savePP_ON_DELAYS;
334 u32 savePP_OFF_DELAYS;
335 u32 saveDVOA;
336 u32 saveDVOB;
337 u32 saveDVOC;
338 u32 savePP_ON;
339 u32 savePP_OFF;
340 u32 savePP_CONTROL;
341 u32 savePP_DIVISOR;
342 u32 savePFIT_CONTROL;
343 u32 save_palette_a[256];
344 u32 save_palette_b[256];
345 u32 saveFBC_CFB_BASE;
346 u32 saveFBC_LL_BASE;
347 u32 saveFBC_CONTROL;
348 u32 saveFBC_CONTROL2;
349 u32 saveIER;
350 u32 saveIIR;
351 u32 saveIMR;
352 u32 saveCACHE_MODE_0;
353 u32 saveD_STATE;
354 u32 saveDSPCLK_GATE_D;
355 u32 saveMI_ARB_STATE;
356 u32 saveSWF0[16];
357 u32 saveSWF1[16];
358 u32 saveSWF2[3];
359 u8 saveMSR;
360 u8 saveSR[8];
361 u8 saveGR[25];
362 u8 saveAR_INDEX;
363 u8 saveAR[21];
364 u8 saveDACMASK;
365 u8 saveCR[37];
366 uint64_t saveFENCE[16];
367 u32 saveCURACNTR;
368 u32 saveCURAPOS;
369 u32 saveCURABASE;
370 u32 saveCURBCNTR;
371 u32 saveCURBPOS;
372 u32 saveCURBBASE;
373 u32 saveCURSIZE;
374 u32 saveDP_B;
375 u32 saveDP_C;
376 u32 saveDP_D;
377 u32 savePIPEA_GMCH_DATA_M;
378 u32 savePIPEB_GMCH_DATA_M;
379 u32 savePIPEA_GMCH_DATA_N;
380 u32 savePIPEB_GMCH_DATA_N;
381 u32 savePIPEA_DP_LINK_M;
382 u32 savePIPEB_DP_LINK_M;
383 u32 savePIPEA_DP_LINK_N;
384 u32 savePIPEB_DP_LINK_N;
385
386 struct {
387 struct drm_mm gtt_space;
388
389 struct io_mapping *gtt_mapping;
390 int gtt_mtrr;
391
392 /**
393 * Membership on list of all loaded devices, used to evict
394 * inactive buffers under memory pressure.
395 *
396 * Modifications should only be done whilst holding the
397 * shrink_list_lock spinlock.
398 */
399 struct list_head shrink_list;
400
401 /**
402 * List of objects currently involved in rendering from the
403 * ringbuffer.
404 *
405 * Includes buffers having the contents of their GPU caches
406 * flushed, not necessarily primitives. last_rendering_seqno
407 * represents when the rendering involved will be completed.
408 *
409 * A reference is held on the buffer while on this list.
410 */
411 spinlock_t active_list_lock;
412 struct list_head active_list;
413
414 /**
415 * List of objects which are not in the ringbuffer but which
416 * still have a write_domain which needs to be flushed before
417 * unbinding.
418 *
419 * last_rendering_seqno is 0 while an object is in this list.
420 *
421 * A reference is held on the buffer while on this list.
422 */
423 struct list_head flushing_list;
424
425 /**
426 * LRU list of objects which are not in the ringbuffer and
427 * are ready to unbind, but are still in the GTT.
428 *
429 * last_rendering_seqno is 0 while an object is in this list.
430 *
431 * A reference is not held on the buffer while on this list,
432 * as merely being GTT-bound shouldn't prevent its being
433 * freed, and we'll pull it off the list in the free path.
434 */
435 struct list_head inactive_list;
436
437 /** LRU list of objects with fence regs on them. */
438 struct list_head fence_list;
439
440 /**
441 * List of breadcrumbs associated with GPU requests currently
442 * outstanding.
443 */
444 struct list_head request_list;
445
446 /**
447 * We leave the user IRQ off as much as possible,
448 * but this means that requests will finish and never
449 * be retired once the system goes idle. Set a timer to
450 * fire periodically while the ring is running. When it
451 * fires, go retire requests.
452 */
453 struct delayed_work retire_work;
454
455 uint32_t next_gem_seqno;
456
457 /**
458 * Waiting sequence number, if any
459 */
460 uint32_t waiting_gem_seqno;
461
462 /**
463 * Last seq seen at irq time
464 */
465 uint32_t irq_gem_seqno;
466
467 /**
468 * Flag if the X Server, and thus DRM, is not currently in
469 * control of the device.
470 *
471 * This is set between LeaveVT and EnterVT. It needs to be
472 * replaced with a semaphore. It also needs to be
473 * transitioned away from for kernel modesetting.
474 */
475 int suspended;
476
477 /**
478 * Flag if the hardware appears to be wedged.
479 *
480 * This is set when attempts to idle the device timeout.
481 * It prevents command submission from occuring and makes
482 * every pending request fail
483 */
484 atomic_t wedged;
485
486 /** Bit 6 swizzling required for X tiling */
487 uint32_t bit_6_swizzle_x;
488 /** Bit 6 swizzling required for Y tiling */
489 uint32_t bit_6_swizzle_y;
490
491 /* storage for physical objects */
492 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
493 } mm;
494 struct sdvo_device_mapping sdvo_mappings[2];
495
496 /* Reclocking support */
497 bool render_reclock_avail;
498 bool lvds_downclock_avail;
499 struct work_struct idle_work;
500 struct timer_list idle_timer;
501 bool busy;
502 u16 orig_clock;
503 } drm_i915_private_t;
504
505 /** driver private structure attached to each drm_gem_object */
506 struct drm_i915_gem_object {
507 struct drm_gem_object *obj;
508
509 /** Current space allocated to this object in the GTT, if any. */
510 struct drm_mm_node *gtt_space;
511
512 /** This object's place on the active/flushing/inactive lists */
513 struct list_head list;
514
515 /** This object's place on the fenced object LRU */
516 struct list_head fence_list;
517
518 /**
519 * This is set if the object is on the active or flushing lists
520 * (has pending rendering), and is not set if it's on inactive (ready
521 * to be unbound).
522 */
523 int active;
524
525 /**
526 * This is set if the object has been written to since last bound
527 * to the GTT
528 */
529 int dirty;
530
531 /** AGP memory structure for our GTT binding. */
532 DRM_AGP_MEM *agp_mem;
533
534 struct page **pages;
535 int pages_refcount;
536
537 /**
538 * Current offset of the object in GTT space.
539 *
540 * This is the same as gtt_space->start
541 */
542 uint32_t gtt_offset;
543
544 /**
545 * Fake offset for use by mmap(2)
546 */
547 uint64_t mmap_offset;
548
549 /**
550 * Fence register bits (if any) for this object. Will be set
551 * as needed when mapped into the GTT.
552 * Protected by dev->struct_mutex.
553 */
554 int fence_reg;
555
556 /** How many users have pinned this object in GTT space */
557 int pin_count;
558
559 /** Breadcrumb of last rendering to the buffer. */
560 uint32_t last_rendering_seqno;
561
562 /** Current tiling mode for the object. */
563 uint32_t tiling_mode;
564 uint32_t stride;
565
566 /** Record of address bit 17 of each page at last unbind. */
567 long *bit_17;
568
569 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
570 uint32_t agp_type;
571
572 /**
573 * If present, while GEM_DOMAIN_CPU is in the read domain this array
574 * flags which individual pages are valid.
575 */
576 uint8_t *page_cpu_valid;
577
578 /** User space pin count and filp owning the pin */
579 uint32_t user_pin_count;
580 struct drm_file *pin_filp;
581
582 /** for phy allocated objects */
583 struct drm_i915_gem_phys_object *phys_obj;
584
585 /**
586 * Used for checking the object doesn't appear more than once
587 * in an execbuffer object list.
588 */
589 int in_execbuffer;
590
591 /**
592 * Advice: are the backing pages purgeable?
593 */
594 int madv;
595 };
596
597 /**
598 * Request queue structure.
599 *
600 * The request queue allows us to note sequence numbers that have been emitted
601 * and may be associated with active buffers to be retired.
602 *
603 * By keeping this list, we can avoid having to do questionable
604 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
605 * an emission time with seqnos for tracking how far ahead of the GPU we are.
606 */
607 struct drm_i915_gem_request {
608 /** GEM sequence number associated with this request. */
609 uint32_t seqno;
610
611 /** Time at which this request was emitted, in jiffies. */
612 unsigned long emitted_jiffies;
613
614 /** global list entry for this request */
615 struct list_head list;
616
617 /** file_priv list entry for this request */
618 struct list_head client_list;
619 };
620
621 struct drm_i915_file_private {
622 struct {
623 struct list_head request_list;
624 } mm;
625 };
626
627 enum intel_chip_family {
628 CHIP_I8XX = 0x01,
629 CHIP_I9XX = 0x02,
630 CHIP_I915 = 0x04,
631 CHIP_I965 = 0x08,
632 };
633
634 extern struct drm_ioctl_desc i915_ioctls[];
635 extern int i915_max_ioctl;
636 extern unsigned int i915_fbpercrtc;
637 extern unsigned int i915_powersave;
638
639 extern void i915_save_display(struct drm_device *dev);
640 extern void i915_restore_display(struct drm_device *dev);
641 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
642 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
643
644 /* i915_dma.c */
645 extern void i915_kernel_lost_context(struct drm_device * dev);
646 extern int i915_driver_load(struct drm_device *, unsigned long flags);
647 extern int i915_driver_unload(struct drm_device *);
648 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
649 extern void i915_driver_lastclose(struct drm_device * dev);
650 extern void i915_driver_preclose(struct drm_device *dev,
651 struct drm_file *file_priv);
652 extern void i915_driver_postclose(struct drm_device *dev,
653 struct drm_file *file_priv);
654 extern int i915_driver_device_is_agp(struct drm_device * dev);
655 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
656 unsigned long arg);
657 extern int i915_emit_box(struct drm_device *dev,
658 struct drm_clip_rect *boxes,
659 int i, int DR1, int DR4);
660 extern int i965_reset(struct drm_device *dev, u8 flags);
661
662 /* i915_irq.c */
663 void i915_hangcheck_elapsed(unsigned long data);
664 extern int i915_irq_emit(struct drm_device *dev, void *data,
665 struct drm_file *file_priv);
666 extern int i915_irq_wait(struct drm_device *dev, void *data,
667 struct drm_file *file_priv);
668 void i915_user_irq_get(struct drm_device *dev);
669 void i915_trace_irq_get(struct drm_device *dev, u32 seqno);
670 void i915_user_irq_put(struct drm_device *dev);
671 extern void i915_enable_interrupt (struct drm_device *dev);
672
673 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
674 extern void i915_driver_irq_preinstall(struct drm_device * dev);
675 extern int i915_driver_irq_postinstall(struct drm_device *dev);
676 extern void i915_driver_irq_uninstall(struct drm_device * dev);
677 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
678 struct drm_file *file_priv);
679 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
680 struct drm_file *file_priv);
681 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
682 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
683 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
684 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
685 extern int i915_vblank_swap(struct drm_device *dev, void *data,
686 struct drm_file *file_priv);
687 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
688
689 void
690 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
691
692 void
693 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
694
695
696 /* i915_mem.c */
697 extern int i915_mem_alloc(struct drm_device *dev, void *data,
698 struct drm_file *file_priv);
699 extern int i915_mem_free(struct drm_device *dev, void *data,
700 struct drm_file *file_priv);
701 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
702 struct drm_file *file_priv);
703 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
704 struct drm_file *file_priv);
705 extern void i915_mem_takedown(struct mem_block **heap);
706 extern void i915_mem_release(struct drm_device * dev,
707 struct drm_file *file_priv, struct mem_block *heap);
708 /* i915_gem.c */
709 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
710 struct drm_file *file_priv);
711 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
712 struct drm_file *file_priv);
713 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
714 struct drm_file *file_priv);
715 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
716 struct drm_file *file_priv);
717 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
718 struct drm_file *file_priv);
719 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
720 struct drm_file *file_priv);
721 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
722 struct drm_file *file_priv);
723 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
724 struct drm_file *file_priv);
725 int i915_gem_execbuffer(struct drm_device *dev, void *data,
726 struct drm_file *file_priv);
727 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
728 struct drm_file *file_priv);
729 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
730 struct drm_file *file_priv);
731 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
732 struct drm_file *file_priv);
733 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
734 struct drm_file *file_priv);
735 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
736 struct drm_file *file_priv);
737 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
738 struct drm_file *file_priv);
739 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
740 struct drm_file *file_priv);
741 int i915_gem_set_tiling(struct drm_device *dev, void *data,
742 struct drm_file *file_priv);
743 int i915_gem_get_tiling(struct drm_device *dev, void *data,
744 struct drm_file *file_priv);
745 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
746 struct drm_file *file_priv);
747 void i915_gem_load(struct drm_device *dev);
748 int i915_gem_init_object(struct drm_gem_object *obj);
749 void i915_gem_free_object(struct drm_gem_object *obj);
750 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
751 void i915_gem_object_unpin(struct drm_gem_object *obj);
752 int i915_gem_object_unbind(struct drm_gem_object *obj);
753 void i915_gem_release_mmap(struct drm_gem_object *obj);
754 void i915_gem_lastclose(struct drm_device *dev);
755 uint32_t i915_get_gem_seqno(struct drm_device *dev);
756 bool i915_seqno_passed(uint32_t seq1, uint32_t seq2);
757 int i915_gem_object_get_fence_reg(struct drm_gem_object *obj);
758 int i915_gem_object_put_fence_reg(struct drm_gem_object *obj);
759 void i915_gem_retire_requests(struct drm_device *dev);
760 void i915_gem_retire_work_handler(struct work_struct *work);
761 void i915_gem_clflush_object(struct drm_gem_object *obj);
762 int i915_gem_object_set_domain(struct drm_gem_object *obj,
763 uint32_t read_domains,
764 uint32_t write_domain);
765 int i915_gem_init_ringbuffer(struct drm_device *dev);
766 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
767 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
768 unsigned long end);
769 int i915_gem_idle(struct drm_device *dev);
770 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
771 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
772 int write);
773 int i915_gem_attach_phys_object(struct drm_device *dev,
774 struct drm_gem_object *obj, int id);
775 void i915_gem_detach_phys_object(struct drm_device *dev,
776 struct drm_gem_object *obj);
777 void i915_gem_free_all_phys_object(struct drm_device *dev);
778 int i915_gem_object_get_pages(struct drm_gem_object *obj);
779 void i915_gem_object_put_pages(struct drm_gem_object *obj);
780 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
781
782 void i915_gem_shrinker_init(void);
783 void i915_gem_shrinker_exit(void);
784
785 /* i915_gem_tiling.c */
786 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
787 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
788 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
789
790 /* i915_gem_debug.c */
791 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
792 const char *where, uint32_t mark);
793 #if WATCH_INACTIVE
794 void i915_verify_inactive(struct drm_device *dev, char *file, int line);
795 #else
796 #define i915_verify_inactive(dev, file, line)
797 #endif
798 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
799 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
800 const char *where, uint32_t mark);
801 void i915_dump_lru(struct drm_device *dev, const char *where);
802
803 /* i915_debugfs.c */
804 int i915_debugfs_init(struct drm_minor *minor);
805 void i915_debugfs_cleanup(struct drm_minor *minor);
806
807 /* i915_suspend.c */
808 extern int i915_save_state(struct drm_device *dev);
809 extern int i915_restore_state(struct drm_device *dev);
810
811 /* i915_suspend.c */
812 extern int i915_save_state(struct drm_device *dev);
813 extern int i915_restore_state(struct drm_device *dev);
814
815 #ifdef CONFIG_ACPI
816 /* i915_opregion.c */
817 extern int intel_opregion_init(struct drm_device *dev, int resume);
818 extern void intel_opregion_free(struct drm_device *dev, int suspend);
819 extern void opregion_asle_intr(struct drm_device *dev);
820 extern void opregion_enable_asle(struct drm_device *dev);
821 #else
822 static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; }
823 static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; }
824 static inline void opregion_asle_intr(struct drm_device *dev) { return; }
825 static inline void opregion_enable_asle(struct drm_device *dev) { return; }
826 #endif
827
828 /* modesetting */
829 extern void intel_modeset_init(struct drm_device *dev);
830 extern void intel_modeset_cleanup(struct drm_device *dev);
831 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
832 extern void i8xx_disable_fbc(struct drm_device *dev);
833 extern void g4x_disable_fbc(struct drm_device *dev);
834
835 /**
836 * Lock test for when it's just for synchronization of ring access.
837 *
838 * In that case, we don't need to do it when GEM is initialized as nobody else
839 * has access to the ring.
840 */
841 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
842 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
843 LOCK_TEST_WITH_RETURN(dev, file_priv); \
844 } while (0)
845
846 #define I915_READ(reg) readl(dev_priv->regs + (reg))
847 #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
848 #define I915_READ16(reg) readw(dev_priv->regs + (reg))
849 #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
850 #define I915_READ8(reg) readb(dev_priv->regs + (reg))
851 #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
852 #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
853 #define I915_READ64(reg) readq(dev_priv->regs + (reg))
854 #define POSTING_READ(reg) (void)I915_READ(reg)
855
856 #define I915_VERBOSE 0
857
858 #define RING_LOCALS volatile unsigned int *ring_virt__;
859
860 #define BEGIN_LP_RING(n) do { \
861 int bytes__ = 4*(n); \
862 if (I915_VERBOSE) DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
863 /* a wrap must occur between instructions so pad beforehand */ \
864 if (unlikely (dev_priv->ring.tail + bytes__ > dev_priv->ring.Size)) \
865 i915_wrap_ring(dev); \
866 if (unlikely (dev_priv->ring.space < bytes__)) \
867 i915_wait_ring(dev, bytes__, __func__); \
868 ring_virt__ = (unsigned int *) \
869 (dev_priv->ring.virtual_start + dev_priv->ring.tail); \
870 dev_priv->ring.tail += bytes__; \
871 dev_priv->ring.tail &= dev_priv->ring.Size - 1; \
872 dev_priv->ring.space -= bytes__; \
873 } while (0)
874
875 #define OUT_RING(n) do { \
876 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
877 *ring_virt__++ = (n); \
878 } while (0)
879
880 #define ADVANCE_LP_RING() do { \
881 if (I915_VERBOSE) \
882 DRM_DEBUG("ADVANCE_LP_RING %x\n", dev_priv->ring.tail); \
883 I915_WRITE(PRB0_TAIL, dev_priv->ring.tail); \
884 } while(0)
885
886 /**
887 * Reads a dword out of the status page, which is written to from the command
888 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
889 * MI_STORE_DATA_IMM.
890 *
891 * The following dwords have a reserved meaning:
892 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
893 * 0x04: ring 0 head pointer
894 * 0x05: ring 1 head pointer (915-class)
895 * 0x06: ring 2 head pointer (915-class)
896 * 0x10-0x1b: Context status DWords (GM45)
897 * 0x1f: Last written status offset. (GM45)
898 *
899 * The area from dword 0x20 to 0x3ff is available for driver usage.
900 */
901 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
902 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
903 #define I915_GEM_HWS_INDEX 0x20
904 #define I915_BREADCRUMB_INDEX 0x21
905
906 extern int i915_wrap_ring(struct drm_device * dev);
907 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
908
909 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
910 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
911 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
912 #define IS_I855(dev) ((dev)->pci_device == 0x3582)
913 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
914
915 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
916 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
917 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
918 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
919 (dev)->pci_device == 0x27AE)
920 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
921 (dev)->pci_device == 0x2982 || \
922 (dev)->pci_device == 0x2992 || \
923 (dev)->pci_device == 0x29A2 || \
924 (dev)->pci_device == 0x2A02 || \
925 (dev)->pci_device == 0x2A12 || \
926 (dev)->pci_device == 0x2A42 || \
927 (dev)->pci_device == 0x2E02 || \
928 (dev)->pci_device == 0x2E12 || \
929 (dev)->pci_device == 0x2E22 || \
930 (dev)->pci_device == 0x2E32 || \
931 (dev)->pci_device == 0x2E42 || \
932 (dev)->pci_device == 0x0042 || \
933 (dev)->pci_device == 0x0046)
934
935 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \
936 (dev)->pci_device == 0x2A12)
937
938 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
939
940 #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
941 (dev)->pci_device == 0x2E12 || \
942 (dev)->pci_device == 0x2E22 || \
943 (dev)->pci_device == 0x2E32 || \
944 (dev)->pci_device == 0x2E42 || \
945 IS_GM45(dev))
946
947 #define IS_IGDG(dev) ((dev)->pci_device == 0xa001)
948 #define IS_IGDGM(dev) ((dev)->pci_device == 0xa011)
949 #define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev))
950
951 #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
952 (dev)->pci_device == 0x29B2 || \
953 (dev)->pci_device == 0x29D2 || \
954 (IS_IGD(dev)))
955
956 #define IS_IGDNG_D(dev) ((dev)->pci_device == 0x0042)
957 #define IS_IGDNG_M(dev) ((dev)->pci_device == 0x0046)
958 #define IS_IGDNG(dev) (IS_IGDNG_D(dev) || IS_IGDNG_M(dev))
959
960 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
961 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev) || \
962 IS_IGDNG(dev))
963
964 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
965 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
966 IS_IGD(dev) || IS_IGDNG_M(dev))
967
968 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev) || \
969 IS_IGDNG(dev))
970 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
971 * rows, which changed the alignment requirements and fence programming.
972 */
973 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
974 IS_I915GM(dev)))
975 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IGDNG(dev))
976 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IGDNG(dev))
977 #define SUPPORTS_EDP(dev) (IS_IGDNG_M(dev))
978 #define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev) || IS_I965G(dev))
979 /* dsparb controlled by hw only */
980 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IGDNG(dev))
981
982 #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IGDNG(dev))
983 #define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IGDNG(dev))
984 #define I915_HAS_FBC(dev) (IS_MOBILE(dev) && (IS_I9XX(dev) || IS_I965G(dev)))
985
986 #define PRIMARY_RINGBUFFER_SIZE (128*1024)
987
988 #endif
Linux for Ginger Game Console