drivers/gpu/drm/i915/intel_bios.h

   1 /*
   2  * Copyright © 2006 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #ifndef _I830_BIOS_H_
  29 #define _I830_BIOS_H_
  30
  31 #include "drmP.h"
  32
  33 struct vbt_header {
  34         u8 signature[20];               /**< Always starts with 'VBT$' */
  35         u16 version;                    /**< decimal */
  36         u16 header_size;                /**< in bytes */
  37         u16 vbt_size;                   /**< in bytes */
  38         u8 vbt_checksum;
  39         u8 reserved0;
  40         u32 bdb_offset;                 /**< from beginning of VBT */
  41         u32 aim_offset[4];              /**< from beginning of VBT */
  42 } __attribute__((packed));
  43
  44 struct bdb_header {
  45         u8 signature[16];               /**< Always 'BIOS_DATA_BLOCK' */
  46         u16 version;                    /**< decimal */
  47         u16 header_size;                /**< in bytes */
  48         u16 bdb_size;                   /**< in bytes */
  49 };
  50
  51 /* strictly speaking, this is a "skip" block, but it has interesting info */
  52 struct vbios_data {
  53         u8 type; /* 0 == desktop, 1 == mobile */
  54         u8 relstage;
  55         u8 chipset;
  56         u8 lvds_present:1;
  57         u8 tv_present:1;
  58         u8 rsvd2:6; /* finish byte */
  59         u8 rsvd3[4];
  60         u8 signon[155];
  61         u8 copyright[61];
  62         u16 code_segment;
  63         u8 dos_boot_mode;
  64         u8 bandwidth_percent;
  65         u8 rsvd4; /* popup memory size */
  66         u8 resize_pci_bios;
  67         u8 rsvd5; /* is crt already on ddc2 */
  68 } __attribute__((packed));
  69
  70 /*
  71  * There are several types of BIOS data blocks (BDBs), each block has
  72  * an ID and size in the first 3 bytes (ID in first, size in next 2).
  73  * Known types are listed below.
  74  */
  75 #define BDB_GENERAL_FEATURES      1
  76 #define BDB_GENERAL_DEFINITIONS   2
  77 #define BDB_OLD_TOGGLE_LIST       3
  78 #define BDB_MODE_SUPPORT_LIST     4
  79 #define BDB_GENERIC_MODE_TABLE    5
  80 #define BDB_EXT_MMIO_REGS         6
  81 #define BDB_SWF_IO                7
  82 #define BDB_SWF_MMIO              8
  83 #define BDB_DOT_CLOCK_TABLE       9
  84 #define BDB_MODE_REMOVAL_TABLE   10
  85 #define BDB_CHILD_DEVICE_TABLE   11
  86 #define BDB_DRIVER_FEATURES      12
  87 #define BDB_DRIVER_PERSISTENCE   13
  88 #define BDB_EXT_TABLE_PTRS       14
  89 #define BDB_DOT_CLOCK_OVERRIDE   15
  90 #define BDB_DISPLAY_SELECT       16
  91 /* 17 rsvd */
  92 #define BDB_DRIVER_ROTATION      18
  93 #define BDB_DISPLAY_REMOVE       19
  94 #define BDB_OEM_CUSTOM           20
  95 #define BDB_EFP_LIST             21 /* workarounds for VGA hsync/vsync */
  96 #define BDB_SDVO_LVDS_OPTIONS    22
  97 #define BDB_SDVO_PANEL_DTDS      23
  98 #define BDB_SDVO_LVDS_PNP_IDS    24
  99 #define BDB_SDVO_LVDS_POWER_SEQ  25
 100 #define BDB_TV_OPTIONS           26
 101 #define BDB_LVDS_OPTIONS         40
 102 #define BDB_LVDS_LFP_DATA_PTRS   41
 103 #define BDB_LVDS_LFP_DATA        42
 104 #define BDB_LVDS_BACKLIGHT       43
 105 #define BDB_LVDS_POWER           44
 106 #define BDB_SKIP                254 /* VBIOS private block, ignore */
 107
 108 struct bdb_general_features {
 109         /* bits 1 */
 110         u8 panel_fitting:2;
 111         u8 flexaim:1;
 112         u8 msg_enable:1;
 113         u8 clear_screen:3;
 114         u8 color_flip:1;
 115
 116         /* bits 2 */
 117         u8 download_ext_vbt:1;
 118         u8 enable_ssc:1;
 119         u8 ssc_freq:1;
 120         u8 enable_lfp_on_override:1;
 121         u8 disable_ssc_ddt:1;
 122         u8 rsvd8:3; /* finish byte */
 123
 124         /* bits 3 */
 125         u8 disable_smooth_vision:1;
 126         u8 single_dvi:1;
 127         u8 rsvd9:6; /* finish byte */
 128
 129         /* bits 4 */
 130         u8 legacy_monitor_detect;
 131
 132         /* bits 5 */
 133         u8 int_crt_support:1;
 134         u8 int_tv_support:1;
 135         u8 rsvd11:6; /* finish byte */
 136 } __attribute__((packed));
 137
 138 /* pre-915 */
 139 #define GPIO_PIN_DVI_LVDS       0x03 /* "DVI/LVDS DDC GPIO pins" */
 140 #define GPIO_PIN_ADD_I2C        0x05 /* "ADDCARD I2C GPIO pins" */
 141 #define GPIO_PIN_ADD_DDC        0x04 /* "ADDCARD DDC GPIO pins" */
 142 #define GPIO_PIN_ADD_DDC_I2C    0x06 /* "ADDCARD DDC/I2C GPIO pins" */
 143
 144 /* Pre 915 */
 145 #define DEVICE_TYPE_NONE        0x00
 146 #define DEVICE_TYPE_CRT         0x01
 147 #define DEVICE_TYPE_TV          0x09
 148 #define DEVICE_TYPE_EFP         0x12
 149 #define DEVICE_TYPE_LFP         0x22
 150 /* On 915+ */
 151 #define DEVICE_TYPE_CRT_DPMS            0x6001
 152 #define DEVICE_TYPE_CRT_DPMS_HOTPLUG    0x4001
 153 #define DEVICE_TYPE_TV_COMPOSITE        0x0209
 154 #define DEVICE_TYPE_TV_MACROVISION      0x0289
 155 #define DEVICE_TYPE_TV_RF_COMPOSITE     0x020c
 156 #define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609
 157 #define DEVICE_TYPE_TV_SCART            0x0209
 158 #define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009
 159 #define DEVICE_TYPE_EFP_HOTPLUG_PWR     0x6012
 160 #define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052
 161 #define DEVICE_TYPE_EFP_DVI_I           0x6053
 162 #define DEVICE_TYPE_EFP_DVI_D_DUAL      0x6152
 163 #define DEVICE_TYPE_EFP_DVI_D_HDCP      0x60d2
 164 #define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062
 165 #define DEVICE_TYPE_OPENLDI_DUALPIX     0x6162
 166 #define DEVICE_TYPE_LFP_PANELLINK       0x5012
 167 #define DEVICE_TYPE_LFP_CMOS_PWR        0x5042
 168 #define DEVICE_TYPE_LFP_LVDS_PWR        0x5062
 169 #define DEVICE_TYPE_LFP_LVDS_DUAL       0x5162
 170 #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP  0x51e2
 171
 172 #define DEVICE_CFG_NONE         0x00
 173 #define DEVICE_CFG_12BIT_DVOB   0x01
 174 #define DEVICE_CFG_12BIT_DVOC   0x02
 175 #define DEVICE_CFG_24BIT_DVOBC  0x09
 176 #define DEVICE_CFG_24BIT_DVOCB  0x0a
 177 #define DEVICE_CFG_DUAL_DVOB    0x11
 178 #define DEVICE_CFG_DUAL_DVOC    0x12
 179 #define DEVICE_CFG_DUAL_DVOBC   0x13
 180 #define DEVICE_CFG_DUAL_LINK_DVOBC      0x19
 181 #define DEVICE_CFG_DUAL_LINK_DVOCB      0x1a
 182
 183 #define DEVICE_WIRE_NONE        0x00
 184 #define DEVICE_WIRE_DVOB        0x01
 185 #define DEVICE_WIRE_DVOC        0x02
 186 #define DEVICE_WIRE_DVOBC       0x03
 187 #define DEVICE_WIRE_DVOBB       0x05
 188 #define DEVICE_WIRE_DVOCC       0x06
 189 #define DEVICE_WIRE_DVOB_MASTER 0x0d
 190 #define DEVICE_WIRE_DVOC_MASTER 0x0e
 191
 192 #define DEVICE_PORT_DVOA        0x00 /* none on 845+ */
 193 #define DEVICE_PORT_DVOB        0x01
 194 #define DEVICE_PORT_DVOC        0x02
 195
 196 struct child_device_config {
 197         u16 handle;
 198         u16 device_type;
 199         u8  device_id[10]; /* See DEVICE_TYPE_* above */
 200         u16 addin_offset;
 201         u8  dvo_port; /* See Device_PORT_* above */
 202         u8  i2c_pin;
 203         u8  slave_addr;
 204         u8  ddc_pin;
 205         u16 edid_ptr;
 206         u8  dvo_cfg; /* See DEVICE_CFG_* above */
 207         u8  dvo2_port;
 208         u8  i2c2_pin;
 209         u8  slave2_addr;
 210         u8  ddc2_pin;
 211         u8  capabilities;
 212         u8  dvo_wiring;/* See DEVICE_WIRE_* above */
 213         u8  dvo2_wiring;
 214         u16 extended_type;
 215         u8  dvo_function;
 216 } __attribute__((packed));
 217
 218 struct bdb_general_definitions {
 219         /* DDC GPIO */
 220         u8 crt_ddc_gmbus_pin;
 221
 222         /* DPMS bits */
 223         u8 dpms_acpi:1;
 224         u8 skip_boot_crt_detect:1;
 225         u8 dpms_aim:1;
 226         u8 rsvd1:5; /* finish byte */
 227
 228         /* boot device bits */
 229         u8 boot_display[2];
 230         u8 child_dev_size;
 231
 232         /*
 233          * Device info:
 234          * If TV is present, it'll be at devices[0].
 235          * LVDS will be next, either devices[0] or [1], if present.
 236          * On some platforms the number of device is 6. But could be as few as
 237          * 4 if both TV and LVDS are missing.
 238          * And the device num is related with the size of general definition
 239          * block. It is obtained by using the following formula:
 240          * number = (block_size - sizeof(bdb_general_definitions))/
 241          *              sizeof(child_device_config);
 242          */
 243         struct child_device_config devices[0];
 244 } __attribute__((packed));
 245
 246 struct bdb_lvds_options {
 247         u8 panel_type;
 248         u8 rsvd1;
 249         /* LVDS capabilities, stored in a dword */
 250         u8 pfit_mode:2;
 251         u8 pfit_text_mode_enhanced:1;
 252         u8 pfit_gfx_mode_enhanced:1;
 253         u8 pfit_ratio_auto:1;
 254         u8 pixel_dither:1;
 255         u8 lvds_edid:1;
 256         u8 rsvd2:1;
 257         u8 rsvd4;
 258 } __attribute__((packed));
 259
 260 /* LFP pointer table contains entries to the struct below */
 261 struct bdb_lvds_lfp_data_ptr {
 262         u16 fp_timing_offset; /* offsets are from start of bdb */
 263         u8 fp_table_size;
 264         u16 dvo_timing_offset;
 265         u8 dvo_table_size;
 266         u16 panel_pnp_id_offset;
 267         u8 pnp_table_size;
 268 } __attribute__((packed));
 269
 270 struct bdb_lvds_lfp_data_ptrs {
 271         u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */
 272         struct bdb_lvds_lfp_data_ptr ptr[16];
 273 } __attribute__((packed));
 274
 275 /* LFP data has 3 blocks per entry */
 276 struct lvds_fp_timing {
 277         u16 x_res;
 278         u16 y_res;
 279         u32 lvds_reg;
 280         u32 lvds_reg_val;
 281         u32 pp_on_reg;
 282         u32 pp_on_reg_val;
 283         u32 pp_off_reg;
 284         u32 pp_off_reg_val;
 285         u32 pp_cycle_reg;
 286         u32 pp_cycle_reg_val;
 287         u32 pfit_reg;
 288         u32 pfit_reg_val;
 289         u16 terminator;
 290 } __attribute__((packed));
 291
 292 struct lvds_dvo_timing {
 293         u16 clock;              /**< In 10khz */
 294         u8 hactive_lo;
 295         u8 hblank_lo;
 296         u8 hblank_hi:4;
 297         u8 hactive_hi:4;
 298         u8 vactive_lo;
 299         u8 vblank_lo;
 300         u8 vblank_hi:4;
 301         u8 vactive_hi:4;
 302         u8 hsync_off_lo;
 303         u8 hsync_pulse_width;
 304         u8 vsync_pulse_width:4;
 305         u8 vsync_off:4;
 306         u8 rsvd0:6;
 307         u8 hsync_off_hi:2;
 308         u8 h_image;
 309         u8 v_image;
 310         u8 max_hv;
 311         u8 h_border;
 312         u8 v_border;
 313         u8 rsvd1:3;
 314         u8 digital:2;
 315         u8 vsync_positive:1;
 316         u8 hsync_positive:1;
 317         u8 rsvd2:1;
 318 } __attribute__((packed));
 319
 320 struct lvds_pnp_id {
 321         u16 mfg_name;
 322         u16 product_code;
 323         u32 serial;
 324         u8 mfg_week;
 325         u8 mfg_year;
 326 } __attribute__((packed));
 327
 328 struct bdb_lvds_lfp_data_entry {
 329         struct lvds_fp_timing fp_timing;
 330         struct lvds_dvo_timing dvo_timing;
 331         struct lvds_pnp_id pnp_id;
 332 } __attribute__((packed));
 333
 334 struct bdb_lvds_lfp_data {
 335         struct bdb_lvds_lfp_data_entry data[16];
 336 } __attribute__((packed));
 337
 338 struct aimdb_header {
 339         char signature[16];
 340         char oem_device[20];
 341         u16 aimdb_version;
 342         u16 aimdb_header_size;
 343         u16 aimdb_size;
 344 } __attribute__((packed));
 345
 346 struct aimdb_block {
 347         u8 aimdb_id;
 348         u16 aimdb_size;
 349 } __attribute__((packed));
 350
 351 struct vch_panel_data {
 352         u16 fp_timing_offset;
 353         u8 fp_timing_size;
 354         u16 dvo_timing_offset;
 355         u8 dvo_timing_size;
 356         u16 text_fitting_offset;
 357         u8 text_fitting_size;
 358         u16 graphics_fitting_offset;
 359         u8 graphics_fitting_size;
 360 } __attribute__((packed));
 361
 362 struct vch_bdb_22 {
 363         struct aimdb_block aimdb_block;
 364         struct vch_panel_data panels[16];
 365 } __attribute__((packed));
 366
 367 struct bdb_sdvo_lvds_options {
 368         u8 panel_backlight;
 369         u8 h40_set_panel_type;
 370         u8 panel_type;
 371         u8 ssc_clk_freq;
 372         u16 als_low_trip;
 373         u16 als_high_trip;
 374         u8 sclalarcoeff_tab_row_num;
 375         u8 sclalarcoeff_tab_row_size;
 376         u8 coefficient[8];
 377         u8 panel_misc_bits_1;
 378         u8 panel_misc_bits_2;
 379         u8 panel_misc_bits_3;
 380         u8 panel_misc_bits_4;
 381 } __attribute__((packed));
 382
 383
 384 #define BDB_DRIVER_FEATURE_NO_LVDS              0
 385 #define BDB_DRIVER_FEATURE_INT_LVDS             1
 386 #define BDB_DRIVER_FEATURE_SDVO_LVDS            2
 387 #define BDB_DRIVER_FEATURE_EDP                  3
 388
 389 struct bdb_driver_features {
 390         u8 boot_dev_algorithm:1;
 391         u8 block_display_switch:1;
 392         u8 allow_display_switch:1;
 393         u8 hotplug_dvo:1;
 394         u8 dual_view_zoom:1;
 395         u8 int15h_hook:1;
 396         u8 sprite_in_clone:1;
 397         u8 primary_lfp_id:1;
 398
 399         u16 boot_mode_x;
 400         u16 boot_mode_y;
 401         u8 boot_mode_bpp;
 402         u8 boot_mode_refresh;
 403
 404         u16 enable_lfp_primary:1;
 405         u16 selective_mode_pruning:1;
 406         u16 dual_frequency:1;
 407         u16 render_clock_freq:1; /* 0: high freq; 1: low freq */
 408         u16 nt_clone_support:1;
 409         u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */
 410         u16 sprite_display_assign:1; /* 0: secondary; 1: primary */
 411         u16 cui_aspect_scaling:1;
 412         u16 preserve_aspect_ratio:1;
 413         u16 sdvo_device_power_down:1;
 414         u16 crt_hotplug:1;
 415         u16 lvds_config:2;
 416         u16 tv_hotplug:1;
 417         u16 hdmi_config:2;
 418
 419         u8 static_display:1;
 420         u8 reserved2:7;
 421         u16 legacy_crt_max_x;
 422         u16 legacy_crt_max_y;
 423         u8 legacy_crt_max_refresh;
 424
 425         u8 hdmi_termination;
 426         u8 custom_vbt_version;
 427 } __attribute__((packed));
 428
 429 bool intel_init_bios(struct drm_device *dev);
 430
 431 /*
 432  * Driver<->VBIOS interaction occurs through scratch bits in
 433  * GR18 & SWF*.
 434  */
 435
 436 /* GR18 bits are set on display switch and hotkey events */
 437 #define GR18_DRIVER_SWITCH_EN   (1<<7) /* 0: VBIOS control, 1: driver control */
 438 #define GR18_HOTKEY_MASK        0x78 /* See also SWF4 15:0 */
 439 #define   GR18_HK_NONE          (0x0<<3)
 440 #define   GR18_HK_LFP_STRETCH   (0x1<<3)
 441 #define   GR18_HK_TOGGLE_DISP   (0x2<<3)
 442 #define   GR18_HK_DISP_SWITCH   (0x4<<3) /* see SWF14 15:0 for what to enable */
 443 #define   GR18_HK_POPUP_DISABLED (0x6<<3)
 444 #define   GR18_HK_POPUP_ENABLED (0x7<<3)
 445 #define   GR18_HK_PFIT          (0x8<<3)
 446 #define   GR18_HK_APM_CHANGE    (0xa<<3)
 447 #define   GR18_HK_MULTIPLE      (0xc<<3)
 448 #define GR18_USER_INT_EN        (1<<2)
 449 #define GR18_A0000_FLUSH_EN     (1<<1)
 450 #define GR18_SMM_EN             (1<<0)
 451
 452 /* Set by driver, cleared by VBIOS */
 453 #define SWF00_YRES_SHIFT        16
 454 #define SWF00_XRES_SHIFT        0
 455 #define SWF00_RES_MASK          0xffff
 456
 457 /* Set by VBIOS at boot time and driver at runtime */
 458 #define SWF01_TV2_FORMAT_SHIFT  8
 459 #define SWF01_TV1_FORMAT_SHIFT  0
 460 #define SWF01_TV_FORMAT_MASK    0xffff
 461
 462 #define SWF10_VBIOS_BLC_I2C_EN  (1<<29)
 463 #define SWF10_GTT_OVERRIDE_EN   (1<<28)
 464 #define SWF10_LFP_DPMS_OVR      (1<<27) /* override DPMS on display switch */
 465 #define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24)
 466 #define   SWF10_OLD_TOGGLE      0x0
 467 #define   SWF10_TOGGLE_LIST_1   0x1
 468 #define   SWF10_TOGGLE_LIST_2   0x2
 469 #define   SWF10_TOGGLE_LIST_3   0x3
 470 #define   SWF10_TOGGLE_LIST_4   0x4
 471 #define SWF10_PANNING_EN        (1<<23)
 472 #define SWF10_DRIVER_LOADED     (1<<22)
 473 #define SWF10_EXTENDED_DESKTOP  (1<<21)
 474 #define SWF10_EXCLUSIVE_MODE    (1<<20)
 475 #define SWF10_OVERLAY_EN        (1<<19)
 476 #define SWF10_PLANEB_HOLDOFF    (1<<18)
 477 #define SWF10_PLANEA_HOLDOFF    (1<<17)
 478 #define SWF10_VGA_HOLDOFF       (1<<16)
 479 #define SWF10_ACTIVE_DISP_MASK  0xffff
 480 #define   SWF10_PIPEB_LFP2      (1<<15)
 481 #define   SWF10_PIPEB_EFP2      (1<<14)
 482 #define   SWF10_PIPEB_TV2       (1<<13)
 483 #define   SWF10_PIPEB_CRT2      (1<<12)
 484 #define   SWF10_PIPEB_LFP       (1<<11)
 485 #define   SWF10_PIPEB_EFP       (1<<10)
 486 #define   SWF10_PIPEB_TV        (1<<9)
 487 #define   SWF10_PIPEB_CRT       (1<<8)
 488 #define   SWF10_PIPEA_LFP2      (1<<7)
 489 #define   SWF10_PIPEA_EFP2      (1<<6)
 490 #define   SWF10_PIPEA_TV2       (1<<5)
 491 #define   SWF10_PIPEA_CRT2      (1<<4)
 492 #define   SWF10_PIPEA_LFP       (1<<3)
 493 #define   SWF10_PIPEA_EFP       (1<<2)
 494 #define   SWF10_PIPEA_TV        (1<<1)
 495 #define   SWF10_PIPEA_CRT       (1<<0)
 496
 497 #define SWF11_MEMORY_SIZE_SHIFT 16
 498 #define SWF11_SV_TEST_EN        (1<<15)
 499 #define SWF11_IS_AGP            (1<<14)
 500 #define SWF11_DISPLAY_HOLDOFF   (1<<13)
 501 #define SWF11_DPMS_REDUCED      (1<<12)
 502 #define SWF11_IS_VBE_MODE       (1<<11)
 503 #define SWF11_PIPEB_ACCESS      (1<<10) /* 0 here means pipe a */
 504 #define SWF11_DPMS_MASK         0x07
 505 #define   SWF11_DPMS_OFF        (1<<2)
 506 #define   SWF11_DPMS_SUSPEND    (1<<1)
 507 #define   SWF11_DPMS_STANDBY    (1<<0)
 508 #define   SWF11_DPMS_ON         0
 509
 510 #define SWF14_GFX_PFIT_EN       (1<<31)
 511 #define SWF14_TEXT_PFIT_EN      (1<<30)
 512 #define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */
 513 #define SWF14_POPUP_EN          (1<<28)
 514 #define SWF14_DISPLAY_HOLDOFF   (1<<27)
 515 #define SWF14_DISP_DETECT_EN    (1<<26)
 516 #define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */
 517 #define SWF14_DRIVER_STATUS     (1<<24)
 518 #define SWF14_OS_TYPE_WIN9X     (1<<23)
 519 #define SWF14_OS_TYPE_WINNT     (1<<22)
 520 /* 21:19 rsvd */
 521 #define SWF14_PM_TYPE_MASK      0x00070000
 522 #define   SWF14_PM_ACPI_VIDEO   (0x4 << 16)
 523 #define   SWF14_PM_ACPI         (0x3 << 16)
 524 #define   SWF14_PM_APM_12       (0x2 << 16)
 525 #define   SWF14_PM_APM_11       (0x1 << 16)
 526 #define SWF14_HK_REQUEST_MASK   0x0000ffff /* see GR18 6:3 for event type */
 527           /* if GR18 indicates a display switch */
 528 #define   SWF14_DS_PIPEB_LFP2_EN (1<<15)
 529 #define   SWF14_DS_PIPEB_EFP2_EN (1<<14)
 530 #define   SWF14_DS_PIPEB_TV2_EN  (1<<13)
 531 #define   SWF14_DS_PIPEB_CRT2_EN (1<<12)
 532 #define   SWF14_DS_PIPEB_LFP_EN  (1<<11)
 533 #define   SWF14_DS_PIPEB_EFP_EN  (1<<10)
 534 #define   SWF14_DS_PIPEB_TV_EN   (1<<9)
 535 #define   SWF14_DS_PIPEB_CRT_EN  (1<<8)
 536 #define   SWF14_DS_PIPEA_LFP2_EN (1<<7)
 537 #define   SWF14_DS_PIPEA_EFP2_EN (1<<6)
 538 #define   SWF14_DS_PIPEA_TV2_EN  (1<<5)
 539 #define   SWF14_DS_PIPEA_CRT2_EN (1<<4)
 540 #define   SWF14_DS_PIPEA_LFP_EN  (1<<3)
 541 #define   SWF14_DS_PIPEA_EFP_EN  (1<<2)
 542 #define   SWF14_DS_PIPEA_TV_EN   (1<<1)
 543 #define   SWF14_DS_PIPEA_CRT_EN  (1<<0)
 544           /* if GR18 indicates a panel fitting request */
 545 #define   SWF14_PFIT_EN         (1<<0) /* 0 means disable */
 546           /* if GR18 indicates an APM change request */
 547 #define   SWF14_APM_HIBERNATE   0x4
 548 #define   SWF14_APM_SUSPEND     0x3
 549 #define   SWF14_APM_STANDBY     0x1
 550 #define   SWF14_APM_RESTORE     0x0
 551
 552 #endif /* _I830_BIOS_H_ */