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Full support for Ginger Console
[linux-ginger.git] / drivers / gpu / drm / i915 / intel_dp.c
blobf4856a510476bcfc117f60ad334d06293d93cd89
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include "drmP.h"
30 #include "drm.h"
31 #include "drm_crtc.h"
32 #include "drm_crtc_helper.h"
33 #include "intel_drv.h"
34 #include "i915_drm.h"
35 #include "i915_drv.h"
36 #include "intel_dp.h"
37
38 #define DP_LINK_STATUS_SIZE 6
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
41 #define DP_LINK_CONFIGURATION_SIZE 9
42
43 #define IS_eDP(i) ((i)->type == INTEL_OUTPUT_EDP)
44
45 struct intel_dp_priv {
46 uint32_t output_reg;
47 uint32_t DP;
48 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
49 uint32_t save_DP;
50 uint8_t save_link_configuration[DP_LINK_CONFIGURATION_SIZE];
51 bool has_audio;
52 int dpms_mode;
53 uint8_t link_bw;
54 uint8_t lane_count;
55 uint8_t dpcd[4];
56 struct intel_output *intel_output;
57 struct i2c_adapter adapter;
58 struct i2c_algo_dp_aux_data algo;
59 };
60
61 static void
62 intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
63 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]);
64
65 static void
66 intel_dp_link_down(struct intel_output *intel_output, uint32_t DP);
67
68 void
69 intel_edp_link_config (struct intel_output *intel_output,
70 int *lane_num, int *link_bw)
71 {
72 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
73
74 *lane_num = dp_priv->lane_count;
75 if (dp_priv->link_bw == DP_LINK_BW_1_62)
76 *link_bw = 162000;
77 else if (dp_priv->link_bw == DP_LINK_BW_2_7)
78 *link_bw = 270000;
79 }
80
81 static int
82 intel_dp_max_lane_count(struct intel_output *intel_output)
83 {
84 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
85 int max_lane_count = 4;
86
87 if (dp_priv->dpcd[0] >= 0x11) {
88 max_lane_count = dp_priv->dpcd[2] & 0x1f;
89 switch (max_lane_count) {
90 case 1: case 2: case 4:
91 break;
92 default:
93 max_lane_count = 4;
94 }
95 }
96 return max_lane_count;
97 }
98
99 static int
100 intel_dp_max_link_bw(struct intel_output *intel_output)
101 {
102 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
103 int max_link_bw = dp_priv->dpcd[1];
104
105 switch (max_link_bw) {
106 case DP_LINK_BW_1_62:
107 case DP_LINK_BW_2_7:
108 break;
109 default:
110 max_link_bw = DP_LINK_BW_1_62;
111 break;
112 }
113 return max_link_bw;
114 }
115
116 static int
117 intel_dp_link_clock(uint8_t link_bw)
118 {
119 if (link_bw == DP_LINK_BW_2_7)
120 return 270000;
121 else
122 return 162000;
123 }
124
125 /* I think this is a fiction */
126 static int
127 intel_dp_link_required(int pixel_clock)
128 {
129 return pixel_clock * 3;
130 }
131
132 static int
133 intel_dp_mode_valid(struct drm_connector *connector,
134 struct drm_display_mode *mode)
135 {
136 struct intel_output *intel_output = to_intel_output(connector);
137 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_output));
138 int max_lanes = intel_dp_max_lane_count(intel_output);
139
140 if (intel_dp_link_required(mode->clock) > max_link_clock * max_lanes)
141 return MODE_CLOCK_HIGH;
142
143 if (mode->clock < 10000)
144 return MODE_CLOCK_LOW;
145
146 return MODE_OK;
147 }
148
149 static uint32_t
150 pack_aux(uint8_t *src, int src_bytes)
151 {
152 int i;
153 uint32_t v = 0;
154
155 if (src_bytes > 4)
156 src_bytes = 4;
157 for (i = 0; i < src_bytes; i++)
158 v |= ((uint32_t) src[i]) << ((3-i) * 8);
159 return v;
160 }
161
162 static void
163 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
164 {
165 int i;
166 if (dst_bytes > 4)
167 dst_bytes = 4;
168 for (i = 0; i < dst_bytes; i++)
169 dst[i] = src >> ((3-i) * 8);
170 }
171
172 /* hrawclock is 1/4 the FSB frequency */
173 static int
174 intel_hrawclk(struct drm_device *dev)
175 {
176 struct drm_i915_private *dev_priv = dev->dev_private;
177 uint32_t clkcfg;
178
179 clkcfg = I915_READ(CLKCFG);
180 switch (clkcfg & CLKCFG_FSB_MASK) {
181 case CLKCFG_FSB_400:
182 return 100;
183 case CLKCFG_FSB_533:
184 return 133;
185 case CLKCFG_FSB_667:
186 return 166;
187 case CLKCFG_FSB_800:
188 return 200;
189 case CLKCFG_FSB_1067:
190 return 266;
191 case CLKCFG_FSB_1333:
192 return 333;
193 /* these two are just a guess; one of them might be right */
194 case CLKCFG_FSB_1600:
195 case CLKCFG_FSB_1600_ALT:
196 return 400;
197 default:
198 return 133;
199 }
200 }
201
202 static int
203 intel_dp_aux_ch(struct intel_output *intel_output,
204 uint8_t *send, int send_bytes,
205 uint8_t *recv, int recv_size)
206 {
207 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
208 uint32_t output_reg = dp_priv->output_reg;
209 struct drm_device *dev = intel_output->base.dev;
210 struct drm_i915_private *dev_priv = dev->dev_private;
211 uint32_t ch_ctl = output_reg + 0x10;
212 uint32_t ch_data = ch_ctl + 4;
213 int i;
214 int recv_bytes;
215 uint32_t ctl;
216 uint32_t status;
217 uint32_t aux_clock_divider;
218 int try;
219
220 /* The clock divider is based off the hrawclk,
221 * and would like to run at 2MHz. So, take the
222 * hrawclk value and divide by 2 and use that
223 */
224 if (IS_eDP(intel_output))
225 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
226 else if (IS_IGDNG(dev))
227 aux_clock_divider = 62; /* IGDNG: input clock fixed at 125Mhz */
228 else
229 aux_clock_divider = intel_hrawclk(dev) / 2;
230
231 /* Must try at least 3 times according to DP spec */
232 for (try = 0; try < 5; try++) {
233 /* Load the send data into the aux channel data registers */
234 for (i = 0; i < send_bytes; i += 4) {
235 uint32_t d = pack_aux(send + i, send_bytes - i);
236
237 I915_WRITE(ch_data + i, d);
238 }
239
240 ctl = (DP_AUX_CH_CTL_SEND_BUSY |
241 DP_AUX_CH_CTL_TIME_OUT_400us |
242 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
243 (5 << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
244 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
245 DP_AUX_CH_CTL_DONE |
246 DP_AUX_CH_CTL_TIME_OUT_ERROR |
247 DP_AUX_CH_CTL_RECEIVE_ERROR);
248
249 /* Send the command and wait for it to complete */
250 I915_WRITE(ch_ctl, ctl);
251 (void) I915_READ(ch_ctl);
252 for (;;) {
253 udelay(100);
254 status = I915_READ(ch_ctl);
255 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
256 break;
257 }
258
259 /* Clear done status and any errors */
260 I915_WRITE(ch_ctl, (status |
261 DP_AUX_CH_CTL_DONE |
262 DP_AUX_CH_CTL_TIME_OUT_ERROR |
263 DP_AUX_CH_CTL_RECEIVE_ERROR));
264 (void) I915_READ(ch_ctl);
265 if ((status & DP_AUX_CH_CTL_TIME_OUT_ERROR) == 0)
266 break;
267 }
268
269 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
270 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
271 return -EBUSY;
272 }
273
274 /* Check for timeout or receive error.
275 * Timeouts occur when the sink is not connected
276 */
277 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
278 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
279 return -EIO;
280 }
281
282 /* Timeouts occur when the device isn't connected, so they're
283 * "normal" -- don't fill the kernel log with these */
284 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
285 DRM_DEBUG("dp_aux_ch timeout status 0x%08x\n", status);
286 return -ETIMEDOUT;
287 }
288
289 /* Unload any bytes sent back from the other side */
290 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
291 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
292
293 if (recv_bytes > recv_size)
294 recv_bytes = recv_size;
295
296 for (i = 0; i < recv_bytes; i += 4) {
297 uint32_t d = I915_READ(ch_data + i);
298
299 unpack_aux(d, recv + i, recv_bytes - i);
300 }
301
302 return recv_bytes;
303 }
304
305 /* Write data to the aux channel in native mode */
306 static int
307 intel_dp_aux_native_write(struct intel_output *intel_output,
308 uint16_t address, uint8_t *send, int send_bytes)
309 {
310 int ret;
311 uint8_t msg[20];
312 int msg_bytes;
313 uint8_t ack;
314
315 if (send_bytes > 16)
316 return -1;
317 msg[0] = AUX_NATIVE_WRITE << 4;
318 msg[1] = address >> 8;
319 msg[2] = address & 0xff;
320 msg[3] = send_bytes - 1;
321 memcpy(&msg[4], send, send_bytes);
322 msg_bytes = send_bytes + 4;
323 for (;;) {
324 ret = intel_dp_aux_ch(intel_output, msg, msg_bytes, &ack, 1);
325 if (ret < 0)
326 return ret;
327 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
328 break;
329 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
330 udelay(100);
331 else
332 return -EIO;
333 }
334 return send_bytes;
335 }
336
337 /* Write a single byte to the aux channel in native mode */
338 static int
339 intel_dp_aux_native_write_1(struct intel_output *intel_output,
340 uint16_t address, uint8_t byte)
341 {
342 return intel_dp_aux_native_write(intel_output, address, &byte, 1);
343 }
344
345 /* read bytes from a native aux channel */
346 static int
347 intel_dp_aux_native_read(struct intel_output *intel_output,
348 uint16_t address, uint8_t *recv, int recv_bytes)
349 {
350 uint8_t msg[4];
351 int msg_bytes;
352 uint8_t reply[20];
353 int reply_bytes;
354 uint8_t ack;
355 int ret;
356
357 msg[0] = AUX_NATIVE_READ << 4;
358 msg[1] = address >> 8;
359 msg[2] = address & 0xff;
360 msg[3] = recv_bytes - 1;
361
362 msg_bytes = 4;
363 reply_bytes = recv_bytes + 1;
364
365 for (;;) {
366 ret = intel_dp_aux_ch(intel_output, msg, msg_bytes,
367 reply, reply_bytes);
368 if (ret == 0)
369 return -EPROTO;
370 if (ret < 0)
371 return ret;
372 ack = reply[0];
373 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
374 memcpy(recv, reply + 1, ret - 1);
375 return ret - 1;
376 }
377 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
378 udelay(100);
379 else
380 return -EIO;
381 }
382 }
383
384 static int
385 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter,
386 uint8_t *send, int send_bytes,
387 uint8_t *recv, int recv_bytes)
388 {
389 struct intel_dp_priv *dp_priv = container_of(adapter,
390 struct intel_dp_priv,
391 adapter);
392 struct intel_output *intel_output = dp_priv->intel_output;
393
394 return intel_dp_aux_ch(intel_output,
395 send, send_bytes, recv, recv_bytes);
396 }
397
398 static int
399 intel_dp_i2c_init(struct intel_output *intel_output, const char *name)
400 {
401 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
402
403 DRM_ERROR("i2c_init %s\n", name);
404 dp_priv->algo.running = false;
405 dp_priv->algo.address = 0;
406 dp_priv->algo.aux_ch = intel_dp_i2c_aux_ch;
407
408 memset(&dp_priv->adapter, '\0', sizeof (dp_priv->adapter));
409 dp_priv->adapter.owner = THIS_MODULE;
410 dp_priv->adapter.class = I2C_CLASS_DDC;
411 strncpy (dp_priv->adapter.name, name, sizeof(dp_priv->adapter.name) - 1);
412 dp_priv->adapter.name[sizeof(dp_priv->adapter.name) - 1] = '\0';
413 dp_priv->adapter.algo_data = &dp_priv->algo;
414 dp_priv->adapter.dev.parent = &intel_output->base.kdev;
415
416 return i2c_dp_aux_add_bus(&dp_priv->adapter);
417 }
418
419 static bool
420 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
421 struct drm_display_mode *adjusted_mode)
422 {
423 struct intel_output *intel_output = enc_to_intel_output(encoder);
424 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
425 int lane_count, clock;
426 int max_lane_count = intel_dp_max_lane_count(intel_output);
427 int max_clock = intel_dp_max_link_bw(intel_output) == DP_LINK_BW_2_7 ? 1 : 0;
428 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
429
430 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
431 for (clock = 0; clock <= max_clock; clock++) {
432 int link_avail = intel_dp_link_clock(bws[clock]) * lane_count;
433
434 if (intel_dp_link_required(mode->clock) <= link_avail) {
435 dp_priv->link_bw = bws[clock];
436 dp_priv->lane_count = lane_count;
437 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
438 DRM_DEBUG("Display port link bw %02x lane count %d clock %d\n",
439 dp_priv->link_bw, dp_priv->lane_count,
440 adjusted_mode->clock);
441 return true;
442 }
443 }
444 }
445 return false;
446 }
447
448 struct intel_dp_m_n {
449 uint32_t tu;
450 uint32_t gmch_m;
451 uint32_t gmch_n;
452 uint32_t link_m;
453 uint32_t link_n;
454 };
455
456 static void
457 intel_reduce_ratio(uint32_t *num, uint32_t *den)
458 {
459 while (*num > 0xffffff || *den > 0xffffff) {
460 *num >>= 1;
461 *den >>= 1;
462 }
463 }
464
465 static void
466 intel_dp_compute_m_n(int bytes_per_pixel,
467 int nlanes,
468 int pixel_clock,
469 int link_clock,
470 struct intel_dp_m_n *m_n)
471 {
472 m_n->tu = 64;
473 m_n->gmch_m = pixel_clock * bytes_per_pixel;
474 m_n->gmch_n = link_clock * nlanes;
475 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
476 m_n->link_m = pixel_clock;
477 m_n->link_n = link_clock;
478 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
479 }
480
481 void
482 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
483 struct drm_display_mode *adjusted_mode)
484 {
485 struct drm_device *dev = crtc->dev;
486 struct drm_mode_config *mode_config = &dev->mode_config;
487 struct drm_connector *connector;
488 struct drm_i915_private *dev_priv = dev->dev_private;
489 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
490 int lane_count = 4;
491 struct intel_dp_m_n m_n;
492
493 /*
494 * Find the lane count in the intel_output private
495 */
496 list_for_each_entry(connector, &mode_config->connector_list, head) {
497 struct intel_output *intel_output = to_intel_output(connector);
498 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
499
500 if (!connector->encoder || connector->encoder->crtc != crtc)
501 continue;
502
503 if (intel_output->type == INTEL_OUTPUT_DISPLAYPORT) {
504 lane_count = dp_priv->lane_count;
505 break;
506 }
507 }
508
509 /*
510 * Compute the GMCH and Link ratios. The '3' here is
511 * the number of bytes_per_pixel post-LUT, which we always
512 * set up for 8-bits of R/G/B, or 3 bytes total.
513 */
514 intel_dp_compute_m_n(3, lane_count,
515 mode->clock, adjusted_mode->clock, &m_n);
516
517 if (IS_IGDNG(dev)) {
518 if (intel_crtc->pipe == 0) {
519 I915_WRITE(TRANSA_DATA_M1,
520 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
521 m_n.gmch_m);
522 I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n);
523 I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m);
524 I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
525 } else {
526 I915_WRITE(TRANSB_DATA_M1,
527 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
528 m_n.gmch_m);
529 I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
530 I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
531 I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
532 }
533 } else {
534 if (intel_crtc->pipe == 0) {
535 I915_WRITE(PIPEA_GMCH_DATA_M,
536 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
537 m_n.gmch_m);
538 I915_WRITE(PIPEA_GMCH_DATA_N,
539 m_n.gmch_n);
540 I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
541 I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
542 } else {
543 I915_WRITE(PIPEB_GMCH_DATA_M,
544 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
545 m_n.gmch_m);
546 I915_WRITE(PIPEB_GMCH_DATA_N,
547 m_n.gmch_n);
548 I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
549 I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
550 }
551 }
552 }
553
554 static void
555 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
556 struct drm_display_mode *adjusted_mode)
557 {
558 struct intel_output *intel_output = enc_to_intel_output(encoder);
559 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
560 struct drm_crtc *crtc = intel_output->enc.crtc;
561 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
562
563 dp_priv->DP = (DP_LINK_TRAIN_OFF |
564 DP_VOLTAGE_0_4 |
565 DP_PRE_EMPHASIS_0 |
566 DP_SYNC_VS_HIGH |
567 DP_SYNC_HS_HIGH);
568
569 switch (dp_priv->lane_count) {
570 case 1:
571 dp_priv->DP |= DP_PORT_WIDTH_1;
572 break;
573 case 2:
574 dp_priv->DP |= DP_PORT_WIDTH_2;
575 break;
576 case 4:
577 dp_priv->DP |= DP_PORT_WIDTH_4;
578 break;
579 }
580 if (dp_priv->has_audio)
581 dp_priv->DP |= DP_AUDIO_OUTPUT_ENABLE;
582
583 memset(dp_priv->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
584 dp_priv->link_configuration[0] = dp_priv->link_bw;
585 dp_priv->link_configuration[1] = dp_priv->lane_count;
586
587 /*
588 * Check for DPCD version > 1.1,
589 * enable enahanced frame stuff in that case
590 */
591 if (dp_priv->dpcd[0] >= 0x11) {
592 dp_priv->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
593 dp_priv->DP |= DP_ENHANCED_FRAMING;
594 }
595
596 if (intel_crtc->pipe == 1)
597 dp_priv->DP |= DP_PIPEB_SELECT;
598
599 if (IS_eDP(intel_output)) {
600 /* don't miss out required setting for eDP */
601 dp_priv->DP |= DP_PLL_ENABLE;
602 if (adjusted_mode->clock < 200000)
603 dp_priv->DP |= DP_PLL_FREQ_160MHZ;
604 else
605 dp_priv->DP |= DP_PLL_FREQ_270MHZ;
606 }
607 }
608
609 static void igdng_edp_backlight_on (struct drm_device *dev)
610 {
611 struct drm_i915_private *dev_priv = dev->dev_private;
612 u32 pp;
613
614 DRM_DEBUG("\n");
615 pp = I915_READ(PCH_PP_CONTROL);
616 pp |= EDP_BLC_ENABLE;
617 I915_WRITE(PCH_PP_CONTROL, pp);
618 }
619
620 static void igdng_edp_backlight_off (struct drm_device *dev)
621 {
622 struct drm_i915_private *dev_priv = dev->dev_private;
623 u32 pp;
624
625 DRM_DEBUG("\n");
626 pp = I915_READ(PCH_PP_CONTROL);
627 pp &= ~EDP_BLC_ENABLE;
628 I915_WRITE(PCH_PP_CONTROL, pp);
629 }
630
631 static void
632 intel_dp_dpms(struct drm_encoder *encoder, int mode)
633 {
634 struct intel_output *intel_output = enc_to_intel_output(encoder);
635 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
636 struct drm_device *dev = intel_output->base.dev;
637 struct drm_i915_private *dev_priv = dev->dev_private;
638 uint32_t dp_reg = I915_READ(dp_priv->output_reg);
639
640 if (mode != DRM_MODE_DPMS_ON) {
641 if (dp_reg & DP_PORT_EN) {
642 intel_dp_link_down(intel_output, dp_priv->DP);
643 if (IS_eDP(intel_output))
644 igdng_edp_backlight_off(dev);
645 }
646 } else {
647 if (!(dp_reg & DP_PORT_EN)) {
648 intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration);
649 if (IS_eDP(intel_output))
650 igdng_edp_backlight_on(dev);
651 }
652 }
653 dp_priv->dpms_mode = mode;
654 }
655
656 /*
657 * Fetch AUX CH registers 0x202 - 0x207 which contain
658 * link status information
659 */
660 static bool
661 intel_dp_get_link_status(struct intel_output *intel_output,
662 uint8_t link_status[DP_LINK_STATUS_SIZE])
663 {
664 int ret;
665
666 ret = intel_dp_aux_native_read(intel_output,
667 DP_LANE0_1_STATUS,
668 link_status, DP_LINK_STATUS_SIZE);
669 if (ret != DP_LINK_STATUS_SIZE)
670 return false;
671 return true;
672 }
673
674 static uint8_t
675 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
676 int r)
677 {
678 return link_status[r - DP_LANE0_1_STATUS];
679 }
680
681 static void
682 intel_dp_save(struct drm_connector *connector)
683 {
684 struct intel_output *intel_output = to_intel_output(connector);
685 struct drm_device *dev = intel_output->base.dev;
686 struct drm_i915_private *dev_priv = dev->dev_private;
687 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
688
689 dp_priv->save_DP = I915_READ(dp_priv->output_reg);
690 intel_dp_aux_native_read(intel_output, DP_LINK_BW_SET,
691 dp_priv->save_link_configuration,
692 sizeof (dp_priv->save_link_configuration));
693 }
694
695 static uint8_t
696 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
697 int lane)
698 {
699 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
700 int s = ((lane & 1) ?
701 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
702 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
703 uint8_t l = intel_dp_link_status(link_status, i);
704
705 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
706 }
707
708 static uint8_t
709 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
710 int lane)
711 {
712 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
713 int s = ((lane & 1) ?
714 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
715 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
716 uint8_t l = intel_dp_link_status(link_status, i);
717
718 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
719 }
720
721
722 #if 0
723 static char *voltage_names[] = {
724 "0.4V", "0.6V", "0.8V", "1.2V"
725 };
726 static char *pre_emph_names[] = {
727 "0dB", "3.5dB", "6dB", "9.5dB"
728 };
729 static char *link_train_names[] = {
730 "pattern 1", "pattern 2", "idle", "off"
731 };
732 #endif
733
734 /*
735 * These are source-specific values; current Intel hardware supports
736 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
737 */
738 #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
739
740 static uint8_t
741 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
742 {
743 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
744 case DP_TRAIN_VOLTAGE_SWING_400:
745 return DP_TRAIN_PRE_EMPHASIS_6;
746 case DP_TRAIN_VOLTAGE_SWING_600:
747 return DP_TRAIN_PRE_EMPHASIS_6;
748 case DP_TRAIN_VOLTAGE_SWING_800:
749 return DP_TRAIN_PRE_EMPHASIS_3_5;
750 case DP_TRAIN_VOLTAGE_SWING_1200:
751 default:
752 return DP_TRAIN_PRE_EMPHASIS_0;
753 }
754 }
755
756 static void
757 intel_get_adjust_train(struct intel_output *intel_output,
758 uint8_t link_status[DP_LINK_STATUS_SIZE],
759 int lane_count,
760 uint8_t train_set[4])
761 {
762 uint8_t v = 0;
763 uint8_t p = 0;
764 int lane;
765
766 for (lane = 0; lane < lane_count; lane++) {
767 uint8_t this_v = intel_get_adjust_request_voltage(link_status, lane);
768 uint8_t this_p = intel_get_adjust_request_pre_emphasis(link_status, lane);
769
770 if (this_v > v)
771 v = this_v;
772 if (this_p > p)
773 p = this_p;
774 }
775
776 if (v >= I830_DP_VOLTAGE_MAX)
777 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
778
779 if (p >= intel_dp_pre_emphasis_max(v))
780 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
781
782 for (lane = 0; lane < 4; lane++)
783 train_set[lane] = v | p;
784 }
785
786 static uint32_t
787 intel_dp_signal_levels(uint8_t train_set, int lane_count)
788 {
789 uint32_t signal_levels = 0;
790
791 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
792 case DP_TRAIN_VOLTAGE_SWING_400:
793 default:
794 signal_levels |= DP_VOLTAGE_0_4;
795 break;
796 case DP_TRAIN_VOLTAGE_SWING_600:
797 signal_levels |= DP_VOLTAGE_0_6;
798 break;
799 case DP_TRAIN_VOLTAGE_SWING_800:
800 signal_levels |= DP_VOLTAGE_0_8;
801 break;
802 case DP_TRAIN_VOLTAGE_SWING_1200:
803 signal_levels |= DP_VOLTAGE_1_2;
804 break;
805 }
806 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
807 case DP_TRAIN_PRE_EMPHASIS_0:
808 default:
809 signal_levels |= DP_PRE_EMPHASIS_0;
810 break;
811 case DP_TRAIN_PRE_EMPHASIS_3_5:
812 signal_levels |= DP_PRE_EMPHASIS_3_5;
813 break;
814 case DP_TRAIN_PRE_EMPHASIS_6:
815 signal_levels |= DP_PRE_EMPHASIS_6;
816 break;
817 case DP_TRAIN_PRE_EMPHASIS_9_5:
818 signal_levels |= DP_PRE_EMPHASIS_9_5;
819 break;
820 }
821 return signal_levels;
822 }
823
824 static uint8_t
825 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
826 int lane)
827 {
828 int i = DP_LANE0_1_STATUS + (lane >> 1);
829 int s = (lane & 1) * 4;
830 uint8_t l = intel_dp_link_status(link_status, i);
831
832 return (l >> s) & 0xf;
833 }
834
835 /* Check for clock recovery is done on all channels */
836 static bool
837 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
838 {
839 int lane;
840 uint8_t lane_status;
841
842 for (lane = 0; lane < lane_count; lane++) {
843 lane_status = intel_get_lane_status(link_status, lane);
844 if ((lane_status & DP_LANE_CR_DONE) == 0)
845 return false;
846 }
847 return true;
848 }
849
850 /* Check to see if channel eq is done on all channels */
851 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
852 DP_LANE_CHANNEL_EQ_DONE|\
853 DP_LANE_SYMBOL_LOCKED)
854 static bool
855 intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
856 {
857 uint8_t lane_align;
858 uint8_t lane_status;
859 int lane;
860
861 lane_align = intel_dp_link_status(link_status,
862 DP_LANE_ALIGN_STATUS_UPDATED);
863 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
864 return false;
865 for (lane = 0; lane < lane_count; lane++) {
866 lane_status = intel_get_lane_status(link_status, lane);
867 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
868 return false;
869 }
870 return true;
871 }
872
873 static bool
874 intel_dp_set_link_train(struct intel_output *intel_output,
875 uint32_t dp_reg_value,
876 uint8_t dp_train_pat,
877 uint8_t train_set[4],
878 bool first)
879 {
880 struct drm_device *dev = intel_output->base.dev;
881 struct drm_i915_private *dev_priv = dev->dev_private;
882 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
883 int ret;
884
885 I915_WRITE(dp_priv->output_reg, dp_reg_value);
886 POSTING_READ(dp_priv->output_reg);
887 if (first)
888 intel_wait_for_vblank(dev);
889
890 intel_dp_aux_native_write_1(intel_output,
891 DP_TRAINING_PATTERN_SET,
892 dp_train_pat);
893
894 ret = intel_dp_aux_native_write(intel_output,
895 DP_TRAINING_LANE0_SET, train_set, 4);
896 if (ret != 4)
897 return false;
898
899 return true;
900 }
901
902 static void
903 intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
904 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE])
905 {
906 struct drm_device *dev = intel_output->base.dev;
907 struct drm_i915_private *dev_priv = dev->dev_private;
908 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
909 uint8_t train_set[4];
910 uint8_t link_status[DP_LINK_STATUS_SIZE];
911 int i;
912 uint8_t voltage;
913 bool clock_recovery = false;
914 bool channel_eq = false;
915 bool first = true;
916 int tries;
917
918 /* Write the link configuration data */
919 intel_dp_aux_native_write(intel_output, 0x100,
920 link_configuration, DP_LINK_CONFIGURATION_SIZE);
921
922 DP |= DP_PORT_EN;
923 DP &= ~DP_LINK_TRAIN_MASK;
924 memset(train_set, 0, 4);
925 voltage = 0xff;
926 tries = 0;
927 clock_recovery = false;
928 for (;;) {
929 /* Use train_set[0] to set the voltage and pre emphasis values */
930 uint32_t signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
931 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
932
933 if (!intel_dp_set_link_train(intel_output, DP | DP_LINK_TRAIN_PAT_1,
934 DP_TRAINING_PATTERN_1, train_set, first))
935 break;
936 first = false;
937 /* Set training pattern 1 */
938
939 udelay(100);
940 if (!intel_dp_get_link_status(intel_output, link_status))
941 break;
942
943 if (intel_clock_recovery_ok(link_status, dp_priv->lane_count)) {
944 clock_recovery = true;
945 break;
946 }
947
948 /* Check to see if we've tried the max voltage */
949 for (i = 0; i < dp_priv->lane_count; i++)
950 if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
951 break;
952 if (i == dp_priv->lane_count)
953 break;
954
955 /* Check to see if we've tried the same voltage 5 times */
956 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
957 ++tries;
958 if (tries == 5)
959 break;
960 } else
961 tries = 0;
962 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
963
964 /* Compute new train_set as requested by target */
965 intel_get_adjust_train(intel_output, link_status, dp_priv->lane_count, train_set);
966 }
967
968 /* channel equalization */
969 tries = 0;
970 channel_eq = false;
971 for (;;) {
972 /* Use train_set[0] to set the voltage and pre emphasis values */
973 uint32_t signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
974 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
975
976 /* channel eq pattern */
977 if (!intel_dp_set_link_train(intel_output, DP | DP_LINK_TRAIN_PAT_2,
978 DP_TRAINING_PATTERN_2, train_set,
979 false))
980 break;
981
982 udelay(400);
983 if (!intel_dp_get_link_status(intel_output, link_status))
984 break;
985
986 if (intel_channel_eq_ok(link_status, dp_priv->lane_count)) {
987 channel_eq = true;
988 break;
989 }
990
991 /* Try 5 times */
992 if (tries > 5)
993 break;
994
995 /* Compute new train_set as requested by target */
996 intel_get_adjust_train(intel_output, link_status, dp_priv->lane_count, train_set);
997 ++tries;
998 }
999
1000 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_OFF);
1001 POSTING_READ(dp_priv->output_reg);
1002 intel_dp_aux_native_write_1(intel_output,
1003 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1004 }
1005
1006 static void
1007 intel_dp_link_down(struct intel_output *intel_output, uint32_t DP)
1008 {
1009 struct drm_device *dev = intel_output->base.dev;
1010 struct drm_i915_private *dev_priv = dev->dev_private;
1011 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1012
1013 DRM_DEBUG("\n");
1014
1015 if (IS_eDP(intel_output)) {
1016 DP &= ~DP_PLL_ENABLE;
1017 I915_WRITE(dp_priv->output_reg, DP);
1018 POSTING_READ(dp_priv->output_reg);
1019 udelay(100);
1020 }
1021
1022 DP &= ~DP_LINK_TRAIN_MASK;
1023 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1024 POSTING_READ(dp_priv->output_reg);
1025
1026 udelay(17000);
1027
1028 if (IS_eDP(intel_output))
1029 DP |= DP_LINK_TRAIN_OFF;
1030 I915_WRITE(dp_priv->output_reg, DP & ~DP_PORT_EN);
1031 POSTING_READ(dp_priv->output_reg);
1032 }
1033
1034 static void
1035 intel_dp_restore(struct drm_connector *connector)
1036 {
1037 struct intel_output *intel_output = to_intel_output(connector);
1038 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1039
1040 if (dp_priv->save_DP & DP_PORT_EN)
1041 intel_dp_link_train(intel_output, dp_priv->save_DP, dp_priv->save_link_configuration);
1042 else
1043 intel_dp_link_down(intel_output, dp_priv->save_DP);
1044 }
1045
1046 /*
1047 * According to DP spec
1048 * 5.1.2:
1049 * 1. Read DPCD
1050 * 2. Configure link according to Receiver Capabilities
1051 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1052 * 4. Check link status on receipt of hot-plug interrupt
1053 */
1054
1055 static void
1056 intel_dp_check_link_status(struct intel_output *intel_output)
1057 {
1058 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1059 uint8_t link_status[DP_LINK_STATUS_SIZE];
1060
1061 if (!intel_output->enc.crtc)
1062 return;
1063
1064 if (!intel_dp_get_link_status(intel_output, link_status)) {
1065 intel_dp_link_down(intel_output, dp_priv->DP);
1066 return;
1067 }
1068
1069 if (!intel_channel_eq_ok(link_status, dp_priv->lane_count))
1070 intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration);
1071 }
1072
1073 static enum drm_connector_status
1074 igdng_dp_detect(struct drm_connector *connector)
1075 {
1076 struct intel_output *intel_output = to_intel_output(connector);
1077 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1078 enum drm_connector_status status;
1079
1080 status = connector_status_disconnected;
1081 if (intel_dp_aux_native_read(intel_output,
1082 0x000, dp_priv->dpcd,
1083 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1084 {
1085 if (dp_priv->dpcd[0] != 0)
1086 status = connector_status_connected;
1087 }
1088 return status;
1089 }
1090
1091 /**
1092 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1093 *
1094 * \return true if DP port is connected.
1095 * \return false if DP port is disconnected.
1096 */
1097 static enum drm_connector_status
1098 intel_dp_detect(struct drm_connector *connector)
1099 {
1100 struct intel_output *intel_output = to_intel_output(connector);
1101 struct drm_device *dev = intel_output->base.dev;
1102 struct drm_i915_private *dev_priv = dev->dev_private;
1103 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1104 uint32_t temp, bit;
1105 enum drm_connector_status status;
1106
1107 dp_priv->has_audio = false;
1108
1109 if (IS_IGDNG(dev))
1110 return igdng_dp_detect(connector);
1111
1112 temp = I915_READ(PORT_HOTPLUG_EN);
1113
1114 I915_WRITE(PORT_HOTPLUG_EN,
1115 temp |
1116 DPB_HOTPLUG_INT_EN |
1117 DPC_HOTPLUG_INT_EN |
1118 DPD_HOTPLUG_INT_EN);
1119
1120 POSTING_READ(PORT_HOTPLUG_EN);
1121
1122 switch (dp_priv->output_reg) {
1123 case DP_B:
1124 bit = DPB_HOTPLUG_INT_STATUS;
1125 break;
1126 case DP_C:
1127 bit = DPC_HOTPLUG_INT_STATUS;
1128 break;
1129 case DP_D:
1130 bit = DPD_HOTPLUG_INT_STATUS;
1131 break;
1132 default:
1133 return connector_status_unknown;
1134 }
1135
1136 temp = I915_READ(PORT_HOTPLUG_STAT);
1137
1138 if ((temp & bit) == 0)
1139 return connector_status_disconnected;
1140
1141 status = connector_status_disconnected;
1142 if (intel_dp_aux_native_read(intel_output,
1143 0x000, dp_priv->dpcd,
1144 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1145 {
1146 if (dp_priv->dpcd[0] != 0)
1147 status = connector_status_connected;
1148 }
1149 return status;
1150 }
1151
1152 static int intel_dp_get_modes(struct drm_connector *connector)
1153 {
1154 struct intel_output *intel_output = to_intel_output(connector);
1155 struct drm_device *dev = intel_output->base.dev;
1156 struct drm_i915_private *dev_priv = dev->dev_private;
1157 int ret;
1158
1159 /* We should parse the EDID data and find out if it has an audio sink
1160 */
1161
1162 ret = intel_ddc_get_modes(intel_output);
1163 if (ret)
1164 return ret;
1165
1166 /* if eDP has no EDID, try to use fixed panel mode from VBT */
1167 if (IS_eDP(intel_output)) {
1168 if (dev_priv->panel_fixed_mode != NULL) {
1169 struct drm_display_mode *mode;
1170 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1171 drm_mode_probed_add(connector, mode);
1172 return 1;
1173 }
1174 }
1175 return 0;
1176 }
1177
1178 static void
1179 intel_dp_destroy (struct drm_connector *connector)
1180 {
1181 struct intel_output *intel_output = to_intel_output(connector);
1182
1183 if (intel_output->i2c_bus)
1184 intel_i2c_destroy(intel_output->i2c_bus);
1185 drm_sysfs_connector_remove(connector);
1186 drm_connector_cleanup(connector);
1187 kfree(intel_output);
1188 }
1189
1190 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1191 .dpms = intel_dp_dpms,
1192 .mode_fixup = intel_dp_mode_fixup,
1193 .prepare = intel_encoder_prepare,
1194 .mode_set = intel_dp_mode_set,
1195 .commit = intel_encoder_commit,
1196 };
1197
1198 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1199 .dpms = drm_helper_connector_dpms,
1200 .save = intel_dp_save,
1201 .restore = intel_dp_restore,
1202 .detect = intel_dp_detect,
1203 .fill_modes = drm_helper_probe_single_connector_modes,
1204 .destroy = intel_dp_destroy,
1205 };
1206
1207 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1208 .get_modes = intel_dp_get_modes,
1209 .mode_valid = intel_dp_mode_valid,
1210 .best_encoder = intel_best_encoder,
1211 };
1212
1213 static void intel_dp_enc_destroy(struct drm_encoder *encoder)
1214 {
1215 drm_encoder_cleanup(encoder);
1216 }
1217
1218 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1219 .destroy = intel_dp_enc_destroy,
1220 };
1221
1222 void
1223 intel_dp_hot_plug(struct intel_output *intel_output)
1224 {
1225 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1226
1227 if (dp_priv->dpms_mode == DRM_MODE_DPMS_ON)
1228 intel_dp_check_link_status(intel_output);
1229 }
1230
1231 void
1232 intel_dp_init(struct drm_device *dev, int output_reg)
1233 {
1234 struct drm_i915_private *dev_priv = dev->dev_private;
1235 struct drm_connector *connector;
1236 struct intel_output *intel_output;
1237 struct intel_dp_priv *dp_priv;
1238 const char *name = NULL;
1239
1240 intel_output = kcalloc(sizeof(struct intel_output) +
1241 sizeof(struct intel_dp_priv), 1, GFP_KERNEL);
1242 if (!intel_output)
1243 return;
1244
1245 dp_priv = (struct intel_dp_priv *)(intel_output + 1);
1246
1247 connector = &intel_output->base;
1248 drm_connector_init(dev, connector, &intel_dp_connector_funcs,
1249 DRM_MODE_CONNECTOR_DisplayPort);
1250 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1251
1252 if (output_reg == DP_A)
1253 intel_output->type = INTEL_OUTPUT_EDP;
1254 else
1255 intel_output->type = INTEL_OUTPUT_DISPLAYPORT;
1256
1257 if (output_reg == DP_B)
1258 intel_output->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
1259 else if (output_reg == DP_C)
1260 intel_output->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
1261 else if (output_reg == DP_D)
1262 intel_output->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1263
1264 if (IS_eDP(intel_output)) {
1265 intel_output->crtc_mask = (1 << 1);
1266 intel_output->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
1267 } else
1268 intel_output->crtc_mask = (1 << 0) | (1 << 1);
1269 connector->interlace_allowed = true;
1270 connector->doublescan_allowed = 0;
1271
1272 dp_priv->intel_output = intel_output;
1273 dp_priv->output_reg = output_reg;
1274 dp_priv->has_audio = false;
1275 dp_priv->dpms_mode = DRM_MODE_DPMS_ON;
1276 intel_output->dev_priv = dp_priv;
1277
1278 drm_encoder_init(dev, &intel_output->enc, &intel_dp_enc_funcs,
1279 DRM_MODE_ENCODER_TMDS);
1280 drm_encoder_helper_add(&intel_output->enc, &intel_dp_helper_funcs);
1281
1282 drm_mode_connector_attach_encoder(&intel_output->base,
1283 &intel_output->enc);
1284 drm_sysfs_connector_add(connector);
1285
1286 /* Set up the DDC bus. */
1287 switch (output_reg) {
1288 case DP_A:
1289 name = "DPDDC-A";
1290 break;
1291 case DP_B:
1292 case PCH_DP_B:
1293 name = "DPDDC-B";
1294 break;
1295 case DP_C:
1296 case PCH_DP_C:
1297 name = "DPDDC-C";
1298 break;
1299 case DP_D:
1300 case PCH_DP_D:
1301 name = "DPDDC-D";
1302 break;
1303 }
1304
1305 intel_dp_i2c_init(intel_output, name);
1306
1307 intel_output->ddc_bus = &dp_priv->adapter;
1308 intel_output->hot_plug = intel_dp_hot_plug;
1309
1310 if (output_reg == DP_A) {
1311 /* initialize panel mode from VBT if available for eDP */
1312 if (dev_priv->lfp_lvds_vbt_mode) {
1313 dev_priv->panel_fixed_mode =
1314 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1315 if (dev_priv->panel_fixed_mode) {
1316 dev_priv->panel_fixed_mode->type |=
1317 DRM_MODE_TYPE_PREFERRED;
1318 }
1319 }
1320 }
1321
1322 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1323 * 0xd. Failure to do so will result in spurious interrupts being
1324 * generated on the port when a cable is not attached.
1325 */
1326 if (IS_G4X(dev) && !IS_GM45(dev)) {
1327 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1328 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1329 }
1330 }
Linux for Ginger Game Console