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Full support for Ginger Console
[linux-ginger.git] / drivers / gpu / drm / radeon / r100.c
blob161094c07d9443957b8f193386e28db258244620
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/seq_file.h>
29 #include "drmP.h"
30 #include "drm.h"
31 #include "radeon_drm.h"
32 #include "radeon_reg.h"
33 #include "radeon.h"
34 #include "r100d.h"
35 #include "rs100d.h"
36 #include "rv200d.h"
37 #include "rv250d.h"
38
39 #include <linux/firmware.h>
40 #include <linux/platform_device.h>
41
42 #include "r100_reg_safe.h"
43 #include "rn50_reg_safe.h"
44
45 /* Firmware Names */
46 #define FIRMWARE_R100 "radeon/R100_cp.bin"
47 #define FIRMWARE_R200 "radeon/R200_cp.bin"
48 #define FIRMWARE_R300 "radeon/R300_cp.bin"
49 #define FIRMWARE_R420 "radeon/R420_cp.bin"
50 #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
51 #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
52 #define FIRMWARE_R520 "radeon/R520_cp.bin"
53
54 MODULE_FIRMWARE(FIRMWARE_R100);
55 MODULE_FIRMWARE(FIRMWARE_R200);
56 MODULE_FIRMWARE(FIRMWARE_R300);
57 MODULE_FIRMWARE(FIRMWARE_R420);
58 MODULE_FIRMWARE(FIRMWARE_RS690);
59 MODULE_FIRMWARE(FIRMWARE_RS600);
60 MODULE_FIRMWARE(FIRMWARE_R520);
61
62 #include "r100_track.h"
63
64 /* This files gather functions specifics to:
65 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
66 */
67
68 /*
69 * PCI GART
70 */
71 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
72 {
73 /* TODO: can we do somethings here ? */
74 /* It seems hw only cache one entry so we should discard this
75 * entry otherwise if first GPU GART read hit this entry it
76 * could end up in wrong address. */
77 }
78
79 int r100_pci_gart_init(struct radeon_device *rdev)
80 {
81 int r;
82
83 if (rdev->gart.table.ram.ptr) {
84 WARN(1, "R100 PCI GART already initialized.\n");
85 return 0;
86 }
87 /* Initialize common gart structure */
88 r = radeon_gart_init(rdev);
89 if (r)
90 return r;
91 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
92 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
93 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
94 return radeon_gart_table_ram_alloc(rdev);
95 }
96
97 int r100_pci_gart_enable(struct radeon_device *rdev)
98 {
99 uint32_t tmp;
100
101 /* discard memory request outside of configured range */
102 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
103 WREG32(RADEON_AIC_CNTL, tmp);
104 /* set address range for PCI address translate */
105 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location);
106 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
107 WREG32(RADEON_AIC_HI_ADDR, tmp);
108 /* Enable bus mastering */
109 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
110 WREG32(RADEON_BUS_CNTL, tmp);
111 /* set PCI GART page-table base address */
112 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
113 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
114 WREG32(RADEON_AIC_CNTL, tmp);
115 r100_pci_gart_tlb_flush(rdev);
116 rdev->gart.ready = true;
117 return 0;
118 }
119
120 void r100_pci_gart_disable(struct radeon_device *rdev)
121 {
122 uint32_t tmp;
123
124 /* discard memory request outside of configured range */
125 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
126 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
127 WREG32(RADEON_AIC_LO_ADDR, 0);
128 WREG32(RADEON_AIC_HI_ADDR, 0);
129 }
130
131 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
132 {
133 if (i < 0 || i > rdev->gart.num_gpu_pages) {
134 return -EINVAL;
135 }
136 rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
137 return 0;
138 }
139
140 void r100_pci_gart_fini(struct radeon_device *rdev)
141 {
142 r100_pci_gart_disable(rdev);
143 radeon_gart_table_ram_free(rdev);
144 radeon_gart_fini(rdev);
145 }
146
147 int r100_irq_set(struct radeon_device *rdev)
148 {
149 uint32_t tmp = 0;
150
151 if (rdev->irq.sw_int) {
152 tmp |= RADEON_SW_INT_ENABLE;
153 }
154 if (rdev->irq.crtc_vblank_int[0]) {
155 tmp |= RADEON_CRTC_VBLANK_MASK;
156 }
157 if (rdev->irq.crtc_vblank_int[1]) {
158 tmp |= RADEON_CRTC2_VBLANK_MASK;
159 }
160 WREG32(RADEON_GEN_INT_CNTL, tmp);
161 return 0;
162 }
163
164 void r100_irq_disable(struct radeon_device *rdev)
165 {
166 u32 tmp;
167
168 WREG32(R_000040_GEN_INT_CNTL, 0);
169 /* Wait and acknowledge irq */
170 mdelay(1);
171 tmp = RREG32(R_000044_GEN_INT_STATUS);
172 WREG32(R_000044_GEN_INT_STATUS, tmp);
173 }
174
175 static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
176 {
177 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
178 uint32_t irq_mask = RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT |
179 RADEON_CRTC2_VBLANK_STAT;
180
181 if (irqs) {
182 WREG32(RADEON_GEN_INT_STATUS, irqs);
183 }
184 return irqs & irq_mask;
185 }
186
187 int r100_irq_process(struct radeon_device *rdev)
188 {
189 uint32_t status;
190
191 status = r100_irq_ack(rdev);
192 if (!status) {
193 return IRQ_NONE;
194 }
195 if (rdev->shutdown) {
196 return IRQ_NONE;
197 }
198 while (status) {
199 /* SW interrupt */
200 if (status & RADEON_SW_INT_TEST) {
201 radeon_fence_process(rdev);
202 }
203 /* Vertical blank interrupts */
204 if (status & RADEON_CRTC_VBLANK_STAT) {
205 drm_handle_vblank(rdev->ddev, 0);
206 }
207 if (status & RADEON_CRTC2_VBLANK_STAT) {
208 drm_handle_vblank(rdev->ddev, 1);
209 }
210 status = r100_irq_ack(rdev);
211 }
212 return IRQ_HANDLED;
213 }
214
215 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
216 {
217 if (crtc == 0)
218 return RREG32(RADEON_CRTC_CRNT_FRAME);
219 else
220 return RREG32(RADEON_CRTC2_CRNT_FRAME);
221 }
222
223 void r100_fence_ring_emit(struct radeon_device *rdev,
224 struct radeon_fence *fence)
225 {
226 /* Who ever call radeon_fence_emit should call ring_lock and ask
227 * for enough space (today caller are ib schedule and buffer move) */
228 /* Wait until IDLE & CLEAN */
229 radeon_ring_write(rdev, PACKET0(0x1720, 0));
230 radeon_ring_write(rdev, (1 << 16) | (1 << 17));
231 /* Emit fence sequence & fire IRQ */
232 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
233 radeon_ring_write(rdev, fence->seq);
234 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
235 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
236 }
237
238 int r100_wb_init(struct radeon_device *rdev)
239 {
240 int r;
241
242 if (rdev->wb.wb_obj == NULL) {
243 r = radeon_object_create(rdev, NULL, 4096,
244 true,
245 RADEON_GEM_DOMAIN_GTT,
246 false, &rdev->wb.wb_obj);
247 if (r) {
248 DRM_ERROR("radeon: failed to create WB buffer (%d).\n", r);
249 return r;
250 }
251 r = radeon_object_pin(rdev->wb.wb_obj,
252 RADEON_GEM_DOMAIN_GTT,
253 &rdev->wb.gpu_addr);
254 if (r) {
255 DRM_ERROR("radeon: failed to pin WB buffer (%d).\n", r);
256 return r;
257 }
258 r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
259 if (r) {
260 DRM_ERROR("radeon: failed to map WB buffer (%d).\n", r);
261 return r;
262 }
263 }
264 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
265 WREG32(R_00070C_CP_RB_RPTR_ADDR,
266 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
267 WREG32(R_000770_SCRATCH_UMSK, 0xff);
268 return 0;
269 }
270
271 void r100_wb_disable(struct radeon_device *rdev)
272 {
273 WREG32(R_000770_SCRATCH_UMSK, 0);
274 }
275
276 void r100_wb_fini(struct radeon_device *rdev)
277 {
278 r100_wb_disable(rdev);
279 if (rdev->wb.wb_obj) {
280 radeon_object_kunmap(rdev->wb.wb_obj);
281 radeon_object_unpin(rdev->wb.wb_obj);
282 radeon_object_unref(&rdev->wb.wb_obj);
283 rdev->wb.wb = NULL;
284 rdev->wb.wb_obj = NULL;
285 }
286 }
287
288 int r100_copy_blit(struct radeon_device *rdev,
289 uint64_t src_offset,
290 uint64_t dst_offset,
291 unsigned num_pages,
292 struct radeon_fence *fence)
293 {
294 uint32_t cur_pages;
295 uint32_t stride_bytes = PAGE_SIZE;
296 uint32_t pitch;
297 uint32_t stride_pixels;
298 unsigned ndw;
299 int num_loops;
300 int r = 0;
301
302 /* radeon limited to 16k stride */
303 stride_bytes &= 0x3fff;
304 /* radeon pitch is /64 */
305 pitch = stride_bytes / 64;
306 stride_pixels = stride_bytes / 4;
307 num_loops = DIV_ROUND_UP(num_pages, 8191);
308
309 /* Ask for enough room for blit + flush + fence */
310 ndw = 64 + (10 * num_loops);
311 r = radeon_ring_lock(rdev, ndw);
312 if (r) {
313 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
314 return -EINVAL;
315 }
316 while (num_pages > 0) {
317 cur_pages = num_pages;
318 if (cur_pages > 8191) {
319 cur_pages = 8191;
320 }
321 num_pages -= cur_pages;
322
323 /* pages are in Y direction - height
324 page width in X direction - width */
325 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
326 radeon_ring_write(rdev,
327 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
328 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
329 RADEON_GMC_SRC_CLIPPING |
330 RADEON_GMC_DST_CLIPPING |
331 RADEON_GMC_BRUSH_NONE |
332 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
333 RADEON_GMC_SRC_DATATYPE_COLOR |
334 RADEON_ROP3_S |
335 RADEON_DP_SRC_SOURCE_MEMORY |
336 RADEON_GMC_CLR_CMP_CNTL_DIS |
337 RADEON_GMC_WR_MSK_DIS);
338 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
339 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
340 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
341 radeon_ring_write(rdev, 0);
342 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
343 radeon_ring_write(rdev, num_pages);
344 radeon_ring_write(rdev, num_pages);
345 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
346 }
347 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
348 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
349 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
350 radeon_ring_write(rdev,
351 RADEON_WAIT_2D_IDLECLEAN |
352 RADEON_WAIT_HOST_IDLECLEAN |
353 RADEON_WAIT_DMA_GUI_IDLE);
354 if (fence) {
355 r = radeon_fence_emit(rdev, fence);
356 }
357 radeon_ring_unlock_commit(rdev);
358 return r;
359 }
360
361 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
362 {
363 unsigned i;
364 u32 tmp;
365
366 for (i = 0; i < rdev->usec_timeout; i++) {
367 tmp = RREG32(R_000E40_RBBM_STATUS);
368 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
369 return 0;
370 }
371 udelay(1);
372 }
373 return -1;
374 }
375
376 void r100_ring_start(struct radeon_device *rdev)
377 {
378 int r;
379
380 r = radeon_ring_lock(rdev, 2);
381 if (r) {
382 return;
383 }
384 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
385 radeon_ring_write(rdev,
386 RADEON_ISYNC_ANY2D_IDLE3D |
387 RADEON_ISYNC_ANY3D_IDLE2D |
388 RADEON_ISYNC_WAIT_IDLEGUI |
389 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
390 radeon_ring_unlock_commit(rdev);
391 }
392
393
394 /* Load the microcode for the CP */
395 static int r100_cp_init_microcode(struct radeon_device *rdev)
396 {
397 struct platform_device *pdev;
398 const char *fw_name = NULL;
399 int err;
400
401 DRM_DEBUG("\n");
402
403 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
404 err = IS_ERR(pdev);
405 if (err) {
406 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
407 return -EINVAL;
408 }
409 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
410 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
411 (rdev->family == CHIP_RS200)) {
412 DRM_INFO("Loading R100 Microcode\n");
413 fw_name = FIRMWARE_R100;
414 } else if ((rdev->family == CHIP_R200) ||
415 (rdev->family == CHIP_RV250) ||
416 (rdev->family == CHIP_RV280) ||
417 (rdev->family == CHIP_RS300)) {
418 DRM_INFO("Loading R200 Microcode\n");
419 fw_name = FIRMWARE_R200;
420 } else if ((rdev->family == CHIP_R300) ||
421 (rdev->family == CHIP_R350) ||
422 (rdev->family == CHIP_RV350) ||
423 (rdev->family == CHIP_RV380) ||
424 (rdev->family == CHIP_RS400) ||
425 (rdev->family == CHIP_RS480)) {
426 DRM_INFO("Loading R300 Microcode\n");
427 fw_name = FIRMWARE_R300;
428 } else if ((rdev->family == CHIP_R420) ||
429 (rdev->family == CHIP_R423) ||
430 (rdev->family == CHIP_RV410)) {
431 DRM_INFO("Loading R400 Microcode\n");
432 fw_name = FIRMWARE_R420;
433 } else if ((rdev->family == CHIP_RS690) ||
434 (rdev->family == CHIP_RS740)) {
435 DRM_INFO("Loading RS690/RS740 Microcode\n");
436 fw_name = FIRMWARE_RS690;
437 } else if (rdev->family == CHIP_RS600) {
438 DRM_INFO("Loading RS600 Microcode\n");
439 fw_name = FIRMWARE_RS600;
440 } else if ((rdev->family == CHIP_RV515) ||
441 (rdev->family == CHIP_R520) ||
442 (rdev->family == CHIP_RV530) ||
443 (rdev->family == CHIP_R580) ||
444 (rdev->family == CHIP_RV560) ||
445 (rdev->family == CHIP_RV570)) {
446 DRM_INFO("Loading R500 Microcode\n");
447 fw_name = FIRMWARE_R520;
448 }
449
450 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
451 platform_device_unregister(pdev);
452 if (err) {
453 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
454 fw_name);
455 } else if (rdev->me_fw->size % 8) {
456 printk(KERN_ERR
457 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
458 rdev->me_fw->size, fw_name);
459 err = -EINVAL;
460 release_firmware(rdev->me_fw);
461 rdev->me_fw = NULL;
462 }
463 return err;
464 }
465
466 static void r100_cp_load_microcode(struct radeon_device *rdev)
467 {
468 const __be32 *fw_data;
469 int i, size;
470
471 if (r100_gui_wait_for_idle(rdev)) {
472 printk(KERN_WARNING "Failed to wait GUI idle while "
473 "programming pipes. Bad things might happen.\n");
474 }
475
476 if (rdev->me_fw) {
477 size = rdev->me_fw->size / 4;
478 fw_data = (const __be32 *)&rdev->me_fw->data[0];
479 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
480 for (i = 0; i < size; i += 2) {
481 WREG32(RADEON_CP_ME_RAM_DATAH,
482 be32_to_cpup(&fw_data[i]));
483 WREG32(RADEON_CP_ME_RAM_DATAL,
484 be32_to_cpup(&fw_data[i + 1]));
485 }
486 }
487 }
488
489 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
490 {
491 unsigned rb_bufsz;
492 unsigned rb_blksz;
493 unsigned max_fetch;
494 unsigned pre_write_timer;
495 unsigned pre_write_limit;
496 unsigned indirect2_start;
497 unsigned indirect1_start;
498 uint32_t tmp;
499 int r;
500
501 if (r100_debugfs_cp_init(rdev)) {
502 DRM_ERROR("Failed to register debugfs file for CP !\n");
503 }
504 /* Reset CP */
505 tmp = RREG32(RADEON_CP_CSQ_STAT);
506 if ((tmp & (1 << 31))) {
507 DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
508 WREG32(RADEON_CP_CSQ_MODE, 0);
509 WREG32(RADEON_CP_CSQ_CNTL, 0);
510 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
511 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
512 mdelay(2);
513 WREG32(RADEON_RBBM_SOFT_RESET, 0);
514 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
515 mdelay(2);
516 tmp = RREG32(RADEON_CP_CSQ_STAT);
517 if ((tmp & (1 << 31))) {
518 DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
519 }
520 } else {
521 DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
522 }
523
524 if (!rdev->me_fw) {
525 r = r100_cp_init_microcode(rdev);
526 if (r) {
527 DRM_ERROR("Failed to load firmware!\n");
528 return r;
529 }
530 }
531
532 /* Align ring size */
533 rb_bufsz = drm_order(ring_size / 8);
534 ring_size = (1 << (rb_bufsz + 1)) * 4;
535 r100_cp_load_microcode(rdev);
536 r = radeon_ring_init(rdev, ring_size);
537 if (r) {
538 return r;
539 }
540 /* Each time the cp read 1024 bytes (16 dword/quadword) update
541 * the rptr copy in system ram */
542 rb_blksz = 9;
543 /* cp will read 128bytes at a time (4 dwords) */
544 max_fetch = 1;
545 rdev->cp.align_mask = 16 - 1;
546 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
547 pre_write_timer = 64;
548 /* Force CP_RB_WPTR write if written more than one time before the
549 * delay expire
550 */
551 pre_write_limit = 0;
552 /* Setup the cp cache like this (cache size is 96 dwords) :
553 * RING 0 to 15
554 * INDIRECT1 16 to 79
555 * INDIRECT2 80 to 95
556 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
557 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
558 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
559 * Idea being that most of the gpu cmd will be through indirect1 buffer
560 * so it gets the bigger cache.
561 */
562 indirect2_start = 80;
563 indirect1_start = 16;
564 /* cp setup */
565 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
566 WREG32(RADEON_CP_RB_CNTL,
567 #ifdef __BIG_ENDIAN
568 RADEON_BUF_SWAP_32BIT |
569 #endif
570 REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
571 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
572 REG_SET(RADEON_MAX_FETCH, max_fetch) |
573 RADEON_RB_NO_UPDATE);
574 /* Set ring address */
575 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
576 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
577 /* Force read & write ptr to 0 */
578 tmp = RREG32(RADEON_CP_RB_CNTL);
579 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
580 WREG32(RADEON_CP_RB_RPTR_WR, 0);
581 WREG32(RADEON_CP_RB_WPTR, 0);
582 WREG32(RADEON_CP_RB_CNTL, tmp);
583 udelay(10);
584 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
585 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
586 /* Set cp mode to bus mastering & enable cp*/
587 WREG32(RADEON_CP_CSQ_MODE,
588 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
589 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
590 WREG32(0x718, 0);
591 WREG32(0x744, 0x00004D4D);
592 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
593 radeon_ring_start(rdev);
594 r = radeon_ring_test(rdev);
595 if (r) {
596 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
597 return r;
598 }
599 rdev->cp.ready = true;
600 return 0;
601 }
602
603 void r100_cp_fini(struct radeon_device *rdev)
604 {
605 if (r100_cp_wait_for_idle(rdev)) {
606 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
607 }
608 /* Disable ring */
609 r100_cp_disable(rdev);
610 radeon_ring_fini(rdev);
611 DRM_INFO("radeon: cp finalized\n");
612 }
613
614 void r100_cp_disable(struct radeon_device *rdev)
615 {
616 /* Disable ring */
617 rdev->cp.ready = false;
618 WREG32(RADEON_CP_CSQ_MODE, 0);
619 WREG32(RADEON_CP_CSQ_CNTL, 0);
620 if (r100_gui_wait_for_idle(rdev)) {
621 printk(KERN_WARNING "Failed to wait GUI idle while "
622 "programming pipes. Bad things might happen.\n");
623 }
624 }
625
626 int r100_cp_reset(struct radeon_device *rdev)
627 {
628 uint32_t tmp;
629 bool reinit_cp;
630 int i;
631
632 reinit_cp = rdev->cp.ready;
633 rdev->cp.ready = false;
634 WREG32(RADEON_CP_CSQ_MODE, 0);
635 WREG32(RADEON_CP_CSQ_CNTL, 0);
636 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
637 (void)RREG32(RADEON_RBBM_SOFT_RESET);
638 udelay(200);
639 WREG32(RADEON_RBBM_SOFT_RESET, 0);
640 /* Wait to prevent race in RBBM_STATUS */
641 mdelay(1);
642 for (i = 0; i < rdev->usec_timeout; i++) {
643 tmp = RREG32(RADEON_RBBM_STATUS);
644 if (!(tmp & (1 << 16))) {
645 DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
646 tmp);
647 if (reinit_cp) {
648 return r100_cp_init(rdev, rdev->cp.ring_size);
649 }
650 return 0;
651 }
652 DRM_UDELAY(1);
653 }
654 tmp = RREG32(RADEON_RBBM_STATUS);
655 DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
656 return -1;
657 }
658
659 void r100_cp_commit(struct radeon_device *rdev)
660 {
661 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
662 (void)RREG32(RADEON_CP_RB_WPTR);
663 }
664
665
666 /*
667 * CS functions
668 */
669 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
670 struct radeon_cs_packet *pkt,
671 const unsigned *auth, unsigned n,
672 radeon_packet0_check_t check)
673 {
674 unsigned reg;
675 unsigned i, j, m;
676 unsigned idx;
677 int r;
678
679 idx = pkt->idx + 1;
680 reg = pkt->reg;
681 /* Check that register fall into register range
682 * determined by the number of entry (n) in the
683 * safe register bitmap.
684 */
685 if (pkt->one_reg_wr) {
686 if ((reg >> 7) > n) {
687 return -EINVAL;
688 }
689 } else {
690 if (((reg + (pkt->count << 2)) >> 7) > n) {
691 return -EINVAL;
692 }
693 }
694 for (i = 0; i <= pkt->count; i++, idx++) {
695 j = (reg >> 7);
696 m = 1 << ((reg >> 2) & 31);
697 if (auth[j] & m) {
698 r = check(p, pkt, idx, reg);
699 if (r) {
700 return r;
701 }
702 }
703 if (pkt->one_reg_wr) {
704 if (!(auth[j] & m)) {
705 break;
706 }
707 } else {
708 reg += 4;
709 }
710 }
711 return 0;
712 }
713
714 void r100_cs_dump_packet(struct radeon_cs_parser *p,
715 struct radeon_cs_packet *pkt)
716 {
717 volatile uint32_t *ib;
718 unsigned i;
719 unsigned idx;
720
721 ib = p->ib->ptr;
722 idx = pkt->idx;
723 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
724 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
725 }
726 }
727
728 /**
729 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
730 * @parser: parser structure holding parsing context.
731 * @pkt: where to store packet informations
732 *
733 * Assume that chunk_ib_index is properly set. Will return -EINVAL
734 * if packet is bigger than remaining ib size. or if packets is unknown.
735 **/
736 int r100_cs_packet_parse(struct radeon_cs_parser *p,
737 struct radeon_cs_packet *pkt,
738 unsigned idx)
739 {
740 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
741 uint32_t header;
742
743 if (idx >= ib_chunk->length_dw) {
744 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
745 idx, ib_chunk->length_dw);
746 return -EINVAL;
747 }
748 header = radeon_get_ib_value(p, idx);
749 pkt->idx = idx;
750 pkt->type = CP_PACKET_GET_TYPE(header);
751 pkt->count = CP_PACKET_GET_COUNT(header);
752 switch (pkt->type) {
753 case PACKET_TYPE0:
754 pkt->reg = CP_PACKET0_GET_REG(header);
755 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
756 break;
757 case PACKET_TYPE3:
758 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
759 break;
760 case PACKET_TYPE2:
761 pkt->count = -1;
762 break;
763 default:
764 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
765 return -EINVAL;
766 }
767 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
768 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
769 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
770 return -EINVAL;
771 }
772 return 0;
773 }
774
775 /**
776 * r100_cs_packet_next_vline() - parse userspace VLINE packet
777 * @parser: parser structure holding parsing context.
778 *
779 * Userspace sends a special sequence for VLINE waits.
780 * PACKET0 - VLINE_START_END + value
781 * PACKET0 - WAIT_UNTIL +_value
782 * RELOC (P3) - crtc_id in reloc.
783 *
784 * This function parses this and relocates the VLINE START END
785 * and WAIT UNTIL packets to the correct crtc.
786 * It also detects a switched off crtc and nulls out the
787 * wait in that case.
788 */
789 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
790 {
791 struct drm_mode_object *obj;
792 struct drm_crtc *crtc;
793 struct radeon_crtc *radeon_crtc;
794 struct radeon_cs_packet p3reloc, waitreloc;
795 int crtc_id;
796 int r;
797 uint32_t header, h_idx, reg;
798 volatile uint32_t *ib;
799
800 ib = p->ib->ptr;
801
802 /* parse the wait until */
803 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
804 if (r)
805 return r;
806
807 /* check its a wait until and only 1 count */
808 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
809 waitreloc.count != 0) {
810 DRM_ERROR("vline wait had illegal wait until segment\n");
811 r = -EINVAL;
812 return r;
813 }
814
815 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
816 DRM_ERROR("vline wait had illegal wait until\n");
817 r = -EINVAL;
818 return r;
819 }
820
821 /* jump over the NOP */
822 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
823 if (r)
824 return r;
825
826 h_idx = p->idx - 2;
827 p->idx += waitreloc.count + 2;
828 p->idx += p3reloc.count + 2;
829
830 header = radeon_get_ib_value(p, h_idx);
831 crtc_id = radeon_get_ib_value(p, h_idx + 5);
832 reg = CP_PACKET0_GET_REG(header);
833 mutex_lock(&p->rdev->ddev->mode_config.mutex);
834 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
835 if (!obj) {
836 DRM_ERROR("cannot find crtc %d\n", crtc_id);
837 r = -EINVAL;
838 goto out;
839 }
840 crtc = obj_to_crtc(obj);
841 radeon_crtc = to_radeon_crtc(crtc);
842 crtc_id = radeon_crtc->crtc_id;
843
844 if (!crtc->enabled) {
845 /* if the CRTC isn't enabled - we need to nop out the wait until */
846 ib[h_idx + 2] = PACKET2(0);
847 ib[h_idx + 3] = PACKET2(0);
848 } else if (crtc_id == 1) {
849 switch (reg) {
850 case AVIVO_D1MODE_VLINE_START_END:
851 header &= ~R300_CP_PACKET0_REG_MASK;
852 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
853 break;
854 case RADEON_CRTC_GUI_TRIG_VLINE:
855 header &= ~R300_CP_PACKET0_REG_MASK;
856 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
857 break;
858 default:
859 DRM_ERROR("unknown crtc reloc\n");
860 r = -EINVAL;
861 goto out;
862 }
863 ib[h_idx] = header;
864 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
865 }
866 out:
867 mutex_unlock(&p->rdev->ddev->mode_config.mutex);
868 return r;
869 }
870
871 /**
872 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
873 * @parser: parser structure holding parsing context.
874 * @data: pointer to relocation data
875 * @offset_start: starting offset
876 * @offset_mask: offset mask (to align start offset on)
877 * @reloc: reloc informations
878 *
879 * Check next packet is relocation packet3, do bo validation and compute
880 * GPU offset using the provided start.
881 **/
882 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
883 struct radeon_cs_reloc **cs_reloc)
884 {
885 struct radeon_cs_chunk *relocs_chunk;
886 struct radeon_cs_packet p3reloc;
887 unsigned idx;
888 int r;
889
890 if (p->chunk_relocs_idx == -1) {
891 DRM_ERROR("No relocation chunk !\n");
892 return -EINVAL;
893 }
894 *cs_reloc = NULL;
895 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
896 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
897 if (r) {
898 return r;
899 }
900 p->idx += p3reloc.count + 2;
901 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
902 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
903 p3reloc.idx);
904 r100_cs_dump_packet(p, &p3reloc);
905 return -EINVAL;
906 }
907 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
908 if (idx >= relocs_chunk->length_dw) {
909 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
910 idx, relocs_chunk->length_dw);
911 r100_cs_dump_packet(p, &p3reloc);
912 return -EINVAL;
913 }
914 /* FIXME: we assume reloc size is 4 dwords */
915 *cs_reloc = p->relocs_ptr[(idx / 4)];
916 return 0;
917 }
918
919 static int r100_get_vtx_size(uint32_t vtx_fmt)
920 {
921 int vtx_size;
922 vtx_size = 2;
923 /* ordered according to bits in spec */
924 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
925 vtx_size++;
926 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
927 vtx_size += 3;
928 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
929 vtx_size++;
930 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
931 vtx_size++;
932 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
933 vtx_size += 3;
934 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
935 vtx_size++;
936 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
937 vtx_size++;
938 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
939 vtx_size += 2;
940 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
941 vtx_size += 2;
942 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
943 vtx_size++;
944 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
945 vtx_size += 2;
946 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
947 vtx_size++;
948 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
949 vtx_size += 2;
950 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
951 vtx_size++;
952 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
953 vtx_size++;
954 /* blend weight */
955 if (vtx_fmt & (0x7 << 15))
956 vtx_size += (vtx_fmt >> 15) & 0x7;
957 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
958 vtx_size += 3;
959 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
960 vtx_size += 2;
961 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
962 vtx_size++;
963 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
964 vtx_size++;
965 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
966 vtx_size++;
967 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
968 vtx_size++;
969 return vtx_size;
970 }
971
972 static int r100_packet0_check(struct radeon_cs_parser *p,
973 struct radeon_cs_packet *pkt,
974 unsigned idx, unsigned reg)
975 {
976 struct radeon_cs_reloc *reloc;
977 struct r100_cs_track *track;
978 volatile uint32_t *ib;
979 uint32_t tmp;
980 int r;
981 int i, face;
982 u32 tile_flags = 0;
983 u32 idx_value;
984
985 ib = p->ib->ptr;
986 track = (struct r100_cs_track *)p->track;
987
988 idx_value = radeon_get_ib_value(p, idx);
989
990 switch (reg) {
991 case RADEON_CRTC_GUI_TRIG_VLINE:
992 r = r100_cs_packet_parse_vline(p);
993 if (r) {
994 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
995 idx, reg);
996 r100_cs_dump_packet(p, pkt);
997 return r;
998 }
999 break;
1000 /* FIXME: only allow PACKET3 blit? easier to check for out of
1001 * range access */
1002 case RADEON_DST_PITCH_OFFSET:
1003 case RADEON_SRC_PITCH_OFFSET:
1004 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1005 if (r)
1006 return r;
1007 break;
1008 case RADEON_RB3D_DEPTHOFFSET:
1009 r = r100_cs_packet_next_reloc(p, &reloc);
1010 if (r) {
1011 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1012 idx, reg);
1013 r100_cs_dump_packet(p, pkt);
1014 return r;
1015 }
1016 track->zb.robj = reloc->robj;
1017 track->zb.offset = idx_value;
1018 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1019 break;
1020 case RADEON_RB3D_COLOROFFSET:
1021 r = r100_cs_packet_next_reloc(p, &reloc);
1022 if (r) {
1023 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1024 idx, reg);
1025 r100_cs_dump_packet(p, pkt);
1026 return r;
1027 }
1028 track->cb[0].robj = reloc->robj;
1029 track->cb[0].offset = idx_value;
1030 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1031 break;
1032 case RADEON_PP_TXOFFSET_0:
1033 case RADEON_PP_TXOFFSET_1:
1034 case RADEON_PP_TXOFFSET_2:
1035 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1036 r = r100_cs_packet_next_reloc(p, &reloc);
1037 if (r) {
1038 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1039 idx, reg);
1040 r100_cs_dump_packet(p, pkt);
1041 return r;
1042 }
1043 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1044 track->textures[i].robj = reloc->robj;
1045 break;
1046 case RADEON_PP_CUBIC_OFFSET_T0_0:
1047 case RADEON_PP_CUBIC_OFFSET_T0_1:
1048 case RADEON_PP_CUBIC_OFFSET_T0_2:
1049 case RADEON_PP_CUBIC_OFFSET_T0_3:
1050 case RADEON_PP_CUBIC_OFFSET_T0_4:
1051 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1052 r = r100_cs_packet_next_reloc(p, &reloc);
1053 if (r) {
1054 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1055 idx, reg);
1056 r100_cs_dump_packet(p, pkt);
1057 return r;
1058 }
1059 track->textures[0].cube_info[i].offset = idx_value;
1060 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1061 track->textures[0].cube_info[i].robj = reloc->robj;
1062 break;
1063 case RADEON_PP_CUBIC_OFFSET_T1_0:
1064 case RADEON_PP_CUBIC_OFFSET_T1_1:
1065 case RADEON_PP_CUBIC_OFFSET_T1_2:
1066 case RADEON_PP_CUBIC_OFFSET_T1_3:
1067 case RADEON_PP_CUBIC_OFFSET_T1_4:
1068 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1069 r = r100_cs_packet_next_reloc(p, &reloc);
1070 if (r) {
1071 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1072 idx, reg);
1073 r100_cs_dump_packet(p, pkt);
1074 return r;
1075 }
1076 track->textures[1].cube_info[i].offset = idx_value;
1077 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1078 track->textures[1].cube_info[i].robj = reloc->robj;
1079 break;
1080 case RADEON_PP_CUBIC_OFFSET_T2_0:
1081 case RADEON_PP_CUBIC_OFFSET_T2_1:
1082 case RADEON_PP_CUBIC_OFFSET_T2_2:
1083 case RADEON_PP_CUBIC_OFFSET_T2_3:
1084 case RADEON_PP_CUBIC_OFFSET_T2_4:
1085 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1086 r = r100_cs_packet_next_reloc(p, &reloc);
1087 if (r) {
1088 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1089 idx, reg);
1090 r100_cs_dump_packet(p, pkt);
1091 return r;
1092 }
1093 track->textures[2].cube_info[i].offset = idx_value;
1094 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1095 track->textures[2].cube_info[i].robj = reloc->robj;
1096 break;
1097 case RADEON_RE_WIDTH_HEIGHT:
1098 track->maxy = ((idx_value >> 16) & 0x7FF);
1099 break;
1100 case RADEON_RB3D_COLORPITCH:
1101 r = r100_cs_packet_next_reloc(p, &reloc);
1102 if (r) {
1103 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1104 idx, reg);
1105 r100_cs_dump_packet(p, pkt);
1106 return r;
1107 }
1108
1109 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1110 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1111 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1112 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1113
1114 tmp = idx_value & ~(0x7 << 16);
1115 tmp |= tile_flags;
1116 ib[idx] = tmp;
1117
1118 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1119 break;
1120 case RADEON_RB3D_DEPTHPITCH:
1121 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1122 break;
1123 case RADEON_RB3D_CNTL:
1124 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1125 case 7:
1126 case 8:
1127 case 9:
1128 case 11:
1129 case 12:
1130 track->cb[0].cpp = 1;
1131 break;
1132 case 3:
1133 case 4:
1134 case 15:
1135 track->cb[0].cpp = 2;
1136 break;
1137 case 6:
1138 track->cb[0].cpp = 4;
1139 break;
1140 default:
1141 DRM_ERROR("Invalid color buffer format (%d) !\n",
1142 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1143 return -EINVAL;
1144 }
1145 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1146 break;
1147 case RADEON_RB3D_ZSTENCILCNTL:
1148 switch (idx_value & 0xf) {
1149 case 0:
1150 track->zb.cpp = 2;
1151 break;
1152 case 2:
1153 case 3:
1154 case 4:
1155 case 5:
1156 case 9:
1157 case 11:
1158 track->zb.cpp = 4;
1159 break;
1160 default:
1161 break;
1162 }
1163 break;
1164 case RADEON_RB3D_ZPASS_ADDR:
1165 r = r100_cs_packet_next_reloc(p, &reloc);
1166 if (r) {
1167 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1168 idx, reg);
1169 r100_cs_dump_packet(p, pkt);
1170 return r;
1171 }
1172 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1173 break;
1174 case RADEON_PP_CNTL:
1175 {
1176 uint32_t temp = idx_value >> 4;
1177 for (i = 0; i < track->num_texture; i++)
1178 track->textures[i].enabled = !!(temp & (1 << i));
1179 }
1180 break;
1181 case RADEON_SE_VF_CNTL:
1182 track->vap_vf_cntl = idx_value;
1183 break;
1184 case RADEON_SE_VTX_FMT:
1185 track->vtx_size = r100_get_vtx_size(idx_value);
1186 break;
1187 case RADEON_PP_TEX_SIZE_0:
1188 case RADEON_PP_TEX_SIZE_1:
1189 case RADEON_PP_TEX_SIZE_2:
1190 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1191 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1192 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1193 break;
1194 case RADEON_PP_TEX_PITCH_0:
1195 case RADEON_PP_TEX_PITCH_1:
1196 case RADEON_PP_TEX_PITCH_2:
1197 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1198 track->textures[i].pitch = idx_value + 32;
1199 break;
1200 case RADEON_PP_TXFILTER_0:
1201 case RADEON_PP_TXFILTER_1:
1202 case RADEON_PP_TXFILTER_2:
1203 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1204 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1205 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1206 tmp = (idx_value >> 23) & 0x7;
1207 if (tmp == 2 || tmp == 6)
1208 track->textures[i].roundup_w = false;
1209 tmp = (idx_value >> 27) & 0x7;
1210 if (tmp == 2 || tmp == 6)
1211 track->textures[i].roundup_h = false;
1212 break;
1213 case RADEON_PP_TXFORMAT_0:
1214 case RADEON_PP_TXFORMAT_1:
1215 case RADEON_PP_TXFORMAT_2:
1216 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1217 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1218 track->textures[i].use_pitch = 1;
1219 } else {
1220 track->textures[i].use_pitch = 0;
1221 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1222 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1223 }
1224 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1225 track->textures[i].tex_coord_type = 2;
1226 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1227 case RADEON_TXFORMAT_I8:
1228 case RADEON_TXFORMAT_RGB332:
1229 case RADEON_TXFORMAT_Y8:
1230 track->textures[i].cpp = 1;
1231 break;
1232 case RADEON_TXFORMAT_AI88:
1233 case RADEON_TXFORMAT_ARGB1555:
1234 case RADEON_TXFORMAT_RGB565:
1235 case RADEON_TXFORMAT_ARGB4444:
1236 case RADEON_TXFORMAT_VYUY422:
1237 case RADEON_TXFORMAT_YVYU422:
1238 case RADEON_TXFORMAT_DXT1:
1239 case RADEON_TXFORMAT_SHADOW16:
1240 case RADEON_TXFORMAT_LDUDV655:
1241 case RADEON_TXFORMAT_DUDV88:
1242 track->textures[i].cpp = 2;
1243 break;
1244 case RADEON_TXFORMAT_ARGB8888:
1245 case RADEON_TXFORMAT_RGBA8888:
1246 case RADEON_TXFORMAT_DXT23:
1247 case RADEON_TXFORMAT_DXT45:
1248 case RADEON_TXFORMAT_SHADOW32:
1249 case RADEON_TXFORMAT_LDUDUV8888:
1250 track->textures[i].cpp = 4;
1251 break;
1252 }
1253 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1254 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1255 break;
1256 case RADEON_PP_CUBIC_FACES_0:
1257 case RADEON_PP_CUBIC_FACES_1:
1258 case RADEON_PP_CUBIC_FACES_2:
1259 tmp = idx_value;
1260 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1261 for (face = 0; face < 4; face++) {
1262 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1263 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1264 }
1265 break;
1266 default:
1267 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1268 reg, idx);
1269 return -EINVAL;
1270 }
1271 return 0;
1272 }
1273
1274 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1275 struct radeon_cs_packet *pkt,
1276 struct radeon_object *robj)
1277 {
1278 unsigned idx;
1279 u32 value;
1280 idx = pkt->idx + 1;
1281 value = radeon_get_ib_value(p, idx + 2);
1282 if ((value + 1) > radeon_object_size(robj)) {
1283 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1284 "(need %u have %lu) !\n",
1285 value + 1,
1286 radeon_object_size(robj));
1287 return -EINVAL;
1288 }
1289 return 0;
1290 }
1291
1292 static int r100_packet3_check(struct radeon_cs_parser *p,
1293 struct radeon_cs_packet *pkt)
1294 {
1295 struct radeon_cs_reloc *reloc;
1296 struct r100_cs_track *track;
1297 unsigned idx;
1298 volatile uint32_t *ib;
1299 int r;
1300
1301 ib = p->ib->ptr;
1302 idx = pkt->idx + 1;
1303 track = (struct r100_cs_track *)p->track;
1304 switch (pkt->opcode) {
1305 case PACKET3_3D_LOAD_VBPNTR:
1306 r = r100_packet3_load_vbpntr(p, pkt, idx);
1307 if (r)
1308 return r;
1309 break;
1310 case PACKET3_INDX_BUFFER:
1311 r = r100_cs_packet_next_reloc(p, &reloc);
1312 if (r) {
1313 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1314 r100_cs_dump_packet(p, pkt);
1315 return r;
1316 }
1317 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1318 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1319 if (r) {
1320 return r;
1321 }
1322 break;
1323 case 0x23:
1324 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1325 r = r100_cs_packet_next_reloc(p, &reloc);
1326 if (r) {
1327 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1328 r100_cs_dump_packet(p, pkt);
1329 return r;
1330 }
1331 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1332 track->num_arrays = 1;
1333 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1334
1335 track->arrays[0].robj = reloc->robj;
1336 track->arrays[0].esize = track->vtx_size;
1337
1338 track->max_indx = radeon_get_ib_value(p, idx+1);
1339
1340 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1341 track->immd_dwords = pkt->count - 1;
1342 r = r100_cs_track_check(p->rdev, track);
1343 if (r)
1344 return r;
1345 break;
1346 case PACKET3_3D_DRAW_IMMD:
1347 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1348 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1349 return -EINVAL;
1350 }
1351 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1352 track->immd_dwords = pkt->count - 1;
1353 r = r100_cs_track_check(p->rdev, track);
1354 if (r)
1355 return r;
1356 break;
1357 /* triggers drawing using in-packet vertex data */
1358 case PACKET3_3D_DRAW_IMMD_2:
1359 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1360 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1361 return -EINVAL;
1362 }
1363 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1364 track->immd_dwords = pkt->count;
1365 r = r100_cs_track_check(p->rdev, track);
1366 if (r)
1367 return r;
1368 break;
1369 /* triggers drawing using in-packet vertex data */
1370 case PACKET3_3D_DRAW_VBUF_2:
1371 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1372 r = r100_cs_track_check(p->rdev, track);
1373 if (r)
1374 return r;
1375 break;
1376 /* triggers drawing of vertex buffers setup elsewhere */
1377 case PACKET3_3D_DRAW_INDX_2:
1378 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1379 r = r100_cs_track_check(p->rdev, track);
1380 if (r)
1381 return r;
1382 break;
1383 /* triggers drawing using indices to vertex buffer */
1384 case PACKET3_3D_DRAW_VBUF:
1385 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1386 r = r100_cs_track_check(p->rdev, track);
1387 if (r)
1388 return r;
1389 break;
1390 /* triggers drawing of vertex buffers setup elsewhere */
1391 case PACKET3_3D_DRAW_INDX:
1392 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1393 r = r100_cs_track_check(p->rdev, track);
1394 if (r)
1395 return r;
1396 break;
1397 /* triggers drawing using indices to vertex buffer */
1398 case PACKET3_NOP:
1399 break;
1400 default:
1401 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1402 return -EINVAL;
1403 }
1404 return 0;
1405 }
1406
1407 int r100_cs_parse(struct radeon_cs_parser *p)
1408 {
1409 struct radeon_cs_packet pkt;
1410 struct r100_cs_track *track;
1411 int r;
1412
1413 track = kzalloc(sizeof(*track), GFP_KERNEL);
1414 r100_cs_track_clear(p->rdev, track);
1415 p->track = track;
1416 do {
1417 r = r100_cs_packet_parse(p, &pkt, p->idx);
1418 if (r) {
1419 return r;
1420 }
1421 p->idx += pkt.count + 2;
1422 switch (pkt.type) {
1423 case PACKET_TYPE0:
1424 if (p->rdev->family >= CHIP_R200)
1425 r = r100_cs_parse_packet0(p, &pkt,
1426 p->rdev->config.r100.reg_safe_bm,
1427 p->rdev->config.r100.reg_safe_bm_size,
1428 &r200_packet0_check);
1429 else
1430 r = r100_cs_parse_packet0(p, &pkt,
1431 p->rdev->config.r100.reg_safe_bm,
1432 p->rdev->config.r100.reg_safe_bm_size,
1433 &r100_packet0_check);
1434 break;
1435 case PACKET_TYPE2:
1436 break;
1437 case PACKET_TYPE3:
1438 r = r100_packet3_check(p, &pkt);
1439 break;
1440 default:
1441 DRM_ERROR("Unknown packet type %d !\n",
1442 pkt.type);
1443 return -EINVAL;
1444 }
1445 if (r) {
1446 return r;
1447 }
1448 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1449 return 0;
1450 }
1451
1452
1453 /*
1454 * Global GPU functions
1455 */
1456 void r100_errata(struct radeon_device *rdev)
1457 {
1458 rdev->pll_errata = 0;
1459
1460 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1461 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1462 }
1463
1464 if (rdev->family == CHIP_RV100 ||
1465 rdev->family == CHIP_RS100 ||
1466 rdev->family == CHIP_RS200) {
1467 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1468 }
1469 }
1470
1471 /* Wait for vertical sync on primary CRTC */
1472 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1473 {
1474 uint32_t crtc_gen_cntl, tmp;
1475 int i;
1476
1477 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1478 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1479 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1480 return;
1481 }
1482 /* Clear the CRTC_VBLANK_SAVE bit */
1483 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1484 for (i = 0; i < rdev->usec_timeout; i++) {
1485 tmp = RREG32(RADEON_CRTC_STATUS);
1486 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1487 return;
1488 }
1489 DRM_UDELAY(1);
1490 }
1491 }
1492
1493 /* Wait for vertical sync on secondary CRTC */
1494 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1495 {
1496 uint32_t crtc2_gen_cntl, tmp;
1497 int i;
1498
1499 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1500 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1501 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1502 return;
1503
1504 /* Clear the CRTC_VBLANK_SAVE bit */
1505 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1506 for (i = 0; i < rdev->usec_timeout; i++) {
1507 tmp = RREG32(RADEON_CRTC2_STATUS);
1508 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1509 return;
1510 }
1511 DRM_UDELAY(1);
1512 }
1513 }
1514
1515 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1516 {
1517 unsigned i;
1518 uint32_t tmp;
1519
1520 for (i = 0; i < rdev->usec_timeout; i++) {
1521 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1522 if (tmp >= n) {
1523 return 0;
1524 }
1525 DRM_UDELAY(1);
1526 }
1527 return -1;
1528 }
1529
1530 int r100_gui_wait_for_idle(struct radeon_device *rdev)
1531 {
1532 unsigned i;
1533 uint32_t tmp;
1534
1535 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1536 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1537 " Bad things might happen.\n");
1538 }
1539 for (i = 0; i < rdev->usec_timeout; i++) {
1540 tmp = RREG32(RADEON_RBBM_STATUS);
1541 if (!(tmp & (1 << 31))) {
1542 return 0;
1543 }
1544 DRM_UDELAY(1);
1545 }
1546 return -1;
1547 }
1548
1549 int r100_mc_wait_for_idle(struct radeon_device *rdev)
1550 {
1551 unsigned i;
1552 uint32_t tmp;
1553
1554 for (i = 0; i < rdev->usec_timeout; i++) {
1555 /* read MC_STATUS */
1556 tmp = RREG32(0x0150);
1557 if (tmp & (1 << 2)) {
1558 return 0;
1559 }
1560 DRM_UDELAY(1);
1561 }
1562 return -1;
1563 }
1564
1565 void r100_gpu_init(struct radeon_device *rdev)
1566 {
1567 /* TODO: anythings to do here ? pipes ? */
1568 r100_hdp_reset(rdev);
1569 }
1570
1571 void r100_hdp_reset(struct radeon_device *rdev)
1572 {
1573 uint32_t tmp;
1574
1575 tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
1576 tmp |= (7 << 28);
1577 WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
1578 (void)RREG32(RADEON_HOST_PATH_CNTL);
1579 udelay(200);
1580 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1581 WREG32(RADEON_HOST_PATH_CNTL, tmp);
1582 (void)RREG32(RADEON_HOST_PATH_CNTL);
1583 }
1584
1585 int r100_rb2d_reset(struct radeon_device *rdev)
1586 {
1587 uint32_t tmp;
1588 int i;
1589
1590 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
1591 (void)RREG32(RADEON_RBBM_SOFT_RESET);
1592 udelay(200);
1593 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1594 /* Wait to prevent race in RBBM_STATUS */
1595 mdelay(1);
1596 for (i = 0; i < rdev->usec_timeout; i++) {
1597 tmp = RREG32(RADEON_RBBM_STATUS);
1598 if (!(tmp & (1 << 26))) {
1599 DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
1600 tmp);
1601 return 0;
1602 }
1603 DRM_UDELAY(1);
1604 }
1605 tmp = RREG32(RADEON_RBBM_STATUS);
1606 DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
1607 return -1;
1608 }
1609
1610 int r100_gpu_reset(struct radeon_device *rdev)
1611 {
1612 uint32_t status;
1613
1614 /* reset order likely matter */
1615 status = RREG32(RADEON_RBBM_STATUS);
1616 /* reset HDP */
1617 r100_hdp_reset(rdev);
1618 /* reset rb2d */
1619 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
1620 r100_rb2d_reset(rdev);
1621 }
1622 /* TODO: reset 3D engine */
1623 /* reset CP */
1624 status = RREG32(RADEON_RBBM_STATUS);
1625 if (status & (1 << 16)) {
1626 r100_cp_reset(rdev);
1627 }
1628 /* Check if GPU is idle */
1629 status = RREG32(RADEON_RBBM_STATUS);
1630 if (status & (1 << 31)) {
1631 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
1632 return -1;
1633 }
1634 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
1635 return 0;
1636 }
1637
1638
1639 /*
1640 * VRAM info
1641 */
1642 static void r100_vram_get_type(struct radeon_device *rdev)
1643 {
1644 uint32_t tmp;
1645
1646 rdev->mc.vram_is_ddr = false;
1647 if (rdev->flags & RADEON_IS_IGP)
1648 rdev->mc.vram_is_ddr = true;
1649 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
1650 rdev->mc.vram_is_ddr = true;
1651 if ((rdev->family == CHIP_RV100) ||
1652 (rdev->family == CHIP_RS100) ||
1653 (rdev->family == CHIP_RS200)) {
1654 tmp = RREG32(RADEON_MEM_CNTL);
1655 if (tmp & RV100_HALF_MODE) {
1656 rdev->mc.vram_width = 32;
1657 } else {
1658 rdev->mc.vram_width = 64;
1659 }
1660 if (rdev->flags & RADEON_SINGLE_CRTC) {
1661 rdev->mc.vram_width /= 4;
1662 rdev->mc.vram_is_ddr = true;
1663 }
1664 } else if (rdev->family <= CHIP_RV280) {
1665 tmp = RREG32(RADEON_MEM_CNTL);
1666 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
1667 rdev->mc.vram_width = 128;
1668 } else {
1669 rdev->mc.vram_width = 64;
1670 }
1671 } else {
1672 /* newer IGPs */
1673 rdev->mc.vram_width = 128;
1674 }
1675 }
1676
1677 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
1678 {
1679 u32 aper_size;
1680 u8 byte;
1681
1682 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1683
1684 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
1685 * that is has the 2nd generation multifunction PCI interface
1686 */
1687 if (rdev->family == CHIP_RV280 ||
1688 rdev->family >= CHIP_RV350) {
1689 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
1690 ~RADEON_HDP_APER_CNTL);
1691 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
1692 return aper_size * 2;
1693 }
1694
1695 /* Older cards have all sorts of funny issues to deal with. First
1696 * check if it's a multifunction card by reading the PCI config
1697 * header type... Limit those to one aperture size
1698 */
1699 pci_read_config_byte(rdev->pdev, 0xe, &byte);
1700 if (byte & 0x80) {
1701 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
1702 DRM_INFO("Limiting VRAM to one aperture\n");
1703 return aper_size;
1704 }
1705
1706 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
1707 * have set it up. We don't write this as it's broken on some ASICs but
1708 * we expect the BIOS to have done the right thing (might be too optimistic...)
1709 */
1710 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
1711 return aper_size * 2;
1712 return aper_size;
1713 }
1714
1715 void r100_vram_init_sizes(struct radeon_device *rdev)
1716 {
1717 u64 config_aper_size;
1718 u32 accessible;
1719
1720 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1721
1722 if (rdev->flags & RADEON_IS_IGP) {
1723 uint32_t tom;
1724 /* read NB_TOM to get the amount of ram stolen for the GPU */
1725 tom = RREG32(RADEON_NB_TOM);
1726 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
1727 /* for IGPs we need to keep VRAM where it was put by the BIOS */
1728 rdev->mc.vram_location = (tom & 0xffff) << 16;
1729 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1730 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1731 } else {
1732 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
1733 /* Some production boards of m6 will report 0
1734 * if it's 8 MB
1735 */
1736 if (rdev->mc.real_vram_size == 0) {
1737 rdev->mc.real_vram_size = 8192 * 1024;
1738 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1739 }
1740 /* let driver place VRAM */
1741 rdev->mc.vram_location = 0xFFFFFFFFUL;
1742 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1743 * Novell bug 204882 + along with lots of ubuntu ones */
1744 if (config_aper_size > rdev->mc.real_vram_size)
1745 rdev->mc.mc_vram_size = config_aper_size;
1746 else
1747 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1748 }
1749
1750 /* work out accessible VRAM */
1751 accessible = r100_get_accessible_vram(rdev);
1752
1753 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1754 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1755
1756 if (accessible > rdev->mc.aper_size)
1757 accessible = rdev->mc.aper_size;
1758
1759 if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
1760 rdev->mc.mc_vram_size = rdev->mc.aper_size;
1761
1762 if (rdev->mc.real_vram_size > rdev->mc.aper_size)
1763 rdev->mc.real_vram_size = rdev->mc.aper_size;
1764 }
1765
1766 void r100_vga_set_state(struct radeon_device *rdev, bool state)
1767 {
1768 uint32_t temp;
1769
1770 temp = RREG32(RADEON_CONFIG_CNTL);
1771 if (state == false) {
1772 temp &= ~(1<<8);
1773 temp |= (1<<9);
1774 } else {
1775 temp &= ~(1<<9);
1776 }
1777 WREG32(RADEON_CONFIG_CNTL, temp);
1778 }
1779
1780 void r100_vram_info(struct radeon_device *rdev)
1781 {
1782 r100_vram_get_type(rdev);
1783
1784 r100_vram_init_sizes(rdev);
1785 }
1786
1787
1788 /*
1789 * Indirect registers accessor
1790 */
1791 void r100_pll_errata_after_index(struct radeon_device *rdev)
1792 {
1793 if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
1794 return;
1795 }
1796 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
1797 (void)RREG32(RADEON_CRTC_GEN_CNTL);
1798 }
1799
1800 static void r100_pll_errata_after_data(struct radeon_device *rdev)
1801 {
1802 /* This workarounds is necessary on RV100, RS100 and RS200 chips
1803 * or the chip could hang on a subsequent access
1804 */
1805 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
1806 udelay(5000);
1807 }
1808
1809 /* This function is required to workaround a hardware bug in some (all?)
1810 * revisions of the R300. This workaround should be called after every
1811 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
1812 * may not be correct.
1813 */
1814 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
1815 uint32_t save, tmp;
1816
1817 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
1818 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
1819 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
1820 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
1821 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
1822 }
1823 }
1824
1825 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
1826 {
1827 uint32_t data;
1828
1829 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
1830 r100_pll_errata_after_index(rdev);
1831 data = RREG32(RADEON_CLOCK_CNTL_DATA);
1832 r100_pll_errata_after_data(rdev);
1833 return data;
1834 }
1835
1836 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1837 {
1838 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
1839 r100_pll_errata_after_index(rdev);
1840 WREG32(RADEON_CLOCK_CNTL_DATA, v);
1841 r100_pll_errata_after_data(rdev);
1842 }
1843
1844 void r100_set_safe_registers(struct radeon_device *rdev)
1845 {
1846 if (ASIC_IS_RN50(rdev)) {
1847 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
1848 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
1849 } else if (rdev->family < CHIP_R200) {
1850 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
1851 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
1852 } else {
1853 r200_set_safe_registers(rdev);
1854 }
1855 }
1856
1857 /*
1858 * Debugfs info
1859 */
1860 #if defined(CONFIG_DEBUG_FS)
1861 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
1862 {
1863 struct drm_info_node *node = (struct drm_info_node *) m->private;
1864 struct drm_device *dev = node->minor->dev;
1865 struct radeon_device *rdev = dev->dev_private;
1866 uint32_t reg, value;
1867 unsigned i;
1868
1869 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
1870 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
1871 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
1872 for (i = 0; i < 64; i++) {
1873 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
1874 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
1875 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
1876 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
1877 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
1878 }
1879 return 0;
1880 }
1881
1882 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
1883 {
1884 struct drm_info_node *node = (struct drm_info_node *) m->private;
1885 struct drm_device *dev = node->minor->dev;
1886 struct radeon_device *rdev = dev->dev_private;
1887 uint32_t rdp, wdp;
1888 unsigned count, i, j;
1889
1890 radeon_ring_free_size(rdev);
1891 rdp = RREG32(RADEON_CP_RB_RPTR);
1892 wdp = RREG32(RADEON_CP_RB_WPTR);
1893 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
1894 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
1895 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
1896 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
1897 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
1898 seq_printf(m, "%u dwords in ring\n", count);
1899 for (j = 0; j <= count; j++) {
1900 i = (rdp + j) & rdev->cp.ptr_mask;
1901 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
1902 }
1903 return 0;
1904 }
1905
1906
1907 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
1908 {
1909 struct drm_info_node *node = (struct drm_info_node *) m->private;
1910 struct drm_device *dev = node->minor->dev;
1911 struct radeon_device *rdev = dev->dev_private;
1912 uint32_t csq_stat, csq2_stat, tmp;
1913 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
1914 unsigned i;
1915
1916 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
1917 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
1918 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
1919 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
1920 r_rptr = (csq_stat >> 0) & 0x3ff;
1921 r_wptr = (csq_stat >> 10) & 0x3ff;
1922 ib1_rptr = (csq_stat >> 20) & 0x3ff;
1923 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
1924 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
1925 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
1926 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
1927 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
1928 seq_printf(m, "Ring rptr %u\n", r_rptr);
1929 seq_printf(m, "Ring wptr %u\n", r_wptr);
1930 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
1931 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
1932 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
1933 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
1934 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
1935 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
1936 seq_printf(m, "Ring fifo:\n");
1937 for (i = 0; i < 256; i++) {
1938 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
1939 tmp = RREG32(RADEON_CP_CSQ_DATA);
1940 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
1941 }
1942 seq_printf(m, "Indirect1 fifo:\n");
1943 for (i = 256; i <= 512; i++) {
1944 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
1945 tmp = RREG32(RADEON_CP_CSQ_DATA);
1946 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
1947 }
1948 seq_printf(m, "Indirect2 fifo:\n");
1949 for (i = 640; i < ib1_wptr; i++) {
1950 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
1951 tmp = RREG32(RADEON_CP_CSQ_DATA);
1952 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
1953 }
1954 return 0;
1955 }
1956
1957 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
1958 {
1959 struct drm_info_node *node = (struct drm_info_node *) m->private;
1960 struct drm_device *dev = node->minor->dev;
1961 struct radeon_device *rdev = dev->dev_private;
1962 uint32_t tmp;
1963
1964 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
1965 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
1966 tmp = RREG32(RADEON_MC_FB_LOCATION);
1967 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
1968 tmp = RREG32(RADEON_BUS_CNTL);
1969 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
1970 tmp = RREG32(RADEON_MC_AGP_LOCATION);
1971 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
1972 tmp = RREG32(RADEON_AGP_BASE);
1973 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
1974 tmp = RREG32(RADEON_HOST_PATH_CNTL);
1975 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
1976 tmp = RREG32(0x01D0);
1977 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
1978 tmp = RREG32(RADEON_AIC_LO_ADDR);
1979 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
1980 tmp = RREG32(RADEON_AIC_HI_ADDR);
1981 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
1982 tmp = RREG32(0x01E4);
1983 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
1984 return 0;
1985 }
1986
1987 static struct drm_info_list r100_debugfs_rbbm_list[] = {
1988 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
1989 };
1990
1991 static struct drm_info_list r100_debugfs_cp_list[] = {
1992 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
1993 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
1994 };
1995
1996 static struct drm_info_list r100_debugfs_mc_info_list[] = {
1997 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
1998 };
1999 #endif
2000
2001 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2002 {
2003 #if defined(CONFIG_DEBUG_FS)
2004 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2005 #else
2006 return 0;
2007 #endif
2008 }
2009
2010 int r100_debugfs_cp_init(struct radeon_device *rdev)
2011 {
2012 #if defined(CONFIG_DEBUG_FS)
2013 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2014 #else
2015 return 0;
2016 #endif
2017 }
2018
2019 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2020 {
2021 #if defined(CONFIG_DEBUG_FS)
2022 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2023 #else
2024 return 0;
2025 #endif
2026 }
2027
2028 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2029 uint32_t tiling_flags, uint32_t pitch,
2030 uint32_t offset, uint32_t obj_size)
2031 {
2032 int surf_index = reg * 16;
2033 int flags = 0;
2034
2035 /* r100/r200 divide by 16 */
2036 if (rdev->family < CHIP_R300)
2037 flags = pitch / 16;
2038 else
2039 flags = pitch / 8;
2040
2041 if (rdev->family <= CHIP_RS200) {
2042 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2043 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2044 flags |= RADEON_SURF_TILE_COLOR_BOTH;
2045 if (tiling_flags & RADEON_TILING_MACRO)
2046 flags |= RADEON_SURF_TILE_COLOR_MACRO;
2047 } else if (rdev->family <= CHIP_RV280) {
2048 if (tiling_flags & (RADEON_TILING_MACRO))
2049 flags |= R200_SURF_TILE_COLOR_MACRO;
2050 if (tiling_flags & RADEON_TILING_MICRO)
2051 flags |= R200_SURF_TILE_COLOR_MICRO;
2052 } else {
2053 if (tiling_flags & RADEON_TILING_MACRO)
2054 flags |= R300_SURF_TILE_MACRO;
2055 if (tiling_flags & RADEON_TILING_MICRO)
2056 flags |= R300_SURF_TILE_MICRO;
2057 }
2058
2059 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2060 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2061 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2062 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2063
2064 DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2065 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2066 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2067 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2068 return 0;
2069 }
2070
2071 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2072 {
2073 int surf_index = reg * 16;
2074 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2075 }
2076
2077 void r100_bandwidth_update(struct radeon_device *rdev)
2078 {
2079 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2080 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2081 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2082 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2083 fixed20_12 memtcas_ff[8] = {
2084 fixed_init(1),
2085 fixed_init(2),
2086 fixed_init(3),
2087 fixed_init(0),
2088 fixed_init_half(1),
2089 fixed_init_half(2),
2090 fixed_init(0),
2091 };
2092 fixed20_12 memtcas_rs480_ff[8] = {
2093 fixed_init(0),
2094 fixed_init(1),
2095 fixed_init(2),
2096 fixed_init(3),
2097 fixed_init(0),
2098 fixed_init_half(1),
2099 fixed_init_half(2),
2100 fixed_init_half(3),
2101 };
2102 fixed20_12 memtcas2_ff[8] = {
2103 fixed_init(0),
2104 fixed_init(1),
2105 fixed_init(2),
2106 fixed_init(3),
2107 fixed_init(4),
2108 fixed_init(5),
2109 fixed_init(6),
2110 fixed_init(7),
2111 };
2112 fixed20_12 memtrbs[8] = {
2113 fixed_init(1),
2114 fixed_init_half(1),
2115 fixed_init(2),
2116 fixed_init_half(2),
2117 fixed_init(3),
2118 fixed_init_half(3),
2119 fixed_init(4),
2120 fixed_init_half(4)
2121 };
2122 fixed20_12 memtrbs_r4xx[8] = {
2123 fixed_init(4),
2124 fixed_init(5),
2125 fixed_init(6),
2126 fixed_init(7),
2127 fixed_init(8),
2128 fixed_init(9),
2129 fixed_init(10),
2130 fixed_init(11)
2131 };
2132 fixed20_12 min_mem_eff;
2133 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2134 fixed20_12 cur_latency_mclk, cur_latency_sclk;
2135 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2136 disp_drain_rate2, read_return_rate;
2137 fixed20_12 time_disp1_drop_priority;
2138 int c;
2139 int cur_size = 16; /* in octawords */
2140 int critical_point = 0, critical_point2;
2141 /* uint32_t read_return_rate, time_disp1_drop_priority; */
2142 int stop_req, max_stop_req;
2143 struct drm_display_mode *mode1 = NULL;
2144 struct drm_display_mode *mode2 = NULL;
2145 uint32_t pixel_bytes1 = 0;
2146 uint32_t pixel_bytes2 = 0;
2147
2148 if (rdev->mode_info.crtcs[0]->base.enabled) {
2149 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2150 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2151 }
2152 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2153 if (rdev->mode_info.crtcs[1]->base.enabled) {
2154 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2155 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2156 }
2157 }
2158
2159 min_mem_eff.full = rfixed_const_8(0);
2160 /* get modes */
2161 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2162 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2163 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2164 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2165 /* check crtc enables */
2166 if (mode2)
2167 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2168 if (mode1)
2169 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2170 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2171 }
2172
2173 /*
2174 * determine is there is enough bw for current mode
2175 */
2176 mclk_ff.full = rfixed_const(rdev->clock.default_mclk);
2177 temp_ff.full = rfixed_const(100);
2178 mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
2179 sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
2180 sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
2181
2182 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2183 temp_ff.full = rfixed_const(temp);
2184 mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
2185
2186 pix_clk.full = 0;
2187 pix_clk2.full = 0;
2188 peak_disp_bw.full = 0;
2189 if (mode1) {
2190 temp_ff.full = rfixed_const(1000);
2191 pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
2192 pix_clk.full = rfixed_div(pix_clk, temp_ff);
2193 temp_ff.full = rfixed_const(pixel_bytes1);
2194 peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
2195 }
2196 if (mode2) {
2197 temp_ff.full = rfixed_const(1000);
2198 pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
2199 pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
2200 temp_ff.full = rfixed_const(pixel_bytes2);
2201 peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
2202 }
2203
2204 mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
2205 if (peak_disp_bw.full >= mem_bw.full) {
2206 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2207 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2208 }
2209
2210 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2211 temp = RREG32(RADEON_MEM_TIMING_CNTL);
2212 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2213 mem_trcd = ((temp >> 2) & 0x3) + 1;
2214 mem_trp = ((temp & 0x3)) + 1;
2215 mem_tras = ((temp & 0x70) >> 4) + 1;
2216 } else if (rdev->family == CHIP_R300 ||
2217 rdev->family == CHIP_R350) { /* r300, r350 */
2218 mem_trcd = (temp & 0x7) + 1;
2219 mem_trp = ((temp >> 8) & 0x7) + 1;
2220 mem_tras = ((temp >> 11) & 0xf) + 4;
2221 } else if (rdev->family == CHIP_RV350 ||
2222 rdev->family <= CHIP_RV380) {
2223 /* rv3x0 */
2224 mem_trcd = (temp & 0x7) + 3;
2225 mem_trp = ((temp >> 8) & 0x7) + 3;
2226 mem_tras = ((temp >> 11) & 0xf) + 6;
2227 } else if (rdev->family == CHIP_R420 ||
2228 rdev->family == CHIP_R423 ||
2229 rdev->family == CHIP_RV410) {
2230 /* r4xx */
2231 mem_trcd = (temp & 0xf) + 3;
2232 if (mem_trcd > 15)
2233 mem_trcd = 15;
2234 mem_trp = ((temp >> 8) & 0xf) + 3;
2235 if (mem_trp > 15)
2236 mem_trp = 15;
2237 mem_tras = ((temp >> 12) & 0x1f) + 6;
2238 if (mem_tras > 31)
2239 mem_tras = 31;
2240 } else { /* RV200, R200 */
2241 mem_trcd = (temp & 0x7) + 1;
2242 mem_trp = ((temp >> 8) & 0x7) + 1;
2243 mem_tras = ((temp >> 12) & 0xf) + 4;
2244 }
2245 /* convert to FF */
2246 trcd_ff.full = rfixed_const(mem_trcd);
2247 trp_ff.full = rfixed_const(mem_trp);
2248 tras_ff.full = rfixed_const(mem_tras);
2249
2250 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2251 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2252 data = (temp & (7 << 20)) >> 20;
2253 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2254 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2255 tcas_ff = memtcas_rs480_ff[data];
2256 else
2257 tcas_ff = memtcas_ff[data];
2258 } else
2259 tcas_ff = memtcas2_ff[data];
2260
2261 if (rdev->family == CHIP_RS400 ||
2262 rdev->family == CHIP_RS480) {
2263 /* extra cas latency stored in bits 23-25 0-4 clocks */
2264 data = (temp >> 23) & 0x7;
2265 if (data < 5)
2266 tcas_ff.full += rfixed_const(data);
2267 }
2268
2269 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2270 /* on the R300, Tcas is included in Trbs.
2271 */
2272 temp = RREG32(RADEON_MEM_CNTL);
2273 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2274 if (data == 1) {
2275 if (R300_MEM_USE_CD_CH_ONLY & temp) {
2276 temp = RREG32(R300_MC_IND_INDEX);
2277 temp &= ~R300_MC_IND_ADDR_MASK;
2278 temp |= R300_MC_READ_CNTL_CD_mcind;
2279 WREG32(R300_MC_IND_INDEX, temp);
2280 temp = RREG32(R300_MC_IND_DATA);
2281 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2282 } else {
2283 temp = RREG32(R300_MC_READ_CNTL_AB);
2284 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2285 }
2286 } else {
2287 temp = RREG32(R300_MC_READ_CNTL_AB);
2288 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2289 }
2290 if (rdev->family == CHIP_RV410 ||
2291 rdev->family == CHIP_R420 ||
2292 rdev->family == CHIP_R423)
2293 trbs_ff = memtrbs_r4xx[data];
2294 else
2295 trbs_ff = memtrbs[data];
2296 tcas_ff.full += trbs_ff.full;
2297 }
2298
2299 sclk_eff_ff.full = sclk_ff.full;
2300
2301 if (rdev->flags & RADEON_IS_AGP) {
2302 fixed20_12 agpmode_ff;
2303 agpmode_ff.full = rfixed_const(radeon_agpmode);
2304 temp_ff.full = rfixed_const_666(16);
2305 sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
2306 }
2307 /* TODO PCIE lanes may affect this - agpmode == 16?? */
2308
2309 if (ASIC_IS_R300(rdev)) {
2310 sclk_delay_ff.full = rfixed_const(250);
2311 } else {
2312 if ((rdev->family == CHIP_RV100) ||
2313 rdev->flags & RADEON_IS_IGP) {
2314 if (rdev->mc.vram_is_ddr)
2315 sclk_delay_ff.full = rfixed_const(41);
2316 else
2317 sclk_delay_ff.full = rfixed_const(33);
2318 } else {
2319 if (rdev->mc.vram_width == 128)
2320 sclk_delay_ff.full = rfixed_const(57);
2321 else
2322 sclk_delay_ff.full = rfixed_const(41);
2323 }
2324 }
2325
2326 mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
2327
2328 if (rdev->mc.vram_is_ddr) {
2329 if (rdev->mc.vram_width == 32) {
2330 k1.full = rfixed_const(40);
2331 c = 3;
2332 } else {
2333 k1.full = rfixed_const(20);
2334 c = 1;
2335 }
2336 } else {
2337 k1.full = rfixed_const(40);
2338 c = 3;
2339 }
2340
2341 temp_ff.full = rfixed_const(2);
2342 mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
2343 temp_ff.full = rfixed_const(c);
2344 mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
2345 temp_ff.full = rfixed_const(4);
2346 mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
2347 mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
2348 mc_latency_mclk.full += k1.full;
2349
2350 mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
2351 mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
2352
2353 /*
2354 HW cursor time assuming worst case of full size colour cursor.
2355 */
2356 temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2357 temp_ff.full += trcd_ff.full;
2358 if (temp_ff.full < tras_ff.full)
2359 temp_ff.full = tras_ff.full;
2360 cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
2361
2362 temp_ff.full = rfixed_const(cur_size);
2363 cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
2364 /*
2365 Find the total latency for the display data.
2366 */
2367 disp_latency_overhead.full = rfixed_const(80);
2368 disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
2369 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2370 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2371
2372 if (mc_latency_mclk.full > mc_latency_sclk.full)
2373 disp_latency.full = mc_latency_mclk.full;
2374 else
2375 disp_latency.full = mc_latency_sclk.full;
2376
2377 /* setup Max GRPH_STOP_REQ default value */
2378 if (ASIC_IS_RV100(rdev))
2379 max_stop_req = 0x5c;
2380 else
2381 max_stop_req = 0x7c;
2382
2383 if (mode1) {
2384 /* CRTC1
2385 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2386 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2387 */
2388 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2389
2390 if (stop_req > max_stop_req)
2391 stop_req = max_stop_req;
2392
2393 /*
2394 Find the drain rate of the display buffer.
2395 */
2396 temp_ff.full = rfixed_const((16/pixel_bytes1));
2397 disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
2398
2399 /*
2400 Find the critical point of the display buffer.
2401 */
2402 crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
2403 crit_point_ff.full += rfixed_const_half(0);
2404
2405 critical_point = rfixed_trunc(crit_point_ff);
2406
2407 if (rdev->disp_priority == 2) {
2408 critical_point = 0;
2409 }
2410
2411 /*
2412 The critical point should never be above max_stop_req-4. Setting
2413 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2414 */
2415 if (max_stop_req - critical_point < 4)
2416 critical_point = 0;
2417
2418 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
2419 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
2420 critical_point = 0x10;
2421 }
2422
2423 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
2424 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
2425 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2426 temp &= ~(RADEON_GRPH_START_REQ_MASK);
2427 if ((rdev->family == CHIP_R350) &&
2428 (stop_req > 0x15)) {
2429 stop_req -= 0x10;
2430 }
2431 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2432 temp |= RADEON_GRPH_BUFFER_SIZE;
2433 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
2434 RADEON_GRPH_CRITICAL_AT_SOF |
2435 RADEON_GRPH_STOP_CNTL);
2436 /*
2437 Write the result into the register.
2438 */
2439 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2440 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2441
2442 #if 0
2443 if ((rdev->family == CHIP_RS400) ||
2444 (rdev->family == CHIP_RS480)) {
2445 /* attempt to program RS400 disp regs correctly ??? */
2446 temp = RREG32(RS400_DISP1_REG_CNTL);
2447 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
2448 RS400_DISP1_STOP_REQ_LEVEL_MASK);
2449 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
2450 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2451 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2452 temp = RREG32(RS400_DMIF_MEM_CNTL1);
2453 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
2454 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
2455 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
2456 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
2457 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
2458 }
2459 #endif
2460
2461 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
2462 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
2463 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
2464 }
2465
2466 if (mode2) {
2467 u32 grph2_cntl;
2468 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
2469
2470 if (stop_req > max_stop_req)
2471 stop_req = max_stop_req;
2472
2473 /*
2474 Find the drain rate of the display buffer.
2475 */
2476 temp_ff.full = rfixed_const((16/pixel_bytes2));
2477 disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
2478
2479 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
2480 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
2481 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2482 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
2483 if ((rdev->family == CHIP_R350) &&
2484 (stop_req > 0x15)) {
2485 stop_req -= 0x10;
2486 }
2487 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2488 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
2489 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
2490 RADEON_GRPH_CRITICAL_AT_SOF |
2491 RADEON_GRPH_STOP_CNTL);
2492
2493 if ((rdev->family == CHIP_RS100) ||
2494 (rdev->family == CHIP_RS200))
2495 critical_point2 = 0;
2496 else {
2497 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
2498 temp_ff.full = rfixed_const(temp);
2499 temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
2500 if (sclk_ff.full < temp_ff.full)
2501 temp_ff.full = sclk_ff.full;
2502
2503 read_return_rate.full = temp_ff.full;
2504
2505 if (mode1) {
2506 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
2507 time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
2508 } else {
2509 time_disp1_drop_priority.full = 0;
2510 }
2511 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
2512 crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
2513 crit_point_ff.full += rfixed_const_half(0);
2514
2515 critical_point2 = rfixed_trunc(crit_point_ff);
2516
2517 if (rdev->disp_priority == 2) {
2518 critical_point2 = 0;
2519 }
2520
2521 if (max_stop_req - critical_point2 < 4)
2522 critical_point2 = 0;
2523
2524 }
2525
2526 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
2527 /* some R300 cards have problem with this set to 0 */
2528 critical_point2 = 0x10;
2529 }
2530
2531 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2532 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2533
2534 if ((rdev->family == CHIP_RS400) ||
2535 (rdev->family == CHIP_RS480)) {
2536 #if 0
2537 /* attempt to program RS400 disp2 regs correctly ??? */
2538 temp = RREG32(RS400_DISP2_REQ_CNTL1);
2539 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
2540 RS400_DISP2_STOP_REQ_LEVEL_MASK);
2541 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
2542 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2543 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2544 temp = RREG32(RS400_DISP2_REQ_CNTL2);
2545 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
2546 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
2547 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
2548 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
2549 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
2550 #endif
2551 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
2552 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
2553 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
2554 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
2555 }
2556
2557 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
2558 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
2559 }
2560 }
2561
2562 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2563 {
2564 DRM_ERROR("pitch %d\n", t->pitch);
2565 DRM_ERROR("width %d\n", t->width);
2566 DRM_ERROR("height %d\n", t->height);
2567 DRM_ERROR("num levels %d\n", t->num_levels);
2568 DRM_ERROR("depth %d\n", t->txdepth);
2569 DRM_ERROR("bpp %d\n", t->cpp);
2570 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2571 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2572 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2573 }
2574
2575 static int r100_cs_track_cube(struct radeon_device *rdev,
2576 struct r100_cs_track *track, unsigned idx)
2577 {
2578 unsigned face, w, h;
2579 struct radeon_object *cube_robj;
2580 unsigned long size;
2581
2582 for (face = 0; face < 5; face++) {
2583 cube_robj = track->textures[idx].cube_info[face].robj;
2584 w = track->textures[idx].cube_info[face].width;
2585 h = track->textures[idx].cube_info[face].height;
2586
2587 size = w * h;
2588 size *= track->textures[idx].cpp;
2589
2590 size += track->textures[idx].cube_info[face].offset;
2591
2592 if (size > radeon_object_size(cube_robj)) {
2593 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2594 size, radeon_object_size(cube_robj));
2595 r100_cs_track_texture_print(&track->textures[idx]);
2596 return -1;
2597 }
2598 }
2599 return 0;
2600 }
2601
2602 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2603 struct r100_cs_track *track)
2604 {
2605 struct radeon_object *robj;
2606 unsigned long size;
2607 unsigned u, i, w, h;
2608 int ret;
2609
2610 for (u = 0; u < track->num_texture; u++) {
2611 if (!track->textures[u].enabled)
2612 continue;
2613 robj = track->textures[u].robj;
2614 if (robj == NULL) {
2615 DRM_ERROR("No texture bound to unit %u\n", u);
2616 return -EINVAL;
2617 }
2618 size = 0;
2619 for (i = 0; i <= track->textures[u].num_levels; i++) {
2620 if (track->textures[u].use_pitch) {
2621 if (rdev->family < CHIP_R300)
2622 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2623 else
2624 w = track->textures[u].pitch / (1 << i);
2625 } else {
2626 w = track->textures[u].width / (1 << i);
2627 if (rdev->family >= CHIP_RV515)
2628 w |= track->textures[u].width_11;
2629 if (track->textures[u].roundup_w)
2630 w = roundup_pow_of_two(w);
2631 }
2632 h = track->textures[u].height / (1 << i);
2633 if (rdev->family >= CHIP_RV515)
2634 h |= track->textures[u].height_11;
2635 if (track->textures[u].roundup_h)
2636 h = roundup_pow_of_two(h);
2637 size += w * h;
2638 }
2639 size *= track->textures[u].cpp;
2640 switch (track->textures[u].tex_coord_type) {
2641 case 0:
2642 break;
2643 case 1:
2644 size *= (1 << track->textures[u].txdepth);
2645 break;
2646 case 2:
2647 if (track->separate_cube) {
2648 ret = r100_cs_track_cube(rdev, track, u);
2649 if (ret)
2650 return ret;
2651 } else
2652 size *= 6;
2653 break;
2654 default:
2655 DRM_ERROR("Invalid texture coordinate type %u for unit "
2656 "%u\n", track->textures[u].tex_coord_type, u);
2657 return -EINVAL;
2658 }
2659 if (size > radeon_object_size(robj)) {
2660 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2661 "%lu\n", u, size, radeon_object_size(robj));
2662 r100_cs_track_texture_print(&track->textures[u]);
2663 return -EINVAL;
2664 }
2665 }
2666 return 0;
2667 }
2668
2669 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2670 {
2671 unsigned i;
2672 unsigned long size;
2673 unsigned prim_walk;
2674 unsigned nverts;
2675
2676 for (i = 0; i < track->num_cb; i++) {
2677 if (track->cb[i].robj == NULL) {
2678 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2679 return -EINVAL;
2680 }
2681 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2682 size += track->cb[i].offset;
2683 if (size > radeon_object_size(track->cb[i].robj)) {
2684 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2685 "(need %lu have %lu) !\n", i, size,
2686 radeon_object_size(track->cb[i].robj));
2687 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2688 i, track->cb[i].pitch, track->cb[i].cpp,
2689 track->cb[i].offset, track->maxy);
2690 return -EINVAL;
2691 }
2692 }
2693 if (track->z_enabled) {
2694 if (track->zb.robj == NULL) {
2695 DRM_ERROR("[drm] No buffer for z buffer !\n");
2696 return -EINVAL;
2697 }
2698 size = track->zb.pitch * track->zb.cpp * track->maxy;
2699 size += track->zb.offset;
2700 if (size > radeon_object_size(track->zb.robj)) {
2701 DRM_ERROR("[drm] Buffer too small for z buffer "
2702 "(need %lu have %lu) !\n", size,
2703 radeon_object_size(track->zb.robj));
2704 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2705 track->zb.pitch, track->zb.cpp,
2706 track->zb.offset, track->maxy);
2707 return -EINVAL;
2708 }
2709 }
2710 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2711 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2712 switch (prim_walk) {
2713 case 1:
2714 for (i = 0; i < track->num_arrays; i++) {
2715 size = track->arrays[i].esize * track->max_indx * 4;
2716 if (track->arrays[i].robj == NULL) {
2717 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2718 "bound\n", prim_walk, i);
2719 return -EINVAL;
2720 }
2721 if (size > radeon_object_size(track->arrays[i].robj)) {
2722 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
2723 "have %lu dwords\n", prim_walk, i,
2724 size >> 2,
2725 radeon_object_size(track->arrays[i].robj) >> 2);
2726 DRM_ERROR("Max indices %u\n", track->max_indx);
2727 return -EINVAL;
2728 }
2729 }
2730 break;
2731 case 2:
2732 for (i = 0; i < track->num_arrays; i++) {
2733 size = track->arrays[i].esize * (nverts - 1) * 4;
2734 if (track->arrays[i].robj == NULL) {
2735 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2736 "bound\n", prim_walk, i);
2737 return -EINVAL;
2738 }
2739 if (size > radeon_object_size(track->arrays[i].robj)) {
2740 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
2741 "have %lu dwords\n", prim_walk, i, size >> 2,
2742 radeon_object_size(track->arrays[i].robj) >> 2);
2743 return -EINVAL;
2744 }
2745 }
2746 break;
2747 case 3:
2748 size = track->vtx_size * nverts;
2749 if (size != track->immd_dwords) {
2750 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2751 track->immd_dwords, size);
2752 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2753 nverts, track->vtx_size);
2754 return -EINVAL;
2755 }
2756 break;
2757 default:
2758 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2759 prim_walk);
2760 return -EINVAL;
2761 }
2762 return r100_cs_track_texture_check(rdev, track);
2763 }
2764
2765 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2766 {
2767 unsigned i, face;
2768
2769 if (rdev->family < CHIP_R300) {
2770 track->num_cb = 1;
2771 if (rdev->family <= CHIP_RS200)
2772 track->num_texture = 3;
2773 else
2774 track->num_texture = 6;
2775 track->maxy = 2048;
2776 track->separate_cube = 1;
2777 } else {
2778 track->num_cb = 4;
2779 track->num_texture = 16;
2780 track->maxy = 4096;
2781 track->separate_cube = 0;
2782 }
2783
2784 for (i = 0; i < track->num_cb; i++) {
2785 track->cb[i].robj = NULL;
2786 track->cb[i].pitch = 8192;
2787 track->cb[i].cpp = 16;
2788 track->cb[i].offset = 0;
2789 }
2790 track->z_enabled = true;
2791 track->zb.robj = NULL;
2792 track->zb.pitch = 8192;
2793 track->zb.cpp = 4;
2794 track->zb.offset = 0;
2795 track->vtx_size = 0x7F;
2796 track->immd_dwords = 0xFFFFFFFFUL;
2797 track->num_arrays = 11;
2798 track->max_indx = 0x00FFFFFFUL;
2799 for (i = 0; i < track->num_arrays; i++) {
2800 track->arrays[i].robj = NULL;
2801 track->arrays[i].esize = 0x7F;
2802 }
2803 for (i = 0; i < track->num_texture; i++) {
2804 track->textures[i].pitch = 16536;
2805 track->textures[i].width = 16536;
2806 track->textures[i].height = 16536;
2807 track->textures[i].width_11 = 1 << 11;
2808 track->textures[i].height_11 = 1 << 11;
2809 track->textures[i].num_levels = 12;
2810 if (rdev->family <= CHIP_RS200) {
2811 track->textures[i].tex_coord_type = 0;
2812 track->textures[i].txdepth = 0;
2813 } else {
2814 track->textures[i].txdepth = 16;
2815 track->textures[i].tex_coord_type = 1;
2816 }
2817 track->textures[i].cpp = 64;
2818 track->textures[i].robj = NULL;
2819 /* CS IB emission code makes sure texture unit are disabled */
2820 track->textures[i].enabled = false;
2821 track->textures[i].roundup_w = true;
2822 track->textures[i].roundup_h = true;
2823 if (track->separate_cube)
2824 for (face = 0; face < 5; face++) {
2825 track->textures[i].cube_info[face].robj = NULL;
2826 track->textures[i].cube_info[face].width = 16536;
2827 track->textures[i].cube_info[face].height = 16536;
2828 track->textures[i].cube_info[face].offset = 0;
2829 }
2830 }
2831 }
2832
2833 int r100_ring_test(struct radeon_device *rdev)
2834 {
2835 uint32_t scratch;
2836 uint32_t tmp = 0;
2837 unsigned i;
2838 int r;
2839
2840 r = radeon_scratch_get(rdev, &scratch);
2841 if (r) {
2842 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2843 return r;
2844 }
2845 WREG32(scratch, 0xCAFEDEAD);
2846 r = radeon_ring_lock(rdev, 2);
2847 if (r) {
2848 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2849 radeon_scratch_free(rdev, scratch);
2850 return r;
2851 }
2852 radeon_ring_write(rdev, PACKET0(scratch, 0));
2853 radeon_ring_write(rdev, 0xDEADBEEF);
2854 radeon_ring_unlock_commit(rdev);
2855 for (i = 0; i < rdev->usec_timeout; i++) {
2856 tmp = RREG32(scratch);
2857 if (tmp == 0xDEADBEEF) {
2858 break;
2859 }
2860 DRM_UDELAY(1);
2861 }
2862 if (i < rdev->usec_timeout) {
2863 DRM_INFO("ring test succeeded in %d usecs\n", i);
2864 } else {
2865 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
2866 scratch, tmp);
2867 r = -EINVAL;
2868 }
2869 radeon_scratch_free(rdev, scratch);
2870 return r;
2871 }
2872
2873 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2874 {
2875 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
2876 radeon_ring_write(rdev, ib->gpu_addr);
2877 radeon_ring_write(rdev, ib->length_dw);
2878 }
2879
2880 int r100_ib_test(struct radeon_device *rdev)
2881 {
2882 struct radeon_ib *ib;
2883 uint32_t scratch;
2884 uint32_t tmp = 0;
2885 unsigned i;
2886 int r;
2887
2888 r = radeon_scratch_get(rdev, &scratch);
2889 if (r) {
2890 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2891 return r;
2892 }
2893 WREG32(scratch, 0xCAFEDEAD);
2894 r = radeon_ib_get(rdev, &ib);
2895 if (r) {
2896 return r;
2897 }
2898 ib->ptr[0] = PACKET0(scratch, 0);
2899 ib->ptr[1] = 0xDEADBEEF;
2900 ib->ptr[2] = PACKET2(0);
2901 ib->ptr[3] = PACKET2(0);
2902 ib->ptr[4] = PACKET2(0);
2903 ib->ptr[5] = PACKET2(0);
2904 ib->ptr[6] = PACKET2(0);
2905 ib->ptr[7] = PACKET2(0);
2906 ib->length_dw = 8;
2907 r = radeon_ib_schedule(rdev, ib);
2908 if (r) {
2909 radeon_scratch_free(rdev, scratch);
2910 radeon_ib_free(rdev, &ib);
2911 return r;
2912 }
2913 r = radeon_fence_wait(ib->fence, false);
2914 if (r) {
2915 return r;
2916 }
2917 for (i = 0; i < rdev->usec_timeout; i++) {
2918 tmp = RREG32(scratch);
2919 if (tmp == 0xDEADBEEF) {
2920 break;
2921 }
2922 DRM_UDELAY(1);
2923 }
2924 if (i < rdev->usec_timeout) {
2925 DRM_INFO("ib test succeeded in %u usecs\n", i);
2926 } else {
2927 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
2928 scratch, tmp);
2929 r = -EINVAL;
2930 }
2931 radeon_scratch_free(rdev, scratch);
2932 radeon_ib_free(rdev, &ib);
2933 return r;
2934 }
2935
2936 void r100_ib_fini(struct radeon_device *rdev)
2937 {
2938 radeon_ib_pool_fini(rdev);
2939 }
2940
2941 int r100_ib_init(struct radeon_device *rdev)
2942 {
2943 int r;
2944
2945 r = radeon_ib_pool_init(rdev);
2946 if (r) {
2947 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
2948 r100_ib_fini(rdev);
2949 return r;
2950 }
2951 r = r100_ib_test(rdev);
2952 if (r) {
2953 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
2954 r100_ib_fini(rdev);
2955 return r;
2956 }
2957 return 0;
2958 }
2959
2960 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
2961 {
2962 /* Shutdown CP we shouldn't need to do that but better be safe than
2963 * sorry
2964 */
2965 rdev->cp.ready = false;
2966 WREG32(R_000740_CP_CSQ_CNTL, 0);
2967
2968 /* Save few CRTC registers */
2969 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
2970 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
2971 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
2972 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
2973 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2974 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
2975 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
2976 }
2977
2978 /* Disable VGA aperture access */
2979 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
2980 /* Disable cursor, overlay, crtc */
2981 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
2982 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
2983 S_000054_CRTC_DISPLAY_DIS(1));
2984 WREG32(R_000050_CRTC_GEN_CNTL,
2985 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
2986 S_000050_CRTC_DISP_REQ_EN_B(1));
2987 WREG32(R_000420_OV0_SCALE_CNTL,
2988 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
2989 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
2990 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2991 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
2992 S_000360_CUR2_LOCK(1));
2993 WREG32(R_0003F8_CRTC2_GEN_CNTL,
2994 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
2995 S_0003F8_CRTC2_DISPLAY_DIS(1) |
2996 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
2997 WREG32(R_000360_CUR2_OFFSET,
2998 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
2999 }
3000 }
3001
3002 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3003 {
3004 /* Update base address for crtc */
3005 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_location);
3006 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3007 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR,
3008 rdev->mc.vram_location);
3009 }
3010 /* Restore CRTC registers */
3011 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3012 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3013 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3014 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3015 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3016 }
3017 }
3018
3019 void r100_vga_render_disable(struct radeon_device *rdev)
3020 {
3021 u32 tmp;
3022
3023 tmp = RREG8(R_0003C2_GENMO_WT);
3024 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3025 }
3026
3027 static void r100_debugfs(struct radeon_device *rdev)
3028 {
3029 int r;
3030
3031 r = r100_debugfs_mc_info_init(rdev);
3032 if (r)
3033 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3034 }
3035
3036 static void r100_mc_program(struct radeon_device *rdev)
3037 {
3038 struct r100_mc_save save;
3039
3040 /* Stops all mc clients */
3041 r100_mc_stop(rdev, &save);
3042 if (rdev->flags & RADEON_IS_AGP) {
3043 WREG32(R_00014C_MC_AGP_LOCATION,
3044 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3045 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3046 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3047 if (rdev->family > CHIP_RV200)
3048 WREG32(R_00015C_AGP_BASE_2,
3049 upper_32_bits(rdev->mc.agp_base) & 0xff);
3050 } else {
3051 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3052 WREG32(R_000170_AGP_BASE, 0);
3053 if (rdev->family > CHIP_RV200)
3054 WREG32(R_00015C_AGP_BASE_2, 0);
3055 }
3056 /* Wait for mc idle */
3057 if (r100_mc_wait_for_idle(rdev))
3058 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3059 /* Program MC, should be a 32bits limited address space */
3060 WREG32(R_000148_MC_FB_LOCATION,
3061 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3062 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3063 r100_mc_resume(rdev, &save);
3064 }
3065
3066 void r100_clock_startup(struct radeon_device *rdev)
3067 {
3068 u32 tmp;
3069
3070 if (radeon_dynclks != -1 && radeon_dynclks)
3071 radeon_legacy_set_clock_gating(rdev, 1);
3072 /* We need to force on some of the block */
3073 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3074 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3075 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3076 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3077 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3078 }
3079
3080 static int r100_startup(struct radeon_device *rdev)
3081 {
3082 int r;
3083
3084 r100_mc_program(rdev);
3085 /* Resume clock */
3086 r100_clock_startup(rdev);
3087 /* Initialize GPU configuration (# pipes, ...) */
3088 r100_gpu_init(rdev);
3089 /* Initialize GART (initialize after TTM so we can allocate
3090 * memory through TTM but finalize after TTM) */
3091 if (rdev->flags & RADEON_IS_PCI) {
3092 r = r100_pci_gart_enable(rdev);
3093 if (r)
3094 return r;
3095 }
3096 /* Enable IRQ */
3097 rdev->irq.sw_int = true;
3098 r100_irq_set(rdev);
3099 /* 1M ring buffer */
3100 r = r100_cp_init(rdev, 1024 * 1024);
3101 if (r) {
3102 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3103 return r;
3104 }
3105 r = r100_wb_init(rdev);
3106 if (r)
3107 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
3108 r = r100_ib_init(rdev);
3109 if (r) {
3110 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3111 return r;
3112 }
3113 return 0;
3114 }
3115
3116 int r100_resume(struct radeon_device *rdev)
3117 {
3118 /* Make sur GART are not working */
3119 if (rdev->flags & RADEON_IS_PCI)
3120 r100_pci_gart_disable(rdev);
3121 /* Resume clock before doing reset */
3122 r100_clock_startup(rdev);
3123 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3124 if (radeon_gpu_reset(rdev)) {
3125 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3126 RREG32(R_000E40_RBBM_STATUS),
3127 RREG32(R_0007C0_CP_STAT));
3128 }
3129 /* post */
3130 radeon_combios_asic_init(rdev->ddev);
3131 /* Resume clock after posting */
3132 r100_clock_startup(rdev);
3133 return r100_startup(rdev);
3134 }
3135
3136 int r100_suspend(struct radeon_device *rdev)
3137 {
3138 r100_cp_disable(rdev);
3139 r100_wb_disable(rdev);
3140 r100_irq_disable(rdev);
3141 if (rdev->flags & RADEON_IS_PCI)
3142 r100_pci_gart_disable(rdev);
3143 return 0;
3144 }
3145
3146 void r100_fini(struct radeon_device *rdev)
3147 {
3148 r100_suspend(rdev);
3149 r100_cp_fini(rdev);
3150 r100_wb_fini(rdev);
3151 r100_ib_fini(rdev);
3152 radeon_gem_fini(rdev);
3153 if (rdev->flags & RADEON_IS_PCI)
3154 r100_pci_gart_fini(rdev);
3155 radeon_irq_kms_fini(rdev);
3156 radeon_fence_driver_fini(rdev);
3157 radeon_object_fini(rdev);
3158 radeon_atombios_fini(rdev);
3159 kfree(rdev->bios);
3160 rdev->bios = NULL;
3161 }
3162
3163 int r100_mc_init(struct radeon_device *rdev)
3164 {
3165 int r;
3166 u32 tmp;
3167
3168 /* Setup GPU memory space */
3169 rdev->mc.vram_location = 0xFFFFFFFFUL;
3170 rdev->mc.gtt_location = 0xFFFFFFFFUL;
3171 if (rdev->flags & RADEON_IS_IGP) {
3172 tmp = G_00015C_MC_FB_START(RREG32(R_00015C_NB_TOM));
3173 rdev->mc.vram_location = tmp << 16;
3174 }
3175 if (rdev->flags & RADEON_IS_AGP) {
3176 r = radeon_agp_init(rdev);
3177 if (r) {
3178 printk(KERN_WARNING "[drm] Disabling AGP\n");
3179 rdev->flags &= ~RADEON_IS_AGP;
3180 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
3181 } else {
3182 rdev->mc.gtt_location = rdev->mc.agp_base;
3183 }
3184 }
3185 r = radeon_mc_setup(rdev);
3186 if (r)
3187 return r;
3188 return 0;
3189 }
3190
3191 int r100_init(struct radeon_device *rdev)
3192 {
3193 int r;
3194
3195 /* Register debugfs file specific to this group of asics */
3196 r100_debugfs(rdev);
3197 /* Disable VGA */
3198 r100_vga_render_disable(rdev);
3199 /* Initialize scratch registers */
3200 radeon_scratch_init(rdev);
3201 /* Initialize surface registers */
3202 radeon_surface_init(rdev);
3203 /* TODO: disable VGA need to use VGA request */
3204 /* BIOS*/
3205 if (!radeon_get_bios(rdev)) {
3206 if (ASIC_IS_AVIVO(rdev))
3207 return -EINVAL;
3208 }
3209 if (rdev->is_atom_bios) {
3210 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3211 return -EINVAL;
3212 } else {
3213 r = radeon_combios_init(rdev);
3214 if (r)
3215 return r;
3216 }
3217 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3218 if (radeon_gpu_reset(rdev)) {
3219 dev_warn(rdev->dev,
3220 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3221 RREG32(R_000E40_RBBM_STATUS),
3222 RREG32(R_0007C0_CP_STAT));
3223 }
3224 /* check if cards are posted or not */
3225 if (!radeon_card_posted(rdev) && rdev->bios) {
3226 DRM_INFO("GPU not posted. posting now...\n");
3227 radeon_combios_asic_init(rdev->ddev);
3228 }
3229 /* Set asic errata */
3230 r100_errata(rdev);
3231 /* Initialize clocks */
3232 radeon_get_clock_info(rdev->ddev);
3233 /* Get vram informations */
3234 r100_vram_info(rdev);
3235 /* Initialize memory controller (also test AGP) */
3236 r = r100_mc_init(rdev);
3237 if (r)
3238 return r;
3239 /* Fence driver */
3240 r = radeon_fence_driver_init(rdev);
3241 if (r)
3242 return r;
3243 r = radeon_irq_kms_init(rdev);
3244 if (r)
3245 return r;
3246 /* Memory manager */
3247 r = radeon_object_init(rdev);
3248 if (r)
3249 return r;
3250 if (rdev->flags & RADEON_IS_PCI) {
3251 r = r100_pci_gart_init(rdev);
3252 if (r)
3253 return r;
3254 }
3255 r100_set_safe_registers(rdev);
3256 rdev->accel_working = true;
3257 r = r100_startup(rdev);
3258 if (r) {
3259 /* Somethings want wront with the accel init stop accel */
3260 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3261 r100_suspend(rdev);
3262 r100_cp_fini(rdev);
3263 r100_wb_fini(rdev);
3264 r100_ib_fini(rdev);
3265 if (rdev->flags & RADEON_IS_PCI)
3266 r100_pci_gart_fini(rdev);
3267 radeon_irq_kms_fini(rdev);
3268 rdev->accel_working = false;
3269 }
3270 return 0;
3271 }
Linux for Ginger Game Console