drivers/gpu/drm/radeon/radeon.h

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #ifndef __RADEON_H__
  29 #define __RADEON_H__
  30
  31 #include "radeon_object.h"
  32
  33 /* TODO: Here are things that needs to be done :
  34  *      - surface allocator & initializer : (bit like scratch reg) should
  35  *        initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
  36  *        related to surface
  37  *      - WB : write back stuff (do it bit like scratch reg things)
  38  *      - Vblank : look at Jesse's rework and what we should do
  39  *      - r600/r700: gart & cp
  40  *      - cs : clean cs ioctl use bitmap & things like that.
  41  *      - power management stuff
  42  *      - Barrier in gart code
  43  *      - Unmappabled vram ?
  44  *      - TESTING, TESTING, TESTING
  45  */
  46
  47 /* Initialization path:
  48  *  We expect that acceleration initialization might fail for various
  49  *  reasons even thought we work hard to make it works on most
  50  *  configurations. In order to still have a working userspace in such
  51  *  situation the init path must succeed up to the memory controller
  52  *  initialization point. Failure before this point are considered as
  53  *  fatal error. Here is the init callchain :
  54  *      radeon_device_init  perform common structure, mutex initialization
  55  *      asic_init           setup the GPU memory layout and perform all
  56  *                          one time initialization (failure in this
  57  *                          function are considered fatal)
  58  *      asic_startup        setup the GPU acceleration, in order to
  59  *                          follow guideline the first thing this
  60  *                          function should do is setting the GPU
  61  *                          memory controller (only MC setup failure
  62  *                          are considered as fatal)
  63  */
  64
  65 #include <asm/atomic.h>
  66 #include <linux/wait.h>
  67 #include <linux/list.h>
  68 #include <linux/kref.h>
  69
  70 #include "radeon_family.h"
  71 #include "radeon_mode.h"
  72 #include "radeon_reg.h"
  73
  74 /*
  75  * Modules parameters.
  76  */
  77 extern int radeon_no_wb;
  78 extern int radeon_modeset;
  79 extern int radeon_dynclks;
  80 extern int radeon_r4xx_atom;
  81 extern int radeon_agpmode;
  82 extern int radeon_vram_limit;
  83 extern int radeon_gart_size;
  84 extern int radeon_benchmarking;
  85 extern int radeon_testing;
  86 extern int radeon_connector_table;
  87 extern int radeon_tv;
  88
  89 /*
  90  * Copy from radeon_drv.h so we don't have to include both and have conflicting
  91  * symbol;
  92  */
  93 #define RADEON_MAX_USEC_TIMEOUT         100000  /* 100 ms */
  94 #define RADEON_IB_POOL_SIZE             16
  95 #define RADEON_DEBUGFS_MAX_NUM_FILES    32
  96 #define RADEONFB_CONN_LIMIT             4
  97 #define RADEON_BIOS_NUM_SCRATCH         8
  98
  99 /*
 100  * Errata workarounds.
 101  */
 102 enum radeon_pll_errata {
 103         CHIP_ERRATA_R300_CG             = 0x00000001,
 104         CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
 105         CHIP_ERRATA_PLL_DELAY           = 0x00000004
 106 };
 107
 108
 109 struct radeon_device;
 110
 111
 112 /*
 113  * BIOS.
 114  */
 115 bool radeon_get_bios(struct radeon_device *rdev);
 116
 117
 118 /*
 119  * Dummy page
 120  */
 121 struct radeon_dummy_page {
 122         struct page     *page;
 123         dma_addr_t      addr;
 124 };
 125 int radeon_dummy_page_init(struct radeon_device *rdev);
 126 void radeon_dummy_page_fini(struct radeon_device *rdev);
 127
 128
 129 /*
 130  * Clocks
 131  */
 132 struct radeon_clock {
 133         struct radeon_pll p1pll;
 134         struct radeon_pll p2pll;
 135         struct radeon_pll spll;
 136         struct radeon_pll mpll;
 137         /* 10 Khz units */
 138         uint32_t default_mclk;
 139         uint32_t default_sclk;
 140 };
 141
 142
 143 /*
 144  * Fences.
 145  */
 146 struct radeon_fence_driver {
 147         uint32_t                        scratch_reg;
 148         atomic_t                        seq;
 149         uint32_t                        last_seq;
 150         unsigned long                   count_timeout;
 151         wait_queue_head_t               queue;
 152         rwlock_t                        lock;
 153         struct list_head                created;
 154         struct list_head                emited;
 155         struct list_head                signaled;
 156 };
 157
 158 struct radeon_fence {
 159         struct radeon_device            *rdev;
 160         struct kref                     kref;
 161         struct list_head                list;
 162         /* protected by radeon_fence.lock */
 163         uint32_t                        seq;
 164         unsigned long                   timeout;
 165         bool                            emited;
 166         bool                            signaled;
 167 };
 168
 169 int radeon_fence_driver_init(struct radeon_device *rdev);
 170 void radeon_fence_driver_fini(struct radeon_device *rdev);
 171 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
 172 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
 173 void radeon_fence_process(struct radeon_device *rdev);
 174 bool radeon_fence_signaled(struct radeon_fence *fence);
 175 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
 176 int radeon_fence_wait_next(struct radeon_device *rdev);
 177 int radeon_fence_wait_last(struct radeon_device *rdev);
 178 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
 179 void radeon_fence_unref(struct radeon_fence **fence);
 180
 181 /*
 182  * Tiling registers
 183  */
 184 struct radeon_surface_reg {
 185         struct radeon_object *robj;
 186 };
 187
 188 #define RADEON_GEM_MAX_SURFACES 8
 189
 190 /*
 191  * Radeon buffer.
 192  */
 193 struct radeon_object;
 194
 195 struct radeon_object_list {
 196         struct list_head        list;
 197         struct radeon_object    *robj;
 198         uint64_t                gpu_offset;
 199         unsigned                rdomain;
 200         unsigned                wdomain;
 201         uint32_t                tiling_flags;
 202 };
 203
 204 int radeon_object_init(struct radeon_device *rdev);
 205 void radeon_object_fini(struct radeon_device *rdev);
 206 int radeon_object_create(struct radeon_device *rdev,
 207                          struct drm_gem_object *gobj,
 208                          unsigned long size,
 209                          bool kernel,
 210                          uint32_t domain,
 211                          bool interruptible,
 212                          struct radeon_object **robj_ptr);
 213 int radeon_object_kmap(struct radeon_object *robj, void **ptr);
 214 void radeon_object_kunmap(struct radeon_object *robj);
 215 void radeon_object_unref(struct radeon_object **robj);
 216 int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
 217                       uint64_t *gpu_addr);
 218 void radeon_object_unpin(struct radeon_object *robj);
 219 int radeon_object_wait(struct radeon_object *robj);
 220 int radeon_object_busy_domain(struct radeon_object *robj, uint32_t *cur_placement);
 221 int radeon_object_evict_vram(struct radeon_device *rdev);
 222 int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset);
 223 void radeon_object_force_delete(struct radeon_device *rdev);
 224 void radeon_object_list_add_object(struct radeon_object_list *lobj,
 225                                    struct list_head *head);
 226 int radeon_object_list_validate(struct list_head *head, void *fence);
 227 void radeon_object_list_unvalidate(struct list_head *head);
 228 void radeon_object_list_clean(struct list_head *head);
 229 int radeon_object_fbdev_mmap(struct radeon_object *robj,
 230                              struct vm_area_struct *vma);
 231 unsigned long radeon_object_size(struct radeon_object *robj);
 232 void radeon_object_clear_surface_reg(struct radeon_object *robj);
 233 int radeon_object_check_tiling(struct radeon_object *robj, bool has_moved,
 234                                bool force_drop);
 235 void radeon_object_set_tiling_flags(struct radeon_object *robj,
 236                                     uint32_t tiling_flags, uint32_t pitch);
 237 void radeon_object_get_tiling_flags(struct radeon_object *robj, uint32_t *tiling_flags, uint32_t *pitch);
 238 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
 239                            struct ttm_mem_reg *mem);
 240 void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
 241 /*
 242  * GEM objects.
 243  */
 244 struct radeon_gem {
 245         struct list_head        objects;
 246 };
 247
 248 int radeon_gem_init(struct radeon_device *rdev);
 249 void radeon_gem_fini(struct radeon_device *rdev);
 250 int radeon_gem_object_create(struct radeon_device *rdev, int size,
 251                              int alignment, int initial_domain,
 252                              bool discardable, bool kernel,
 253                              bool interruptible,
 254                              struct drm_gem_object **obj);
 255 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
 256                           uint64_t *gpu_addr);
 257 void radeon_gem_object_unpin(struct drm_gem_object *obj);
 258
 259
 260 /*
 261  * GART structures, functions & helpers
 262  */
 263 struct radeon_mc;
 264
 265 struct radeon_gart_table_ram {
 266         volatile uint32_t               *ptr;
 267 };
 268
 269 struct radeon_gart_table_vram {
 270         struct radeon_object            *robj;
 271         volatile uint32_t               *ptr;
 272 };
 273
 274 union radeon_gart_table {
 275         struct radeon_gart_table_ram    ram;
 276         struct radeon_gart_table_vram   vram;
 277 };
 278
 279 struct radeon_gart {
 280         dma_addr_t                      table_addr;
 281         unsigned                        num_gpu_pages;
 282         unsigned                        num_cpu_pages;
 283         unsigned                        table_size;
 284         union radeon_gart_table         table;
 285         struct page                     **pages;
 286         dma_addr_t                      *pages_addr;
 287         bool                            ready;
 288 };
 289
 290 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
 291 void radeon_gart_table_ram_free(struct radeon_device *rdev);
 292 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
 293 void radeon_gart_table_vram_free(struct radeon_device *rdev);
 294 int radeon_gart_init(struct radeon_device *rdev);
 295 void radeon_gart_fini(struct radeon_device *rdev);
 296 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
 297                         int pages);
 298 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
 299                      int pages, struct page **pagelist);
 300
 301
 302 /*
 303  * GPU MC structures, functions & helpers
 304  */
 305 struct radeon_mc {
 306         resource_size_t         aper_size;
 307         resource_size_t         aper_base;
 308         resource_size_t         agp_base;
 309         /* for some chips with <= 32MB we need to lie
 310          * about vram size near mc fb location */
 311         u64                     mc_vram_size;
 312         u64                     gtt_location;
 313         u64                     gtt_size;
 314         u64                     gtt_start;
 315         u64                     gtt_end;
 316         u64                     vram_location;
 317         u64                     vram_start;
 318         u64                     vram_end;
 319         unsigned                vram_width;
 320         u64                     real_vram_size;
 321         int                     vram_mtrr;
 322         bool                    vram_is_ddr;
 323 };
 324
 325 int radeon_mc_setup(struct radeon_device *rdev);
 326
 327
 328 /*
 329  * GPU scratch registers structures, functions & helpers
 330  */
 331 struct radeon_scratch {
 332         unsigned                num_reg;
 333         bool                    free[32];
 334         uint32_t                reg[32];
 335 };
 336
 337 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
 338 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
 339
 340
 341 /*
 342  * IRQS.
 343  */
 344 struct radeon_irq {
 345         bool            installed;
 346         bool            sw_int;
 347         /* FIXME: use a define max crtc rather than hardcode it */
 348         bool            crtc_vblank_int[2];
 349 };
 350
 351 int radeon_irq_kms_init(struct radeon_device *rdev);
 352 void radeon_irq_kms_fini(struct radeon_device *rdev);
 353
 354
 355 /*
 356  * CP & ring.
 357  */
 358 struct radeon_ib {
 359         struct list_head        list;
 360         unsigned long           idx;
 361         uint64_t                gpu_addr;
 362         struct radeon_fence     *fence;
 363         uint32_t        *ptr;
 364         uint32_t                length_dw;
 365 };
 366
 367 /*
 368  * locking -
 369  * mutex protects scheduled_ibs, ready, alloc_bm
 370  */
 371 struct radeon_ib_pool {
 372         struct mutex            mutex;
 373         struct radeon_object    *robj;
 374         struct list_head        scheduled_ibs;
 375         struct radeon_ib        ibs[RADEON_IB_POOL_SIZE];
 376         bool                    ready;
 377         DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
 378 };
 379
 380 struct radeon_cp {
 381         struct radeon_object    *ring_obj;
 382         volatile uint32_t       *ring;
 383         unsigned                rptr;
 384         unsigned                wptr;
 385         unsigned                wptr_old;
 386         unsigned                ring_size;
 387         unsigned                ring_free_dw;
 388         int                     count_dw;
 389         uint64_t                gpu_addr;
 390         uint32_t                align_mask;
 391         uint32_t                ptr_mask;
 392         struct mutex            mutex;
 393         bool                    ready;
 394 };
 395
 396 struct r600_blit {
 397         struct radeon_object    *shader_obj;
 398         u64 shader_gpu_addr;
 399         u32 vs_offset, ps_offset;
 400         u32 state_offset;
 401         u32 state_len;
 402         u32 vb_used, vb_total;
 403         struct radeon_ib *vb_ib;
 404 };
 405
 406 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
 407 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
 408 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
 409 int radeon_ib_pool_init(struct radeon_device *rdev);
 410 void radeon_ib_pool_fini(struct radeon_device *rdev);
 411 int radeon_ib_test(struct radeon_device *rdev);
 412 /* Ring access between begin & end cannot sleep */
 413 void radeon_ring_free_size(struct radeon_device *rdev);
 414 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
 415 void radeon_ring_unlock_commit(struct radeon_device *rdev);
 416 void radeon_ring_unlock_undo(struct radeon_device *rdev);
 417 int radeon_ring_test(struct radeon_device *rdev);
 418 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
 419 void radeon_ring_fini(struct radeon_device *rdev);
 420
 421
 422 /*
 423  * CS.
 424  */
 425 struct radeon_cs_reloc {
 426         struct drm_gem_object           *gobj;
 427         struct radeon_object            *robj;
 428         struct radeon_object_list       lobj;
 429         uint32_t                        handle;
 430         uint32_t                        flags;
 431 };
 432
 433 struct radeon_cs_chunk {
 434         uint32_t                chunk_id;
 435         uint32_t                length_dw;
 436         int kpage_idx[2];
 437         uint32_t                *kpage[2];
 438         uint32_t                *kdata;
 439         void __user *user_ptr;
 440         int last_copied_page;
 441         int last_page_index;
 442 };
 443
 444 struct radeon_cs_parser {
 445         struct radeon_device    *rdev;
 446         struct drm_file         *filp;
 447         /* chunks */
 448         unsigned                nchunks;
 449         struct radeon_cs_chunk  *chunks;
 450         uint64_t                *chunks_array;
 451         /* IB */
 452         unsigned                idx;
 453         /* relocations */
 454         unsigned                nrelocs;
 455         struct radeon_cs_reloc  *relocs;
 456         struct radeon_cs_reloc  **relocs_ptr;
 457         struct list_head        validated;
 458         /* indices of various chunks */
 459         int                     chunk_ib_idx;
 460         int                     chunk_relocs_idx;
 461         struct radeon_ib        *ib;
 462         void                    *track;
 463         unsigned                family;
 464         int parser_error;
 465 };
 466
 467 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
 468 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
 469
 470
 471 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
 472 {
 473         struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
 474         u32 pg_idx, pg_offset;
 475         u32 idx_value = 0;
 476         int new_page;
 477
 478         pg_idx = (idx * 4) / PAGE_SIZE;
 479         pg_offset = (idx * 4) % PAGE_SIZE;
 480
 481         if (ibc->kpage_idx[0] == pg_idx)
 482                 return ibc->kpage[0][pg_offset/4];
 483         if (ibc->kpage_idx[1] == pg_idx)
 484                 return ibc->kpage[1][pg_offset/4];
 485
 486         new_page = radeon_cs_update_pages(p, pg_idx);
 487         if (new_page < 0) {
 488                 p->parser_error = new_page;
 489                 return 0;
 490         }
 491
 492         idx_value = ibc->kpage[new_page][pg_offset/4];
 493         return idx_value;
 494 }
 495
 496 struct radeon_cs_packet {
 497         unsigned        idx;
 498         unsigned        type;
 499         unsigned        reg;
 500         unsigned        opcode;
 501         int             count;
 502         unsigned        one_reg_wr;
 503 };
 504
 505 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
 506                                       struct radeon_cs_packet *pkt,
 507                                       unsigned idx, unsigned reg);
 508 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
 509                                       struct radeon_cs_packet *pkt);
 510
 511
 512 /*
 513  * AGP
 514  */
 515 int radeon_agp_init(struct radeon_device *rdev);
 516 void radeon_agp_fini(struct radeon_device *rdev);
 517
 518
 519 /*
 520  * Writeback
 521  */
 522 struct radeon_wb {
 523         struct radeon_object    *wb_obj;
 524         volatile uint32_t       *wb;
 525         uint64_t                gpu_addr;
 526 };
 527
 528 /**
 529  * struct radeon_pm - power management datas
 530  * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
 531  * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
 532  * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
 533  * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
 534  * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
 535  * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
 536  * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
 537  * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
 538  * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
 539  * @sclk:               GPU clock Mhz (core bandwith depends of this clock)
 540  * @needed_bandwidth:   current bandwidth needs
 541  *
 542  * It keeps track of various data needed to take powermanagement decision.
 543  * Bandwith need is used to determine minimun clock of the GPU and memory.
 544  * Equation between gpu/memory clock and available bandwidth is hw dependent
 545  * (type of memory, bus size, efficiency, ...)
 546  */
 547 struct radeon_pm {
 548         fixed20_12              max_bandwidth;
 549         fixed20_12              igp_sideport_mclk;
 550         fixed20_12              igp_system_mclk;
 551         fixed20_12              igp_ht_link_clk;
 552         fixed20_12              igp_ht_link_width;
 553         fixed20_12              k8_bandwidth;
 554         fixed20_12              sideport_bandwidth;
 555         fixed20_12              ht_bandwidth;
 556         fixed20_12              core_bandwidth;
 557         fixed20_12              sclk;
 558         fixed20_12              needed_bandwidth;
 559 };
 560
 561
 562 /*
 563  * Benchmarking
 564  */
 565 void radeon_benchmark(struct radeon_device *rdev);
 566
 567
 568 /*
 569  * Testing
 570  */
 571 void radeon_test_moves(struct radeon_device *rdev);
 572
 573
 574 /*
 575  * Debugfs
 576  */
 577 int radeon_debugfs_add_files(struct radeon_device *rdev,
 578                              struct drm_info_list *files,
 579                              unsigned nfiles);
 580 int radeon_debugfs_fence_init(struct radeon_device *rdev);
 581 int r100_debugfs_rbbm_init(struct radeon_device *rdev);
 582 int r100_debugfs_cp_init(struct radeon_device *rdev);
 583
 584
 585 /*
 586  * ASIC specific functions.
 587  */
 588 struct radeon_asic {
 589         int (*init)(struct radeon_device *rdev);
 590         void (*fini)(struct radeon_device *rdev);
 591         int (*resume)(struct radeon_device *rdev);
 592         int (*suspend)(struct radeon_device *rdev);
 593         void (*vga_set_state)(struct radeon_device *rdev, bool state);
 594         int (*gpu_reset)(struct radeon_device *rdev);
 595         void (*gart_tlb_flush)(struct radeon_device *rdev);
 596         int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
 597         int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
 598         void (*cp_fini)(struct radeon_device *rdev);
 599         void (*cp_disable)(struct radeon_device *rdev);
 600         void (*cp_commit)(struct radeon_device *rdev);
 601         void (*ring_start)(struct radeon_device *rdev);
 602         int (*ring_test)(struct radeon_device *rdev);
 603         void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
 604         int (*irq_set)(struct radeon_device *rdev);
 605         int (*irq_process)(struct radeon_device *rdev);
 606         u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
 607         void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
 608         int (*cs_parse)(struct radeon_cs_parser *p);
 609         int (*copy_blit)(struct radeon_device *rdev,
 610                          uint64_t src_offset,
 611                          uint64_t dst_offset,
 612                          unsigned num_pages,
 613                          struct radeon_fence *fence);
 614         int (*copy_dma)(struct radeon_device *rdev,
 615                         uint64_t src_offset,
 616                         uint64_t dst_offset,
 617                         unsigned num_pages,
 618                         struct radeon_fence *fence);
 619         int (*copy)(struct radeon_device *rdev,
 620                     uint64_t src_offset,
 621                     uint64_t dst_offset,
 622                     unsigned num_pages,
 623                     struct radeon_fence *fence);
 624         void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
 625         void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
 626         void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
 627         void (*set_clock_gating)(struct radeon_device *rdev, int enable);
 628         int (*set_surface_reg)(struct radeon_device *rdev, int reg,
 629                                uint32_t tiling_flags, uint32_t pitch,
 630                                uint32_t offset, uint32_t obj_size);
 631         int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
 632         void (*bandwidth_update)(struct radeon_device *rdev);
 633 };
 634
 635 /*
 636  * Asic structures
 637  */
 638 struct r100_asic {
 639         const unsigned  *reg_safe_bm;
 640         unsigned        reg_safe_bm_size;
 641 };
 642
 643 struct r300_asic {
 644         const unsigned  *reg_safe_bm;
 645         unsigned        reg_safe_bm_size;
 646 };
 647
 648 struct r600_asic {
 649         unsigned max_pipes;
 650         unsigned max_tile_pipes;
 651         unsigned max_simds;
 652         unsigned max_backends;
 653         unsigned max_gprs;
 654         unsigned max_threads;
 655         unsigned max_stack_entries;
 656         unsigned max_hw_contexts;
 657         unsigned max_gs_threads;
 658         unsigned sx_max_export_size;
 659         unsigned sx_max_export_pos_size;
 660         unsigned sx_max_export_smx_size;
 661         unsigned sq_num_cf_insts;
 662 };
 663
 664 struct rv770_asic {
 665         unsigned max_pipes;
 666         unsigned max_tile_pipes;
 667         unsigned max_simds;
 668         unsigned max_backends;
 669         unsigned max_gprs;
 670         unsigned max_threads;
 671         unsigned max_stack_entries;
 672         unsigned max_hw_contexts;
 673         unsigned max_gs_threads;
 674         unsigned sx_max_export_size;
 675         unsigned sx_max_export_pos_size;
 676         unsigned sx_max_export_smx_size;
 677         unsigned sq_num_cf_insts;
 678         unsigned sx_num_of_sets;
 679         unsigned sc_prim_fifo_size;
 680         unsigned sc_hiz_tile_fifo_size;
 681         unsigned sc_earlyz_tile_fifo_fize;
 682 };
 683
 684 union radeon_asic_config {
 685         struct r300_asic        r300;
 686         struct r100_asic        r100;
 687         struct r600_asic        r600;
 688         struct rv770_asic       rv770;
 689 };
 690
 691
 692 /*
 693  * IOCTL.
 694  */
 695 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
 696                           struct drm_file *filp);
 697 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
 698                             struct drm_file *filp);
 699 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
 700                          struct drm_file *file_priv);
 701 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
 702                            struct drm_file *file_priv);
 703 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 704                             struct drm_file *file_priv);
 705 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
 706                            struct drm_file *file_priv);
 707 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 708                                 struct drm_file *filp);
 709 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
 710                           struct drm_file *filp);
 711 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
 712                           struct drm_file *filp);
 713 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
 714                               struct drm_file *filp);
 715 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
 716 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
 717                                 struct drm_file *filp);
 718 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
 719                                 struct drm_file *filp);
 720
 721
 722 /*
 723  * Core structure, functions and helpers.
 724  */
 725 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
 726 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
 727
 728 struct radeon_device {
 729         struct device                   *dev;
 730         struct drm_device               *ddev;
 731         struct pci_dev                  *pdev;
 732         /* ASIC */
 733         union radeon_asic_config        config;
 734         enum radeon_family              family;
 735         unsigned long                   flags;
 736         int                             usec_timeout;
 737         enum radeon_pll_errata          pll_errata;
 738         int                             num_gb_pipes;
 739         int                             num_z_pipes;
 740         int                             disp_priority;
 741         /* BIOS */
 742         uint8_t                         *bios;
 743         bool                            is_atom_bios;
 744         uint16_t                        bios_header_start;
 745         struct radeon_object            *stollen_vga_memory;
 746         struct fb_info                  *fbdev_info;
 747         struct radeon_object            *fbdev_robj;
 748         struct radeon_framebuffer       *fbdev_rfb;
 749         /* Register mmio */
 750         resource_size_t                 rmmio_base;
 751         resource_size_t                 rmmio_size;
 752         void                            *rmmio;
 753         radeon_rreg_t                   mc_rreg;
 754         radeon_wreg_t                   mc_wreg;
 755         radeon_rreg_t                   pll_rreg;
 756         radeon_wreg_t                   pll_wreg;
 757         uint32_t                        pcie_reg_mask;
 758         radeon_rreg_t                   pciep_rreg;
 759         radeon_wreg_t                   pciep_wreg;
 760         struct radeon_clock             clock;
 761         struct radeon_mc                mc;
 762         struct radeon_gart              gart;
 763         struct radeon_mode_info         mode_info;
 764         struct radeon_scratch           scratch;
 765         struct radeon_mman              mman;
 766         struct radeon_fence_driver      fence_drv;
 767         struct radeon_cp                cp;
 768         struct radeon_ib_pool           ib_pool;
 769         struct radeon_irq               irq;
 770         struct radeon_asic              *asic;
 771         struct radeon_gem               gem;
 772         struct radeon_pm                pm;
 773         uint32_t                        bios_scratch[RADEON_BIOS_NUM_SCRATCH];
 774         struct mutex                    cs_mutex;
 775         struct radeon_wb                wb;
 776         struct radeon_dummy_page        dummy_page;
 777         bool                            gpu_lockup;
 778         bool                            shutdown;
 779         bool                            suspend;
 780         bool                            need_dma32;
 781         bool                            accel_working;
 782         struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
 783         const struct firmware *me_fw;   /* all family ME firmware */
 784         const struct firmware *pfp_fw;  /* r6/700 PFP firmware */
 785         struct r600_blit r600_blit;
 786 };
 787
 788 int radeon_device_init(struct radeon_device *rdev,
 789                        struct drm_device *ddev,
 790                        struct pci_dev *pdev,
 791                        uint32_t flags);
 792 void radeon_device_fini(struct radeon_device *rdev);
 793 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
 794
 795 /* r600 blit */
 796 int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
 797 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
 798 void r600_kms_blit_copy(struct radeon_device *rdev,
 799                         u64 src_gpu_addr, u64 dst_gpu_addr,
 800                         int size_bytes);
 801
 802 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
 803 {
 804         if (reg < 0x10000)
 805                 return readl(((void __iomem *)rdev->rmmio) + reg);
 806         else {
 807                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
 808                 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
 809         }
 810 }
 811
 812 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 813 {
 814         if (reg < 0x10000)
 815                 writel(v, ((void __iomem *)rdev->rmmio) + reg);
 816         else {
 817                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
 818                 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
 819         }
 820 }
 821
 822
 823 /*
 824  * Registers read & write functions.
 825  */
 826 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
 827 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
 828 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
 829 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
 830 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
 831 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
 832 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
 833 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
 834 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
 835 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
 836 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
 837 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
 838 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
 839 #define WREG32_P(reg, val, mask)                                \
 840         do {                                                    \
 841                 uint32_t tmp_ = RREG32(reg);                    \
 842                 tmp_ &= (mask);                                 \
 843                 tmp_ |= ((val) & ~(mask));                      \
 844                 WREG32(reg, tmp_);                              \
 845         } while (0)
 846 #define WREG32_PLL_P(reg, val, mask)                            \
 847         do {                                                    \
 848                 uint32_t tmp_ = RREG32_PLL(reg);                \
 849                 tmp_ &= (mask);                                 \
 850                 tmp_ |= ((val) & ~(mask));                      \
 851                 WREG32_PLL(reg, tmp_);                          \
 852         } while (0)
 853 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
 854
 855 /*
 856  * Indirect registers accessor
 857  */
 858 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
 859 {
 860         uint32_t r;
 861
 862         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
 863         r = RREG32(RADEON_PCIE_DATA);
 864         return r;
 865 }
 866
 867 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 868 {
 869         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
 870         WREG32(RADEON_PCIE_DATA, (v));
 871 }
 872
 873 void r100_pll_errata_after_index(struct radeon_device *rdev);
 874
 875
 876 /*
 877  * ASICs helpers.
 878  */
 879 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
 880                             (rdev->pdev->device == 0x5969))
 881 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
 882                 (rdev->family == CHIP_RV200) || \
 883                 (rdev->family == CHIP_RS100) || \
 884                 (rdev->family == CHIP_RS200) || \
 885                 (rdev->family == CHIP_RV250) || \
 886                 (rdev->family == CHIP_RV280) || \
 887                 (rdev->family == CHIP_RS300))
 888 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  ||     \
 889                 (rdev->family == CHIP_RV350) ||                 \
 890                 (rdev->family == CHIP_R350)  ||                 \
 891                 (rdev->family == CHIP_RV380) ||                 \
 892                 (rdev->family == CHIP_R420)  ||                 \
 893                 (rdev->family == CHIP_R423)  ||                 \
 894                 (rdev->family == CHIP_RV410) ||                 \
 895                 (rdev->family == CHIP_RS400) ||                 \
 896                 (rdev->family == CHIP_RS480))
 897 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
 898 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
 899 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
 900
 901
 902 /*
 903  * BIOS helpers.
 904  */
 905 #define RBIOS8(i) (rdev->bios[i])
 906 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
 907 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
 908
 909 int radeon_combios_init(struct radeon_device *rdev);
 910 void radeon_combios_fini(struct radeon_device *rdev);
 911 int radeon_atombios_init(struct radeon_device *rdev);
 912 void radeon_atombios_fini(struct radeon_device *rdev);
 913
 914
 915 /*
 916  * RING helpers.
 917  */
 918 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
 919 {
 920 #if DRM_DEBUG_CODE
 921         if (rdev->cp.count_dw <= 0) {
 922                 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
 923         }
 924 #endif
 925         rdev->cp.ring[rdev->cp.wptr++] = v;
 926         rdev->cp.wptr &= rdev->cp.ptr_mask;
 927         rdev->cp.count_dw--;
 928         rdev->cp.ring_free_dw--;
 929 }
 930
 931
 932 /*
 933  * ASICs macro.
 934  */
 935 #define radeon_init(rdev) (rdev)->asic->init((rdev))
 936 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
 937 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
 938 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
 939 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
 940 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
 941 #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
 942 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
 943 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
 944 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
 945 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
 946 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
 947 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
 948 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
 949 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
 950 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
 951 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
 952 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
 953 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
 954 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
 955 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
 956 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
 957 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
 958 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
 959 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
 960 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
 961 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
 962
 963 /* Common functions */
 964 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
 965 extern int radeon_modeset_init(struct radeon_device *rdev);
 966 extern void radeon_modeset_fini(struct radeon_device *rdev);
 967 extern bool radeon_card_posted(struct radeon_device *rdev);
 968 extern int radeon_clocks_init(struct radeon_device *rdev);
 969 extern void radeon_clocks_fini(struct radeon_device *rdev);
 970 extern void radeon_scratch_init(struct radeon_device *rdev);
 971 extern void radeon_surface_init(struct radeon_device *rdev);
 972 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
 973 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
 974 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
 975
 976 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
 977 struct r100_mc_save {
 978         u32     GENMO_WT;
 979         u32     CRTC_EXT_CNTL;
 980         u32     CRTC_GEN_CNTL;
 981         u32     CRTC2_GEN_CNTL;
 982         u32     CUR_OFFSET;
 983         u32     CUR2_OFFSET;
 984 };
 985 extern void r100_cp_disable(struct radeon_device *rdev);
 986 extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
 987 extern void r100_cp_fini(struct radeon_device *rdev);
 988 extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
 989 extern int r100_pci_gart_init(struct radeon_device *rdev);
 990 extern void r100_pci_gart_fini(struct radeon_device *rdev);
 991 extern int r100_pci_gart_enable(struct radeon_device *rdev);
 992 extern void r100_pci_gart_disable(struct radeon_device *rdev);
 993 extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
 994 extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
 995 extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
 996 extern void r100_ib_fini(struct radeon_device *rdev);
 997 extern int r100_ib_init(struct radeon_device *rdev);
 998 extern void r100_irq_disable(struct radeon_device *rdev);
 999 extern int r100_irq_set(struct radeon_device *rdev);
1000 extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
1001 extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
1002 extern void r100_vram_init_sizes(struct radeon_device *rdev);
1003 extern void r100_wb_disable(struct radeon_device *rdev);
1004 extern void r100_wb_fini(struct radeon_device *rdev);
1005 extern int r100_wb_init(struct radeon_device *rdev);
1006 extern void r100_hdp_reset(struct radeon_device *rdev);
1007 extern int r100_rb2d_reset(struct radeon_device *rdev);
1008 extern int r100_cp_reset(struct radeon_device *rdev);
1009 extern void r100_vga_render_disable(struct radeon_device *rdev);
1010 extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1011                                                 struct radeon_cs_packet *pkt,
1012                                                 struct radeon_object *robj);
1013 extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1014                                 struct radeon_cs_packet *pkt,
1015                                 const unsigned *auth, unsigned n,
1016                                 radeon_packet0_check_t check);
1017 extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
1018                                 struct radeon_cs_packet *pkt,
1019                                 unsigned idx);
1020
1021 /* rv200,rv250,rv280 */
1022 extern void r200_set_safe_registers(struct radeon_device *rdev);
1023
1024 /* r300,r350,rv350,rv370,rv380 */
1025 extern void r300_set_reg_safe(struct radeon_device *rdev);
1026 extern void r300_mc_program(struct radeon_device *rdev);
1027 extern void r300_vram_info(struct radeon_device *rdev);
1028 extern void r300_clock_startup(struct radeon_device *rdev);
1029 extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
1030 extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1031 extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1032 extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
1033 extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
1034
1035 /* r420,r423,rv410 */
1036 extern int r420_mc_init(struct radeon_device *rdev);
1037 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1038 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1039 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
1040 extern void r420_pipes_init(struct radeon_device *rdev);
1041
1042 /* rv515 */
1043 struct rv515_mc_save {
1044         u32 d1vga_control;
1045         u32 d2vga_control;
1046         u32 vga_render_control;
1047         u32 vga_hdp_control;
1048         u32 d1crtc_control;
1049         u32 d2crtc_control;
1050 };
1051 extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
1052 extern void rv515_vga_render_disable(struct radeon_device *rdev);
1053 extern void rv515_set_safe_registers(struct radeon_device *rdev);
1054 extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
1055 extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
1056 extern void rv515_clock_startup(struct radeon_device *rdev);
1057 extern void rv515_debugfs(struct radeon_device *rdev);
1058 extern int rv515_suspend(struct radeon_device *rdev);
1059
1060 /* rs400 */
1061 extern int rs400_gart_init(struct radeon_device *rdev);
1062 extern int rs400_gart_enable(struct radeon_device *rdev);
1063 extern void rs400_gart_adjust_size(struct radeon_device *rdev);
1064 extern void rs400_gart_disable(struct radeon_device *rdev);
1065 extern void rs400_gart_fini(struct radeon_device *rdev);
1066
1067 /* rs600 */
1068 extern void rs600_set_safe_registers(struct radeon_device *rdev);
1069 extern int rs600_irq_set(struct radeon_device *rdev);
1070 extern void rs600_irq_disable(struct radeon_device *rdev);
1071
1072 /* rs690, rs740 */
1073 extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1074                                         struct drm_display_mode *mode1,
1075                                         struct drm_display_mode *mode2);
1076
1077 /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1078 extern bool r600_card_posted(struct radeon_device *rdev);
1079 extern void r600_cp_stop(struct radeon_device *rdev);
1080 extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1081 extern int r600_cp_resume(struct radeon_device *rdev);
1082 extern int r600_count_pipe_bits(uint32_t val);
1083 extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
1084 extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
1085 extern int r600_pcie_gart_init(struct radeon_device *rdev);
1086 extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1087 extern int r600_ib_test(struct radeon_device *rdev);
1088 extern int r600_ring_test(struct radeon_device *rdev);
1089 extern void r600_wb_fini(struct radeon_device *rdev);
1090 extern int r600_wb_enable(struct radeon_device *rdev);
1091 extern void r600_wb_disable(struct radeon_device *rdev);
1092 extern void r600_scratch_init(struct radeon_device *rdev);
1093 extern int r600_blit_init(struct radeon_device *rdev);
1094 extern void r600_blit_fini(struct radeon_device *rdev);
1095 extern int r600_cp_init_microcode(struct radeon_device *rdev);
1096 extern int r600_gpu_reset(struct radeon_device *rdev);
1097
1098 #endif