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Full support for Ginger Console
[linux-ginger.git] / drivers / gpu / drm / radeon / rv515.c
blob41a34c23e6d8514b39d9f427ce59880a405cce04
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/seq_file.h>
29 #include "drmP.h"
30 #include "rv515d.h"
31 #include "radeon.h"
32 #include "atom.h"
33 #include "rv515_reg_safe.h"
34
35 /* This files gather functions specifics to: rv515 */
36 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
37 int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
38 void rv515_gpu_init(struct radeon_device *rdev);
39 int rv515_mc_wait_for_idle(struct radeon_device *rdev);
40
41 void rv515_debugfs(struct radeon_device *rdev)
42 {
43 if (r100_debugfs_rbbm_init(rdev)) {
44 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
45 }
46 if (rv515_debugfs_pipes_info_init(rdev)) {
47 DRM_ERROR("Failed to register debugfs file for pipes !\n");
48 }
49 if (rv515_debugfs_ga_info_init(rdev)) {
50 DRM_ERROR("Failed to register debugfs file for pipes !\n");
51 }
52 }
53
54 void rv515_ring_start(struct radeon_device *rdev)
55 {
56 int r;
57
58 r = radeon_ring_lock(rdev, 64);
59 if (r) {
60 return;
61 }
62 radeon_ring_write(rdev, PACKET0(ISYNC_CNTL, 0));
63 radeon_ring_write(rdev,
64 ISYNC_ANY2D_IDLE3D |
65 ISYNC_ANY3D_IDLE2D |
66 ISYNC_WAIT_IDLEGUI |
67 ISYNC_CPSCRATCH_IDLEGUI);
68 radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
69 radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
70 radeon_ring_write(rdev, PACKET0(0x170C, 0));
71 radeon_ring_write(rdev, 1 << 31);
72 radeon_ring_write(rdev, PACKET0(GB_SELECT, 0));
73 radeon_ring_write(rdev, 0);
74 radeon_ring_write(rdev, PACKET0(GB_ENABLE, 0));
75 radeon_ring_write(rdev, 0);
76 radeon_ring_write(rdev, PACKET0(0x42C8, 0));
77 radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1);
78 radeon_ring_write(rdev, PACKET0(VAP_INDEX_OFFSET, 0));
79 radeon_ring_write(rdev, 0);
80 radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
81 radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
82 radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
83 radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
84 radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
85 radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
86 radeon_ring_write(rdev, PACKET0(GB_AA_CONFIG, 0));
87 radeon_ring_write(rdev, 0);
88 radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
89 radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
90 radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
91 radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
92 radeon_ring_write(rdev, PACKET0(GB_MSPOS0, 0));
93 radeon_ring_write(rdev,
94 ((6 << MS_X0_SHIFT) |
95 (6 << MS_Y0_SHIFT) |
96 (6 << MS_X1_SHIFT) |
97 (6 << MS_Y1_SHIFT) |
98 (6 << MS_X2_SHIFT) |
99 (6 << MS_Y2_SHIFT) |
100 (6 << MSBD0_Y_SHIFT) |
101 (6 << MSBD0_X_SHIFT)));
102 radeon_ring_write(rdev, PACKET0(GB_MSPOS1, 0));
103 radeon_ring_write(rdev,
104 ((6 << MS_X3_SHIFT) |
105 (6 << MS_Y3_SHIFT) |
106 (6 << MS_X4_SHIFT) |
107 (6 << MS_Y4_SHIFT) |
108 (6 << MS_X5_SHIFT) |
109 (6 << MS_Y5_SHIFT) |
110 (6 << MSBD1_SHIFT)));
111 radeon_ring_write(rdev, PACKET0(GA_ENHANCE, 0));
112 radeon_ring_write(rdev, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
113 radeon_ring_write(rdev, PACKET0(GA_POLY_MODE, 0));
114 radeon_ring_write(rdev, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
115 radeon_ring_write(rdev, PACKET0(GA_ROUND_MODE, 0));
116 radeon_ring_write(rdev, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
117 radeon_ring_write(rdev, PACKET0(0x20C8, 0));
118 radeon_ring_write(rdev, 0);
119 radeon_ring_unlock_commit(rdev);
120 }
121
122 int rv515_mc_wait_for_idle(struct radeon_device *rdev)
123 {
124 unsigned i;
125 uint32_t tmp;
126
127 for (i = 0; i < rdev->usec_timeout; i++) {
128 /* read MC_STATUS */
129 tmp = RREG32_MC(MC_STATUS);
130 if (tmp & MC_STATUS_IDLE) {
131 return 0;
132 }
133 DRM_UDELAY(1);
134 }
135 return -1;
136 }
137
138 void rv515_vga_render_disable(struct radeon_device *rdev)
139 {
140 WREG32(R_000300_VGA_RENDER_CONTROL,
141 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
142 }
143
144 void rv515_gpu_init(struct radeon_device *rdev)
145 {
146 unsigned pipe_select_current, gb_pipe_select, tmp;
147
148 r100_hdp_reset(rdev);
149 r100_rb2d_reset(rdev);
150
151 if (r100_gui_wait_for_idle(rdev)) {
152 printk(KERN_WARNING "Failed to wait GUI idle while "
153 "reseting GPU. Bad things might happen.\n");
154 }
155
156 rv515_vga_render_disable(rdev);
157
158 r420_pipes_init(rdev);
159 gb_pipe_select = RREG32(0x402C);
160 tmp = RREG32(0x170C);
161 pipe_select_current = (tmp >> 2) & 3;
162 tmp = (1 << pipe_select_current) |
163 (((gb_pipe_select >> 8) & 0xF) << 4);
164 WREG32_PLL(0x000D, tmp);
165 if (r100_gui_wait_for_idle(rdev)) {
166 printk(KERN_WARNING "Failed to wait GUI idle while "
167 "reseting GPU. Bad things might happen.\n");
168 }
169 if (rv515_mc_wait_for_idle(rdev)) {
170 printk(KERN_WARNING "Failed to wait MC idle while "
171 "programming pipes. Bad things might happen.\n");
172 }
173 }
174
175 int rv515_ga_reset(struct radeon_device *rdev)
176 {
177 uint32_t tmp;
178 bool reinit_cp;
179 int i;
180
181 reinit_cp = rdev->cp.ready;
182 rdev->cp.ready = false;
183 for (i = 0; i < rdev->usec_timeout; i++) {
184 WREG32(CP_CSQ_MODE, 0);
185 WREG32(CP_CSQ_CNTL, 0);
186 WREG32(RBBM_SOFT_RESET, 0x32005);
187 (void)RREG32(RBBM_SOFT_RESET);
188 udelay(200);
189 WREG32(RBBM_SOFT_RESET, 0);
190 /* Wait to prevent race in RBBM_STATUS */
191 mdelay(1);
192 tmp = RREG32(RBBM_STATUS);
193 if (tmp & ((1 << 20) | (1 << 26))) {
194 DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)\n", tmp);
195 /* GA still busy soft reset it */
196 WREG32(0x429C, 0x200);
197 WREG32(VAP_PVS_STATE_FLUSH_REG, 0);
198 WREG32(0x43E0, 0);
199 WREG32(0x43E4, 0);
200 WREG32(0x24AC, 0);
201 }
202 /* Wait to prevent race in RBBM_STATUS */
203 mdelay(1);
204 tmp = RREG32(RBBM_STATUS);
205 if (!(tmp & ((1 << 20) | (1 << 26)))) {
206 break;
207 }
208 }
209 for (i = 0; i < rdev->usec_timeout; i++) {
210 tmp = RREG32(RBBM_STATUS);
211 if (!(tmp & ((1 << 20) | (1 << 26)))) {
212 DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
213 tmp);
214 DRM_INFO("GA_IDLE=0x%08X\n", RREG32(0x425C));
215 DRM_INFO("RB3D_RESET_STATUS=0x%08X\n", RREG32(0x46f0));
216 DRM_INFO("ISYNC_CNTL=0x%08X\n", RREG32(0x1724));
217 if (reinit_cp) {
218 return r100_cp_init(rdev, rdev->cp.ring_size);
219 }
220 return 0;
221 }
222 DRM_UDELAY(1);
223 }
224 tmp = RREG32(RBBM_STATUS);
225 DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
226 return -1;
227 }
228
229 int rv515_gpu_reset(struct radeon_device *rdev)
230 {
231 uint32_t status;
232
233 /* reset order likely matter */
234 status = RREG32(RBBM_STATUS);
235 /* reset HDP */
236 r100_hdp_reset(rdev);
237 /* reset rb2d */
238 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
239 r100_rb2d_reset(rdev);
240 }
241 /* reset GA */
242 if (status & ((1 << 20) | (1 << 26))) {
243 rv515_ga_reset(rdev);
244 }
245 /* reset CP */
246 status = RREG32(RBBM_STATUS);
247 if (status & (1 << 16)) {
248 r100_cp_reset(rdev);
249 }
250 /* Check if GPU is idle */
251 status = RREG32(RBBM_STATUS);
252 if (status & (1 << 31)) {
253 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
254 return -1;
255 }
256 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
257 return 0;
258 }
259
260 static void rv515_vram_get_type(struct radeon_device *rdev)
261 {
262 uint32_t tmp;
263
264 rdev->mc.vram_width = 128;
265 rdev->mc.vram_is_ddr = true;
266 tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
267 switch (tmp) {
268 case 0:
269 rdev->mc.vram_width = 64;
270 break;
271 case 1:
272 rdev->mc.vram_width = 128;
273 break;
274 default:
275 rdev->mc.vram_width = 128;
276 break;
277 }
278 }
279
280 void rv515_vram_info(struct radeon_device *rdev)
281 {
282 fixed20_12 a;
283
284 rv515_vram_get_type(rdev);
285
286 r100_vram_init_sizes(rdev);
287 /* FIXME: we should enforce default clock in case GPU is not in
288 * default setup
289 */
290 a.full = rfixed_const(100);
291 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
292 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
293 }
294
295 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
296 {
297 uint32_t r;
298
299 WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
300 r = RREG32(MC_IND_DATA);
301 WREG32(MC_IND_INDEX, 0);
302 return r;
303 }
304
305 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
306 {
307 WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
308 WREG32(MC_IND_DATA, (v));
309 WREG32(MC_IND_INDEX, 0);
310 }
311
312 #if defined(CONFIG_DEBUG_FS)
313 static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
314 {
315 struct drm_info_node *node = (struct drm_info_node *) m->private;
316 struct drm_device *dev = node->minor->dev;
317 struct radeon_device *rdev = dev->dev_private;
318 uint32_t tmp;
319
320 tmp = RREG32(GB_PIPE_SELECT);
321 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
322 tmp = RREG32(SU_REG_DEST);
323 seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
324 tmp = RREG32(GB_TILE_CONFIG);
325 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
326 tmp = RREG32(DST_PIPE_CONFIG);
327 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
328 return 0;
329 }
330
331 static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
332 {
333 struct drm_info_node *node = (struct drm_info_node *) m->private;
334 struct drm_device *dev = node->minor->dev;
335 struct radeon_device *rdev = dev->dev_private;
336 uint32_t tmp;
337
338 tmp = RREG32(0x2140);
339 seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
340 radeon_gpu_reset(rdev);
341 tmp = RREG32(0x425C);
342 seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
343 return 0;
344 }
345
346 static struct drm_info_list rv515_pipes_info_list[] = {
347 {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
348 };
349
350 static struct drm_info_list rv515_ga_info_list[] = {
351 {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
352 };
353 #endif
354
355 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
356 {
357 #if defined(CONFIG_DEBUG_FS)
358 return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
359 #else
360 return 0;
361 #endif
362 }
363
364 int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
365 {
366 #if defined(CONFIG_DEBUG_FS)
367 return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
368 #else
369 return 0;
370 #endif
371 }
372
373 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
374 {
375 save->d1vga_control = RREG32(R_000330_D1VGA_CONTROL);
376 save->d2vga_control = RREG32(R_000338_D2VGA_CONTROL);
377 save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
378 save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
379 save->d1crtc_control = RREG32(R_006080_D1CRTC_CONTROL);
380 save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL);
381
382 /* Stop all video */
383 WREG32(R_000330_D1VGA_CONTROL, 0);
384 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
385 WREG32(R_000300_VGA_RENDER_CONTROL, 0);
386 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
387 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
388 WREG32(R_006080_D1CRTC_CONTROL, 0);
389 WREG32(R_006880_D2CRTC_CONTROL, 0);
390 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
391 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
392 }
393
394 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
395 {
396 WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
397 WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
398 WREG32(R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
399 WREG32(R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
400 WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
401 /* Unlock host access */
402 WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
403 mdelay(1);
404 /* Restore video state */
405 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
406 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
407 WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control);
408 WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control);
409 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
410 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
411 WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control);
412 WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control);
413 WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
414 }
415
416 void rv515_mc_program(struct radeon_device *rdev)
417 {
418 struct rv515_mc_save save;
419
420 /* Stops all mc clients */
421 rv515_mc_stop(rdev, &save);
422
423 /* Wait for mc idle */
424 if (rv515_mc_wait_for_idle(rdev))
425 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
426 /* Write VRAM size in case we are limiting it */
427 WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
428 /* Program MC, should be a 32bits limited address space */
429 WREG32_MC(R_000001_MC_FB_LOCATION,
430 S_000001_MC_FB_START(rdev->mc.vram_start >> 16) |
431 S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16));
432 WREG32(R_000134_HDP_FB_LOCATION,
433 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
434 if (rdev->flags & RADEON_IS_AGP) {
435 WREG32_MC(R_000002_MC_AGP_LOCATION,
436 S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) |
437 S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
438 WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
439 WREG32_MC(R_000004_MC_AGP_BASE_2,
440 S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
441 } else {
442 WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF);
443 WREG32_MC(R_000003_MC_AGP_BASE, 0);
444 WREG32_MC(R_000004_MC_AGP_BASE_2, 0);
445 }
446
447 rv515_mc_resume(rdev, &save);
448 }
449
450 void rv515_clock_startup(struct radeon_device *rdev)
451 {
452 if (radeon_dynclks != -1 && radeon_dynclks)
453 radeon_atom_set_clock_gating(rdev, 1);
454 /* We need to force on some of the block */
455 WREG32_PLL(R_00000F_CP_DYN_CNTL,
456 RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1));
457 WREG32_PLL(R_000011_E2_DYN_CNTL,
458 RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1));
459 WREG32_PLL(R_000013_IDCT_DYN_CNTL,
460 RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1));
461 }
462
463 static int rv515_startup(struct radeon_device *rdev)
464 {
465 int r;
466
467 rv515_mc_program(rdev);
468 /* Resume clock */
469 rv515_clock_startup(rdev);
470 /* Initialize GPU configuration (# pipes, ...) */
471 rv515_gpu_init(rdev);
472 /* Initialize GART (initialize after TTM so we can allocate
473 * memory through TTM but finalize after TTM) */
474 if (rdev->flags & RADEON_IS_PCIE) {
475 r = rv370_pcie_gart_enable(rdev);
476 if (r)
477 return r;
478 }
479 /* Enable IRQ */
480 rdev->irq.sw_int = true;
481 rs600_irq_set(rdev);
482 /* 1M ring buffer */
483 r = r100_cp_init(rdev, 1024 * 1024);
484 if (r) {
485 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
486 return r;
487 }
488 r = r100_wb_init(rdev);
489 if (r)
490 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
491 r = r100_ib_init(rdev);
492 if (r) {
493 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
494 return r;
495 }
496 return 0;
497 }
498
499 int rv515_resume(struct radeon_device *rdev)
500 {
501 /* Make sur GART are not working */
502 if (rdev->flags & RADEON_IS_PCIE)
503 rv370_pcie_gart_disable(rdev);
504 /* Resume clock before doing reset */
505 rv515_clock_startup(rdev);
506 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
507 if (radeon_gpu_reset(rdev)) {
508 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
509 RREG32(R_000E40_RBBM_STATUS),
510 RREG32(R_0007C0_CP_STAT));
511 }
512 /* post */
513 atom_asic_init(rdev->mode_info.atom_context);
514 /* Resume clock after posting */
515 rv515_clock_startup(rdev);
516 return rv515_startup(rdev);
517 }
518
519 int rv515_suspend(struct radeon_device *rdev)
520 {
521 r100_cp_disable(rdev);
522 r100_wb_disable(rdev);
523 rs600_irq_disable(rdev);
524 if (rdev->flags & RADEON_IS_PCIE)
525 rv370_pcie_gart_disable(rdev);
526 return 0;
527 }
528
529 void rv515_set_safe_registers(struct radeon_device *rdev)
530 {
531 rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
532 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
533 }
534
535 void rv515_fini(struct radeon_device *rdev)
536 {
537 rv515_suspend(rdev);
538 r100_cp_fini(rdev);
539 r100_wb_fini(rdev);
540 r100_ib_fini(rdev);
541 radeon_gem_fini(rdev);
542 rv370_pcie_gart_fini(rdev);
543 radeon_agp_fini(rdev);
544 radeon_irq_kms_fini(rdev);
545 radeon_fence_driver_fini(rdev);
546 radeon_object_fini(rdev);
547 radeon_atombios_fini(rdev);
548 kfree(rdev->bios);
549 rdev->bios = NULL;
550 }
551
552 int rv515_init(struct radeon_device *rdev)
553 {
554 int r;
555
556 /* Initialize scratch registers */
557 radeon_scratch_init(rdev);
558 /* Initialize surface registers */
559 radeon_surface_init(rdev);
560 /* TODO: disable VGA need to use VGA request */
561 /* BIOS*/
562 if (!radeon_get_bios(rdev)) {
563 if (ASIC_IS_AVIVO(rdev))
564 return -EINVAL;
565 }
566 if (rdev->is_atom_bios) {
567 r = radeon_atombios_init(rdev);
568 if (r)
569 return r;
570 } else {
571 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
572 return -EINVAL;
573 }
574 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
575 if (radeon_gpu_reset(rdev)) {
576 dev_warn(rdev->dev,
577 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
578 RREG32(R_000E40_RBBM_STATUS),
579 RREG32(R_0007C0_CP_STAT));
580 }
581 /* check if cards are posted or not */
582 if (!radeon_card_posted(rdev) && rdev->bios) {
583 DRM_INFO("GPU not posted. posting now...\n");
584 atom_asic_init(rdev->mode_info.atom_context);
585 }
586 /* Initialize clocks */
587 radeon_get_clock_info(rdev->ddev);
588 /* Get vram informations */
589 rv515_vram_info(rdev);
590 /* Initialize memory controller (also test AGP) */
591 r = r420_mc_init(rdev);
592 if (r)
593 return r;
594 rv515_debugfs(rdev);
595 /* Fence driver */
596 r = radeon_fence_driver_init(rdev);
597 if (r)
598 return r;
599 r = radeon_irq_kms_init(rdev);
600 if (r)
601 return r;
602 /* Memory manager */
603 r = radeon_object_init(rdev);
604 if (r)
605 return r;
606 r = rv370_pcie_gart_init(rdev);
607 if (r)
608 return r;
609 rv515_set_safe_registers(rdev);
610 rdev->accel_working = true;
611 r = rv515_startup(rdev);
612 if (r) {
613 /* Somethings want wront with the accel init stop accel */
614 dev_err(rdev->dev, "Disabling GPU acceleration\n");
615 rv515_suspend(rdev);
616 r100_cp_fini(rdev);
617 r100_wb_fini(rdev);
618 r100_ib_fini(rdev);
619 rv370_pcie_gart_fini(rdev);
620 radeon_agp_fini(rdev);
621 radeon_irq_kms_fini(rdev);
622 rdev->accel_working = false;
623 }
624 return 0;
625 }
626
627 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)
628 {
629 int index_reg = 0x6578 + crtc->crtc_offset;
630 int data_reg = 0x657c + crtc->crtc_offset;
631
632 WREG32(0x659C + crtc->crtc_offset, 0x0);
633 WREG32(0x6594 + crtc->crtc_offset, 0x705);
634 WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
635 WREG32(0x65D8 + crtc->crtc_offset, 0x0);
636 WREG32(0x65B0 + crtc->crtc_offset, 0x0);
637 WREG32(0x65C0 + crtc->crtc_offset, 0x0);
638 WREG32(0x65D4 + crtc->crtc_offset, 0x0);
639 WREG32(index_reg, 0x0);
640 WREG32(data_reg, 0x841880A8);
641 WREG32(index_reg, 0x1);
642 WREG32(data_reg, 0x84208680);
643 WREG32(index_reg, 0x2);
644 WREG32(data_reg, 0xBFF880B0);
645 WREG32(index_reg, 0x100);
646 WREG32(data_reg, 0x83D88088);
647 WREG32(index_reg, 0x101);
648 WREG32(data_reg, 0x84608680);
649 WREG32(index_reg, 0x102);
650 WREG32(data_reg, 0xBFF080D0);
651 WREG32(index_reg, 0x200);
652 WREG32(data_reg, 0x83988068);
653 WREG32(index_reg, 0x201);
654 WREG32(data_reg, 0x84A08680);
655 WREG32(index_reg, 0x202);
656 WREG32(data_reg, 0xBFF080F8);
657 WREG32(index_reg, 0x300);
658 WREG32(data_reg, 0x83588058);
659 WREG32(index_reg, 0x301);
660 WREG32(data_reg, 0x84E08660);
661 WREG32(index_reg, 0x302);
662 WREG32(data_reg, 0xBFF88120);
663 WREG32(index_reg, 0x400);
664 WREG32(data_reg, 0x83188040);
665 WREG32(index_reg, 0x401);
666 WREG32(data_reg, 0x85008660);
667 WREG32(index_reg, 0x402);
668 WREG32(data_reg, 0xBFF88150);
669 WREG32(index_reg, 0x500);
670 WREG32(data_reg, 0x82D88030);
671 WREG32(index_reg, 0x501);
672 WREG32(data_reg, 0x85408640);
673 WREG32(index_reg, 0x502);
674 WREG32(data_reg, 0xBFF88180);
675 WREG32(index_reg, 0x600);
676 WREG32(data_reg, 0x82A08018);
677 WREG32(index_reg, 0x601);
678 WREG32(data_reg, 0x85808620);
679 WREG32(index_reg, 0x602);
680 WREG32(data_reg, 0xBFF081B8);
681 WREG32(index_reg, 0x700);
682 WREG32(data_reg, 0x82608010);
683 WREG32(index_reg, 0x701);
684 WREG32(data_reg, 0x85A08600);
685 WREG32(index_reg, 0x702);
686 WREG32(data_reg, 0x800081F0);
687 WREG32(index_reg, 0x800);
688 WREG32(data_reg, 0x8228BFF8);
689 WREG32(index_reg, 0x801);
690 WREG32(data_reg, 0x85E085E0);
691 WREG32(index_reg, 0x802);
692 WREG32(data_reg, 0xBFF88228);
693 WREG32(index_reg, 0x10000);
694 WREG32(data_reg, 0x82A8BF00);
695 WREG32(index_reg, 0x10001);
696 WREG32(data_reg, 0x82A08CC0);
697 WREG32(index_reg, 0x10002);
698 WREG32(data_reg, 0x8008BEF8);
699 WREG32(index_reg, 0x10100);
700 WREG32(data_reg, 0x81F0BF28);
701 WREG32(index_reg, 0x10101);
702 WREG32(data_reg, 0x83608CA0);
703 WREG32(index_reg, 0x10102);
704 WREG32(data_reg, 0x8018BED0);
705 WREG32(index_reg, 0x10200);
706 WREG32(data_reg, 0x8148BF38);
707 WREG32(index_reg, 0x10201);
708 WREG32(data_reg, 0x84408C80);
709 WREG32(index_reg, 0x10202);
710 WREG32(data_reg, 0x8008BEB8);
711 WREG32(index_reg, 0x10300);
712 WREG32(data_reg, 0x80B0BF78);
713 WREG32(index_reg, 0x10301);
714 WREG32(data_reg, 0x85008C20);
715 WREG32(index_reg, 0x10302);
716 WREG32(data_reg, 0x8020BEA0);
717 WREG32(index_reg, 0x10400);
718 WREG32(data_reg, 0x8028BF90);
719 WREG32(index_reg, 0x10401);
720 WREG32(data_reg, 0x85E08BC0);
721 WREG32(index_reg, 0x10402);
722 WREG32(data_reg, 0x8018BE90);
723 WREG32(index_reg, 0x10500);
724 WREG32(data_reg, 0xBFB8BFB0);
725 WREG32(index_reg, 0x10501);
726 WREG32(data_reg, 0x86C08B40);
727 WREG32(index_reg, 0x10502);
728 WREG32(data_reg, 0x8010BE90);
729 WREG32(index_reg, 0x10600);
730 WREG32(data_reg, 0xBF58BFC8);
731 WREG32(index_reg, 0x10601);
732 WREG32(data_reg, 0x87A08AA0);
733 WREG32(index_reg, 0x10602);
734 WREG32(data_reg, 0x8010BE98);
735 WREG32(index_reg, 0x10700);
736 WREG32(data_reg, 0xBF10BFF0);
737 WREG32(index_reg, 0x10701);
738 WREG32(data_reg, 0x886089E0);
739 WREG32(index_reg, 0x10702);
740 WREG32(data_reg, 0x8018BEB0);
741 WREG32(index_reg, 0x10800);
742 WREG32(data_reg, 0xBED8BFE8);
743 WREG32(index_reg, 0x10801);
744 WREG32(data_reg, 0x89408940);
745 WREG32(index_reg, 0x10802);
746 WREG32(data_reg, 0xBFE8BED8);
747 WREG32(index_reg, 0x20000);
748 WREG32(data_reg, 0x80008000);
749 WREG32(index_reg, 0x20001);
750 WREG32(data_reg, 0x90008000);
751 WREG32(index_reg, 0x20002);
752 WREG32(data_reg, 0x80008000);
753 WREG32(index_reg, 0x20003);
754 WREG32(data_reg, 0x80008000);
755 WREG32(index_reg, 0x20100);
756 WREG32(data_reg, 0x80108000);
757 WREG32(index_reg, 0x20101);
758 WREG32(data_reg, 0x8FE0BF70);
759 WREG32(index_reg, 0x20102);
760 WREG32(data_reg, 0xBFE880C0);
761 WREG32(index_reg, 0x20103);
762 WREG32(data_reg, 0x80008000);
763 WREG32(index_reg, 0x20200);
764 WREG32(data_reg, 0x8018BFF8);
765 WREG32(index_reg, 0x20201);
766 WREG32(data_reg, 0x8F80BF08);
767 WREG32(index_reg, 0x20202);
768 WREG32(data_reg, 0xBFD081A0);
769 WREG32(index_reg, 0x20203);
770 WREG32(data_reg, 0xBFF88000);
771 WREG32(index_reg, 0x20300);
772 WREG32(data_reg, 0x80188000);
773 WREG32(index_reg, 0x20301);
774 WREG32(data_reg, 0x8EE0BEC0);
775 WREG32(index_reg, 0x20302);
776 WREG32(data_reg, 0xBFB082A0);
777 WREG32(index_reg, 0x20303);
778 WREG32(data_reg, 0x80008000);
779 WREG32(index_reg, 0x20400);
780 WREG32(data_reg, 0x80188000);
781 WREG32(index_reg, 0x20401);
782 WREG32(data_reg, 0x8E00BEA0);
783 WREG32(index_reg, 0x20402);
784 WREG32(data_reg, 0xBF8883C0);
785 WREG32(index_reg, 0x20403);
786 WREG32(data_reg, 0x80008000);
787 WREG32(index_reg, 0x20500);
788 WREG32(data_reg, 0x80188000);
789 WREG32(index_reg, 0x20501);
790 WREG32(data_reg, 0x8D00BE90);
791 WREG32(index_reg, 0x20502);
792 WREG32(data_reg, 0xBF588500);
793 WREG32(index_reg, 0x20503);
794 WREG32(data_reg, 0x80008008);
795 WREG32(index_reg, 0x20600);
796 WREG32(data_reg, 0x80188000);
797 WREG32(index_reg, 0x20601);
798 WREG32(data_reg, 0x8BC0BE98);
799 WREG32(index_reg, 0x20602);
800 WREG32(data_reg, 0xBF308660);
801 WREG32(index_reg, 0x20603);
802 WREG32(data_reg, 0x80008008);
803 WREG32(index_reg, 0x20700);
804 WREG32(data_reg, 0x80108000);
805 WREG32(index_reg, 0x20701);
806 WREG32(data_reg, 0x8A80BEB0);
807 WREG32(index_reg, 0x20702);
808 WREG32(data_reg, 0xBF0087C0);
809 WREG32(index_reg, 0x20703);
810 WREG32(data_reg, 0x80008008);
811 WREG32(index_reg, 0x20800);
812 WREG32(data_reg, 0x80108000);
813 WREG32(index_reg, 0x20801);
814 WREG32(data_reg, 0x8920BED0);
815 WREG32(index_reg, 0x20802);
816 WREG32(data_reg, 0xBED08920);
817 WREG32(index_reg, 0x20803);
818 WREG32(data_reg, 0x80008010);
819 WREG32(index_reg, 0x30000);
820 WREG32(data_reg, 0x90008000);
821 WREG32(index_reg, 0x30001);
822 WREG32(data_reg, 0x80008000);
823 WREG32(index_reg, 0x30100);
824 WREG32(data_reg, 0x8FE0BF90);
825 WREG32(index_reg, 0x30101);
826 WREG32(data_reg, 0xBFF880A0);
827 WREG32(index_reg, 0x30200);
828 WREG32(data_reg, 0x8F60BF40);
829 WREG32(index_reg, 0x30201);
830 WREG32(data_reg, 0xBFE88180);
831 WREG32(index_reg, 0x30300);
832 WREG32(data_reg, 0x8EC0BF00);
833 WREG32(index_reg, 0x30301);
834 WREG32(data_reg, 0xBFC88280);
835 WREG32(index_reg, 0x30400);
836 WREG32(data_reg, 0x8DE0BEE0);
837 WREG32(index_reg, 0x30401);
838 WREG32(data_reg, 0xBFA083A0);
839 WREG32(index_reg, 0x30500);
840 WREG32(data_reg, 0x8CE0BED0);
841 WREG32(index_reg, 0x30501);
842 WREG32(data_reg, 0xBF7884E0);
843 WREG32(index_reg, 0x30600);
844 WREG32(data_reg, 0x8BA0BED8);
845 WREG32(index_reg, 0x30601);
846 WREG32(data_reg, 0xBF508640);
847 WREG32(index_reg, 0x30700);
848 WREG32(data_reg, 0x8A60BEE8);
849 WREG32(index_reg, 0x30701);
850 WREG32(data_reg, 0xBF2087A0);
851 WREG32(index_reg, 0x30800);
852 WREG32(data_reg, 0x8900BF00);
853 WREG32(index_reg, 0x30801);
854 WREG32(data_reg, 0xBF008900);
855 }
856
857 struct rv515_watermark {
858 u32 lb_request_fifo_depth;
859 fixed20_12 num_line_pair;
860 fixed20_12 estimated_width;
861 fixed20_12 worst_case_latency;
862 fixed20_12 consumption_rate;
863 fixed20_12 active_time;
864 fixed20_12 dbpp;
865 fixed20_12 priority_mark_max;
866 fixed20_12 priority_mark;
867 fixed20_12 sclk;
868 };
869
870 void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
871 struct radeon_crtc *crtc,
872 struct rv515_watermark *wm)
873 {
874 struct drm_display_mode *mode = &crtc->base.mode;
875 fixed20_12 a, b, c;
876 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
877 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
878
879 if (!crtc->base.enabled) {
880 /* FIXME: wouldn't it better to set priority mark to maximum */
881 wm->lb_request_fifo_depth = 4;
882 return;
883 }
884
885 if (crtc->vsc.full > rfixed_const(2))
886 wm->num_line_pair.full = rfixed_const(2);
887 else
888 wm->num_line_pair.full = rfixed_const(1);
889
890 b.full = rfixed_const(mode->crtc_hdisplay);
891 c.full = rfixed_const(256);
892 a.full = rfixed_mul(wm->num_line_pair, b);
893 request_fifo_depth.full = rfixed_div(a, c);
894 if (a.full < rfixed_const(4)) {
895 wm->lb_request_fifo_depth = 4;
896 } else {
897 wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth);
898 }
899
900 /* Determine consumption rate
901 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
902 * vtaps = number of vertical taps,
903 * vsc = vertical scaling ratio, defined as source/destination
904 * hsc = horizontal scaling ration, defined as source/destination
905 */
906 a.full = rfixed_const(mode->clock);
907 b.full = rfixed_const(1000);
908 a.full = rfixed_div(a, b);
909 pclk.full = rfixed_div(b, a);
910 if (crtc->rmx_type != RMX_OFF) {
911 b.full = rfixed_const(2);
912 if (crtc->vsc.full > b.full)
913 b.full = crtc->vsc.full;
914 b.full = rfixed_mul(b, crtc->hsc);
915 c.full = rfixed_const(2);
916 b.full = rfixed_div(b, c);
917 consumption_time.full = rfixed_div(pclk, b);
918 } else {
919 consumption_time.full = pclk.full;
920 }
921 a.full = rfixed_const(1);
922 wm->consumption_rate.full = rfixed_div(a, consumption_time);
923
924
925 /* Determine line time
926 * LineTime = total time for one line of displayhtotal
927 * LineTime = total number of horizontal pixels
928 * pclk = pixel clock period(ns)
929 */
930 a.full = rfixed_const(crtc->base.mode.crtc_htotal);
931 line_time.full = rfixed_mul(a, pclk);
932
933 /* Determine active time
934 * ActiveTime = time of active region of display within one line,
935 * hactive = total number of horizontal active pixels
936 * htotal = total number of horizontal pixels
937 */
938 a.full = rfixed_const(crtc->base.mode.crtc_htotal);
939 b.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
940 wm->active_time.full = rfixed_mul(line_time, b);
941 wm->active_time.full = rfixed_div(wm->active_time, a);
942
943 /* Determine chunk time
944 * ChunkTime = the time it takes the DCP to send one chunk of data
945 * to the LB which consists of pipeline delay and inter chunk gap
946 * sclk = system clock(Mhz)
947 */
948 a.full = rfixed_const(600 * 1000);
949 chunk_time.full = rfixed_div(a, rdev->pm.sclk);
950 read_delay_latency.full = rfixed_const(1000);
951
952 /* Determine the worst case latency
953 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
954 * WorstCaseLatency = worst case time from urgent to when the MC starts
955 * to return data
956 * READ_DELAY_IDLE_MAX = constant of 1us
957 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
958 * which consists of pipeline delay and inter chunk gap
959 */
960 if (rfixed_trunc(wm->num_line_pair) > 1) {
961 a.full = rfixed_const(3);
962 wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
963 wm->worst_case_latency.full += read_delay_latency.full;
964 } else {
965 wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full;
966 }
967
968 /* Determine the tolerable latency
969 * TolerableLatency = Any given request has only 1 line time
970 * for the data to be returned
971 * LBRequestFifoDepth = Number of chunk requests the LB can
972 * put into the request FIFO for a display
973 * LineTime = total time for one line of display
974 * ChunkTime = the time it takes the DCP to send one chunk
975 * of data to the LB which consists of
976 * pipeline delay and inter chunk gap
977 */
978 if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) {
979 tolerable_latency.full = line_time.full;
980 } else {
981 tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2);
982 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
983 tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time);
984 tolerable_latency.full = line_time.full - tolerable_latency.full;
985 }
986 /* We assume worst case 32bits (4 bytes) */
987 wm->dbpp.full = rfixed_const(2 * 16);
988
989 /* Determine the maximum priority mark
990 * width = viewport width in pixels
991 */
992 a.full = rfixed_const(16);
993 wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
994 wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a);
995
996 /* Determine estimated width */
997 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
998 estimated_width.full = rfixed_div(estimated_width, consumption_time);
999 if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
1000 wm->priority_mark.full = rfixed_const(10);
1001 } else {
1002 a.full = rfixed_const(16);
1003 wm->priority_mark.full = rfixed_div(estimated_width, a);
1004 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
1005 }
1006 }
1007
1008 void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
1009 {
1010 struct drm_display_mode *mode0 = NULL;
1011 struct drm_display_mode *mode1 = NULL;
1012 struct rv515_watermark wm0;
1013 struct rv515_watermark wm1;
1014 u32 tmp;
1015 fixed20_12 priority_mark02, priority_mark12, fill_rate;
1016 fixed20_12 a, b;
1017
1018 if (rdev->mode_info.crtcs[0]->base.enabled)
1019 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1020 if (rdev->mode_info.crtcs[1]->base.enabled)
1021 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1022 rs690_line_buffer_adjust(rdev, mode0, mode1);
1023
1024 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
1025 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
1026
1027 tmp = wm0.lb_request_fifo_depth;
1028 tmp |= wm1.lb_request_fifo_depth << 16;
1029 WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
1030
1031 if (mode0 && mode1) {
1032 if (rfixed_trunc(wm0.dbpp) > 64)
1033 a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair);
1034 else
1035 a.full = wm0.num_line_pair.full;
1036 if (rfixed_trunc(wm1.dbpp) > 64)
1037 b.full = rfixed_div(wm1.dbpp, wm1.num_line_pair);
1038 else
1039 b.full = wm1.num_line_pair.full;
1040 a.full += b.full;
1041 fill_rate.full = rfixed_div(wm0.sclk, a);
1042 if (wm0.consumption_rate.full > fill_rate.full) {
1043 b.full = wm0.consumption_rate.full - fill_rate.full;
1044 b.full = rfixed_mul(b, wm0.active_time);
1045 a.full = rfixed_const(16);
1046 b.full = rfixed_div(b, a);
1047 a.full = rfixed_mul(wm0.worst_case_latency,
1048 wm0.consumption_rate);
1049 priority_mark02.full = a.full + b.full;
1050 } else {
1051 a.full = rfixed_mul(wm0.worst_case_latency,
1052 wm0.consumption_rate);
1053 b.full = rfixed_const(16 * 1000);
1054 priority_mark02.full = rfixed_div(a, b);
1055 }
1056 if (wm1.consumption_rate.full > fill_rate.full) {
1057 b.full = wm1.consumption_rate.full - fill_rate.full;
1058 b.full = rfixed_mul(b, wm1.active_time);
1059 a.full = rfixed_const(16);
1060 b.full = rfixed_div(b, a);
1061 a.full = rfixed_mul(wm1.worst_case_latency,
1062 wm1.consumption_rate);
1063 priority_mark12.full = a.full + b.full;
1064 } else {
1065 a.full = rfixed_mul(wm1.worst_case_latency,
1066 wm1.consumption_rate);
1067 b.full = rfixed_const(16 * 1000);
1068 priority_mark12.full = rfixed_div(a, b);
1069 }
1070 if (wm0.priority_mark.full > priority_mark02.full)
1071 priority_mark02.full = wm0.priority_mark.full;
1072 if (rfixed_trunc(priority_mark02) < 0)
1073 priority_mark02.full = 0;
1074 if (wm0.priority_mark_max.full > priority_mark02.full)
1075 priority_mark02.full = wm0.priority_mark_max.full;
1076 if (wm1.priority_mark.full > priority_mark12.full)
1077 priority_mark12.full = wm1.priority_mark.full;
1078 if (rfixed_trunc(priority_mark12) < 0)
1079 priority_mark12.full = 0;
1080 if (wm1.priority_mark_max.full > priority_mark12.full)
1081 priority_mark12.full = wm1.priority_mark_max.full;
1082 WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
1083 WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
1084 WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
1085 WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
1086 } else if (mode0) {
1087 if (rfixed_trunc(wm0.dbpp) > 64)
1088 a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair);
1089 else
1090 a.full = wm0.num_line_pair.full;
1091 fill_rate.full = rfixed_div(wm0.sclk, a);
1092 if (wm0.consumption_rate.full > fill_rate.full) {
1093 b.full = wm0.consumption_rate.full - fill_rate.full;
1094 b.full = rfixed_mul(b, wm0.active_time);
1095 a.full = rfixed_const(16);
1096 b.full = rfixed_div(b, a);
1097 a.full = rfixed_mul(wm0.worst_case_latency,
1098 wm0.consumption_rate);
1099 priority_mark02.full = a.full + b.full;
1100 } else {
1101 a.full = rfixed_mul(wm0.worst_case_latency,
1102 wm0.consumption_rate);
1103 b.full = rfixed_const(16);
1104 priority_mark02.full = rfixed_div(a, b);
1105 }
1106 if (wm0.priority_mark.full > priority_mark02.full)
1107 priority_mark02.full = wm0.priority_mark.full;
1108 if (rfixed_trunc(priority_mark02) < 0)
1109 priority_mark02.full = 0;
1110 if (wm0.priority_mark_max.full > priority_mark02.full)
1111 priority_mark02.full = wm0.priority_mark_max.full;
1112 WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
1113 WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
1114 WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
1115 WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
1116 } else {
1117 if (rfixed_trunc(wm1.dbpp) > 64)
1118 a.full = rfixed_div(wm1.dbpp, wm1.num_line_pair);
1119 else
1120 a.full = wm1.num_line_pair.full;
1121 fill_rate.full = rfixed_div(wm1.sclk, a);
1122 if (wm1.consumption_rate.full > fill_rate.full) {
1123 b.full = wm1.consumption_rate.full - fill_rate.full;
1124 b.full = rfixed_mul(b, wm1.active_time);
1125 a.full = rfixed_const(16);
1126 b.full = rfixed_div(b, a);
1127 a.full = rfixed_mul(wm1.worst_case_latency,
1128 wm1.consumption_rate);
1129 priority_mark12.full = a.full + b.full;
1130 } else {
1131 a.full = rfixed_mul(wm1.worst_case_latency,
1132 wm1.consumption_rate);
1133 b.full = rfixed_const(16 * 1000);
1134 priority_mark12.full = rfixed_div(a, b);
1135 }
1136 if (wm1.priority_mark.full > priority_mark12.full)
1137 priority_mark12.full = wm1.priority_mark.full;
1138 if (rfixed_trunc(priority_mark12) < 0)
1139 priority_mark12.full = 0;
1140 if (wm1.priority_mark_max.full > priority_mark12.full)
1141 priority_mark12.full = wm1.priority_mark_max.full;
1142 WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
1143 WREG32(D1MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
1144 WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
1145 WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
1146 }
1147 }
1148
1149 void rv515_bandwidth_update(struct radeon_device *rdev)
1150 {
1151 uint32_t tmp;
1152 struct drm_display_mode *mode0 = NULL;
1153 struct drm_display_mode *mode1 = NULL;
1154
1155 if (rdev->mode_info.crtcs[0]->base.enabled)
1156 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1157 if (rdev->mode_info.crtcs[1]->base.enabled)
1158 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1159 /*
1160 * Set display0/1 priority up in the memory controller for
1161 * modes if the user specifies HIGH for displaypriority
1162 * option.
1163 */
1164 if (rdev->disp_priority == 2) {
1165 tmp = RREG32_MC(MC_MISC_LAT_TIMER);
1166 tmp &= ~MC_DISP1R_INIT_LAT_MASK;
1167 tmp &= ~MC_DISP0R_INIT_LAT_MASK;
1168 if (mode1)
1169 tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
1170 if (mode0)
1171 tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
1172 WREG32_MC(MC_MISC_LAT_TIMER, tmp);
1173 }
1174 rv515_bandwidth_avivo_update(rdev);
1175 }
Linux for Ginger Game Console