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Full support for Ginger Console
[linux-ginger.git] / drivers / i2c / busses / i2c-omap.c
blob75bf3ad180993a2315a9af4dfd3b30f5bd1067f2
1 /*
2 * TI OMAP I2C master mode driver
3 *
4 * Copyright (C) 2003 MontaVista Software, Inc.
5 * Copyright (C) 2005 Nokia Corporation
6 * Copyright (C) 2004 - 2007 Texas Instruments.
7 *
8 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@solidboot.com>
13 * Syed Khasim <x0khasim@ti.com>
14 * Nishant Menon <nm@ti.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31 #include <linux/module.h>
32 #include <linux/delay.h>
33 #include <linux/i2c.h>
34 #include <linux/err.h>
35 #include <linux/interrupt.h>
36 #include <linux/completion.h>
37 #include <linux/platform_device.h>
38 #include <linux/clk.h>
39 #include <linux/io.h>
40
41 /* I2C controller revisions */
42 #define OMAP_I2C_REV_2 0x20
43
44 /* I2C controller revisions present on specific hardware */
45 #define OMAP_I2C_REV_ON_2430 0x36
46 #define OMAP_I2C_REV_ON_3430 0x3C
47
48 /* timeout waiting for the controller to respond */
49 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
50
51 #define OMAP_I2C_REV_REG 0x00
52 #define OMAP_I2C_IE_REG 0x04
53 #define OMAP_I2C_STAT_REG 0x08
54 #define OMAP_I2C_IV_REG 0x0c
55 /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
56 #define OMAP_I2C_WE_REG 0x0c
57 #define OMAP_I2C_SYSS_REG 0x10
58 #define OMAP_I2C_BUF_REG 0x14
59 #define OMAP_I2C_CNT_REG 0x18
60 #define OMAP_I2C_DATA_REG 0x1c
61 #define OMAP_I2C_SYSC_REG 0x20
62 #define OMAP_I2C_CON_REG 0x24
63 #define OMAP_I2C_OA_REG 0x28
64 #define OMAP_I2C_SA_REG 0x2c
65 #define OMAP_I2C_PSC_REG 0x30
66 #define OMAP_I2C_SCLL_REG 0x34
67 #define OMAP_I2C_SCLH_REG 0x38
68 #define OMAP_I2C_SYSTEST_REG 0x3c
69 #define OMAP_I2C_BUFSTAT_REG 0x40
70
71 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
72 #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
73 #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
74 #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
75 #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
76 #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
77 #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
78 #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
79
80 /* I2C Status Register (OMAP_I2C_STAT): */
81 #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
82 #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
83 #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
84 #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
85 #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
86 #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
87 #define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
88 #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
89 #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
90 #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
91 #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
92 #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
93
94 /* I2C WE wakeup enable register */
95 #define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
96 #define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
97 #define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
98 #define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
99 #define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
100 #define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
101 #define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
102 #define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
103 #define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
104 #define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
105
106 #define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
107 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
108 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
109 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
110 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
111
112 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
113 #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
114 #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
115 #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
116 #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
117
118 /* I2C Configuration Register (OMAP_I2C_CON): */
119 #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
120 #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
121 #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
122 #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
123 #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
124 #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
125 #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
126 #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
127 #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
128 #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
129
130 /* I2C SCL time value when Master */
131 #define OMAP_I2C_SCLL_HSSCLL 8
132 #define OMAP_I2C_SCLH_HSSCLH 8
133
134 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
135 #ifdef DEBUG
136 #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
137 #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
138 #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
139 #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
140 #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
141 #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
142 #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
143 #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
144 #endif
145
146 /* OCP_SYSSTATUS bit definitions */
147 #define SYSS_RESETDONE_MASK (1 << 0)
148
149 /* OCP_SYSCONFIG bit definitions */
150 #define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
151 #define SYSC_SIDLEMODE_MASK (0x3 << 3)
152 #define SYSC_ENAWAKEUP_MASK (1 << 2)
153 #define SYSC_SOFTRESET_MASK (1 << 1)
154 #define SYSC_AUTOIDLE_MASK (1 << 0)
155
156 #define SYSC_IDLEMODE_SMART 0x2
157 #define SYSC_CLOCKACTIVITY_FCLK 0x2
158
159
160 struct omap_i2c_dev {
161 struct device *dev;
162 void __iomem *base; /* virtual */
163 int irq;
164 struct clk *iclk; /* Interface clock */
165 struct clk *fclk; /* Functional clock */
166 struct completion cmd_complete;
167 struct resource *ioarea;
168 u32 speed; /* Speed of bus in Khz */
169 u16 cmd_err;
170 u8 *buf;
171 size_t buf_len;
172 struct i2c_adapter adapter;
173 u8 fifo_size; /* use as flag and value
174 * fifo_size==0 implies no fifo
175 * if set, should be trsh+1
176 */
177 u8 rev;
178 unsigned b_hw:1; /* bad h/w fixes */
179 unsigned idle:1;
180 u16 iestate; /* Saved interrupt register */
181 u16 pscstate;
182 u16 scllstate;
183 u16 sclhstate;
184 u16 bufstate;
185 u16 syscstate;
186 u16 westate;
187 };
188
189 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
190 int reg, u16 val)
191 {
192 __raw_writew(val, i2c_dev->base + reg);
193 }
194
195 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
196 {
197 return __raw_readw(i2c_dev->base + reg);
198 }
199
200 static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
201 {
202 int ret;
203
204 dev->iclk = clk_get(dev->dev, "ick");
205 if (IS_ERR(dev->iclk)) {
206 ret = PTR_ERR(dev->iclk);
207 dev->iclk = NULL;
208 return ret;
209 }
210
211 dev->fclk = clk_get(dev->dev, "fck");
212 if (IS_ERR(dev->fclk)) {
213 ret = PTR_ERR(dev->fclk);
214 if (dev->iclk != NULL) {
215 clk_put(dev->iclk);
216 dev->iclk = NULL;
217 }
218 dev->fclk = NULL;
219 return ret;
220 }
221
222 return 0;
223 }
224
225 static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
226 {
227 clk_put(dev->fclk);
228 dev->fclk = NULL;
229 clk_put(dev->iclk);
230 dev->iclk = NULL;
231 }
232
233 static void omap_i2c_unidle(struct omap_i2c_dev *dev)
234 {
235 WARN_ON(!dev->idle);
236
237 clk_enable(dev->iclk);
238 clk_enable(dev->fclk);
239 if (cpu_is_omap34xx()) {
240 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
241 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
242 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
243 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
244 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, dev->bufstate);
245 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, dev->syscstate);
246 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
247 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
248 }
249 dev->idle = 0;
250 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
251 }
252
253 static void omap_i2c_idle(struct omap_i2c_dev *dev)
254 {
255 u16 iv;
256
257 WARN_ON(dev->idle);
258
259 dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
260 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
261 if (dev->rev < OMAP_I2C_REV_2) {
262 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
263 } else {
264 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
265
266 /* Flush posted write before the dev->idle store occurs */
267 omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
268 }
269 dev->idle = 1;
270 clk_disable(dev->fclk);
271 clk_disable(dev->iclk);
272 }
273
274 static int omap_i2c_init(struct omap_i2c_dev *dev)
275 {
276 u16 psc = 0, scll = 0, sclh = 0, buf = 0;
277 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
278 unsigned long fclk_rate = 12000000;
279 unsigned long timeout;
280 unsigned long internal_clk = 0;
281
282 if (dev->rev >= OMAP_I2C_REV_2) {
283 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
284 /* For some reason we need to set the EN bit before the
285 * reset done bit gets set. */
286 timeout = jiffies + OMAP_I2C_TIMEOUT;
287 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
288 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
289 SYSS_RESETDONE_MASK)) {
290 if (time_after(jiffies, timeout)) {
291 dev_warn(dev->dev, "timeout waiting "
292 "for controller reset\n");
293 return -ETIMEDOUT;
294 }
295 msleep(1);
296 }
297
298 /* SYSC register is cleared by the reset; rewrite it */
299 if (dev->rev == OMAP_I2C_REV_ON_2430) {
300
301 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
302 SYSC_AUTOIDLE_MASK);
303
304 } else if (dev->rev >= OMAP_I2C_REV_ON_3430) {
305 dev->syscstate = SYSC_AUTOIDLE_MASK;
306 dev->syscstate |= SYSC_ENAWAKEUP_MASK;
307 dev->syscstate |= (SYSC_IDLEMODE_SMART <<
308 __ffs(SYSC_SIDLEMODE_MASK));
309 dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK <<
310 __ffs(SYSC_CLOCKACTIVITY_MASK));
311
312 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
313 dev->syscstate);
314 /*
315 * Enabling all wakup sources to stop I2C freezing on
316 * WFI instruction.
317 * REVISIT: Some wkup sources might not be needed.
318 */
319 dev->westate = OMAP_I2C_WE_ALL;
320 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
321 }
322 }
323 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
324
325 if (cpu_class_is_omap1()) {
326 /*
327 * The I2C functional clock is the armxor_ck, so there's
328 * no need to get "armxor_ck" separately. Now, if OMAP2420
329 * always returns 12MHz for the functional clock, we can
330 * do this bit unconditionally.
331 */
332 fclk_rate = clk_get_rate(dev->fclk);
333
334 /* TRM for 5912 says the I2C clock must be prescaled to be
335 * between 7 - 12 MHz. The XOR input clock is typically
336 * 12, 13 or 19.2 MHz. So we should have code that produces:
337 *
338 * XOR MHz Divider Prescaler
339 * 12 1 0
340 * 13 2 1
341 * 19.2 2 1
342 */
343 if (fclk_rate > 12000000)
344 psc = fclk_rate / 12000000;
345 }
346
347 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
348
349 /*
350 * HSI2C controller internal clk rate should be 19.2 Mhz for
351 * HS and for all modes on 2430. On 34xx we can use lower rate
352 * to get longer filter period for better noise suppression.
353 * The filter is iclk (fclk for HS) period.
354 */
355 if (dev->speed > 400 || cpu_is_omap2430())
356 internal_clk = 19200;
357 else if (dev->speed > 100)
358 internal_clk = 9600;
359 else
360 internal_clk = 4000;
361 fclk_rate = clk_get_rate(dev->fclk) / 1000;
362
363 /* Compute prescaler divisor */
364 psc = fclk_rate / internal_clk;
365 psc = psc - 1;
366
367 /* If configured for High Speed */
368 if (dev->speed > 400) {
369 unsigned long scl;
370
371 /* For first phase of HS mode */
372 scl = internal_clk / 400;
373 fsscll = scl - (scl / 3) - 7;
374 fssclh = (scl / 3) - 5;
375
376 /* For second phase of HS mode */
377 scl = fclk_rate / dev->speed;
378 hsscll = scl - (scl / 3) - 7;
379 hssclh = (scl / 3) - 5;
380 } else if (dev->speed > 100) {
381 unsigned long scl;
382
383 /* Fast mode */
384 scl = internal_clk / dev->speed;
385 fsscll = scl - (scl / 3) - 7;
386 fssclh = (scl / 3) - 5;
387 } else {
388 /* Standard mode */
389 fsscll = internal_clk / (dev->speed * 2) - 7;
390 fssclh = internal_clk / (dev->speed * 2) - 5;
391 }
392 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
393 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
394 } else {
395 /* Program desired operating rate */
396 fclk_rate /= (psc + 1) * 1000;
397 if (psc > 2)
398 psc = 2;
399 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
400 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
401 }
402
403 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
404 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
405
406 /* SCL low and high time values */
407 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
408 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
409
410 if (dev->fifo_size) {
411 /* Note: setup required fifo size - 1. RTRSH and XTRSH */
412 buf = (dev->fifo_size - 1) << 8 | OMAP_I2C_BUF_RXFIF_CLR |
413 (dev->fifo_size - 1) | OMAP_I2C_BUF_TXFIF_CLR;
414 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
415 }
416
417 /* Take the I2C module out of reset: */
418 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
419
420 /* Enable interrupts */
421 dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
422 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
423 OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
424 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
425 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
426 if (cpu_is_omap34xx()) {
427 dev->pscstate = psc;
428 dev->scllstate = scll;
429 dev->sclhstate = sclh;
430 dev->bufstate = buf;
431 }
432 return 0;
433 }
434
435 /*
436 * Waiting on Bus Busy
437 */
438 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
439 {
440 unsigned long timeout;
441
442 timeout = jiffies + OMAP_I2C_TIMEOUT;
443 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
444 if (time_after(jiffies, timeout)) {
445 dev_warn(dev->dev, "timeout waiting for bus ready\n");
446 return -ETIMEDOUT;
447 }
448 msleep(1);
449 }
450
451 return 0;
452 }
453
454 /*
455 * Low level master read/write transaction.
456 */
457 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
458 struct i2c_msg *msg, int stop)
459 {
460 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
461 int r;
462 u16 w;
463
464 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
465 msg->addr, msg->len, msg->flags, stop);
466
467 if (msg->len == 0)
468 return -EINVAL;
469
470 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
471
472 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
473 dev->buf = msg->buf;
474 dev->buf_len = msg->len;
475
476 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
477
478 /* Clear the FIFO Buffers */
479 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
480 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
481 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
482
483 init_completion(&dev->cmd_complete);
484 dev->cmd_err = 0;
485
486 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
487
488 /* High speed configuration */
489 if (dev->speed > 400)
490 w |= OMAP_I2C_CON_OPMODE_HS;
491
492 if (msg->flags & I2C_M_TEN)
493 w |= OMAP_I2C_CON_XA;
494 if (!(msg->flags & I2C_M_RD))
495 w |= OMAP_I2C_CON_TRX;
496
497 if (!dev->b_hw && stop)
498 w |= OMAP_I2C_CON_STP;
499
500 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
501
502 /*
503 * Don't write stt and stp together on some hardware.
504 */
505 if (dev->b_hw && stop) {
506 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
507 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
508 while (con & OMAP_I2C_CON_STT) {
509 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
510
511 /* Let the user know if i2c is in a bad state */
512 if (time_after(jiffies, delay)) {
513 dev_err(dev->dev, "controller timed out "
514 "waiting for start condition to finish\n");
515 return -ETIMEDOUT;
516 }
517 cpu_relax();
518 }
519
520 w |= OMAP_I2C_CON_STP;
521 w &= ~OMAP_I2C_CON_STT;
522 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
523 }
524
525 /*
526 * REVISIT: We should abort the transfer on signals, but the bus goes
527 * into arbitration and we're currently unable to recover from it.
528 */
529 r = wait_for_completion_timeout(&dev->cmd_complete,
530 OMAP_I2C_TIMEOUT);
531 dev->buf_len = 0;
532 if (r < 0)
533 return r;
534 if (r == 0) {
535 dev_err(dev->dev, "controller timed out\n");
536 omap_i2c_init(dev);
537 return -ETIMEDOUT;
538 }
539
540 if (likely(!dev->cmd_err))
541 return 0;
542
543 /* We have an error */
544 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
545 OMAP_I2C_STAT_XUDF)) {
546 omap_i2c_init(dev);
547 return -EIO;
548 }
549
550 if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
551 if (msg->flags & I2C_M_IGNORE_NAK)
552 return 0;
553 if (stop) {
554 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
555 w |= OMAP_I2C_CON_STP;
556 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
557 }
558 return -EREMOTEIO;
559 }
560 return -EIO;
561 }
562
563
564 /*
565 * Prepare controller for a transaction and call omap_i2c_xfer_msg
566 * to do the work during IRQ processing.
567 */
568 static int
569 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
570 {
571 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
572 int i;
573 int r;
574
575 omap_i2c_unidle(dev);
576
577 r = omap_i2c_wait_for_bb(dev);
578 if (r < 0)
579 goto out;
580
581 for (i = 0; i < num; i++) {
582 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
583 if (r != 0)
584 break;
585 }
586
587 if (r == 0)
588 r = num;
589 out:
590 omap_i2c_idle(dev);
591 return r;
592 }
593
594 static u32
595 omap_i2c_func(struct i2c_adapter *adap)
596 {
597 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
598 }
599
600 static inline void
601 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
602 {
603 dev->cmd_err |= err;
604 complete(&dev->cmd_complete);
605 }
606
607 static inline void
608 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
609 {
610 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
611 }
612
613 /* rev1 devices are apparently only on some 15xx */
614 #ifdef CONFIG_ARCH_OMAP15XX
615
616 static irqreturn_t
617 omap_i2c_rev1_isr(int this_irq, void *dev_id)
618 {
619 struct omap_i2c_dev *dev = dev_id;
620 u16 iv, w;
621
622 if (dev->idle)
623 return IRQ_NONE;
624
625 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
626 switch (iv) {
627 case 0x00: /* None */
628 break;
629 case 0x01: /* Arbitration lost */
630 dev_err(dev->dev, "Arbitration lost\n");
631 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
632 break;
633 case 0x02: /* No acknowledgement */
634 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
635 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
636 break;
637 case 0x03: /* Register access ready */
638 omap_i2c_complete_cmd(dev, 0);
639 break;
640 case 0x04: /* Receive data ready */
641 if (dev->buf_len) {
642 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
643 *dev->buf++ = w;
644 dev->buf_len--;
645 if (dev->buf_len) {
646 *dev->buf++ = w >> 8;
647 dev->buf_len--;
648 }
649 } else
650 dev_err(dev->dev, "RRDY IRQ while no data requested\n");
651 break;
652 case 0x05: /* Transmit data ready */
653 if (dev->buf_len) {
654 w = *dev->buf++;
655 dev->buf_len--;
656 if (dev->buf_len) {
657 w |= *dev->buf++ << 8;
658 dev->buf_len--;
659 }
660 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
661 } else
662 dev_err(dev->dev, "XRDY IRQ while no data to send\n");
663 break;
664 default:
665 return IRQ_NONE;
666 }
667
668 return IRQ_HANDLED;
669 }
670 #else
671 #define omap_i2c_rev1_isr NULL
672 #endif
673
674 static irqreturn_t
675 omap_i2c_isr(int this_irq, void *dev_id)
676 {
677 struct omap_i2c_dev *dev = dev_id;
678 u16 bits;
679 u16 stat, w;
680 int err, count = 0;
681
682 if (dev->idle)
683 return IRQ_NONE;
684
685 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
686 while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
687 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
688 if (count++ == 100) {
689 dev_warn(dev->dev, "Too much work in one IRQ\n");
690 break;
691 }
692
693 err = 0;
694 complete:
695 /*
696 * Ack the stat in one go, but [R/X]DR and [R/X]RDY should be
697 * acked after the data operation is complete.
698 * Ref: TRM SWPU114Q Figure 18-31
699 */
700 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat &
701 ~(OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
702 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
703
704 if (stat & OMAP_I2C_STAT_NACK) {
705 err |= OMAP_I2C_STAT_NACK;
706 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
707 OMAP_I2C_CON_STP);
708 }
709 if (stat & OMAP_I2C_STAT_AL) {
710 dev_err(dev->dev, "Arbitration lost\n");
711 err |= OMAP_I2C_STAT_AL;
712 }
713 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
714 OMAP_I2C_STAT_AL)) {
715 omap_i2c_ack_stat(dev, stat &
716 (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
717 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
718 omap_i2c_complete_cmd(dev, err);
719 return IRQ_HANDLED;
720 }
721 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
722 u8 num_bytes = 1;
723 if (dev->fifo_size) {
724 if (stat & OMAP_I2C_STAT_RRDY)
725 num_bytes = dev->fifo_size;
726 else /* read RXSTAT on RDR interrupt */
727 num_bytes = (omap_i2c_read_reg(dev,
728 OMAP_I2C_BUFSTAT_REG)
729 >> 8) & 0x3F;
730 }
731 while (num_bytes) {
732 num_bytes--;
733 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
734 if (dev->buf_len) {
735 *dev->buf++ = w;
736 dev->buf_len--;
737 /* Data reg from 2430 is 8 bit wide */
738 if (!cpu_is_omap2430() &&
739 !cpu_is_omap34xx()) {
740 if (dev->buf_len) {
741 *dev->buf++ = w >> 8;
742 dev->buf_len--;
743 }
744 }
745 } else {
746 if (stat & OMAP_I2C_STAT_RRDY)
747 dev_err(dev->dev,
748 "RRDY IRQ while no data"
749 " requested\n");
750 if (stat & OMAP_I2C_STAT_RDR)
751 dev_err(dev->dev,
752 "RDR IRQ while no data"
753 " requested\n");
754 break;
755 }
756 }
757 omap_i2c_ack_stat(dev,
758 stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
759 continue;
760 }
761 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
762 u8 num_bytes = 1;
763 if (dev->fifo_size) {
764 if (stat & OMAP_I2C_STAT_XRDY)
765 num_bytes = dev->fifo_size;
766 else /* read TXSTAT on XDR interrupt */
767 num_bytes = omap_i2c_read_reg(dev,
768 OMAP_I2C_BUFSTAT_REG)
769 & 0x3F;
770 }
771 while (num_bytes) {
772 num_bytes--;
773 w = 0;
774 if (dev->buf_len) {
775 w = *dev->buf++;
776 dev->buf_len--;
777 /* Data reg from 2430 is 8 bit wide */
778 if (!cpu_is_omap2430() &&
779 !cpu_is_omap34xx()) {
780 if (dev->buf_len) {
781 w |= *dev->buf++ << 8;
782 dev->buf_len--;
783 }
784 }
785 } else {
786 if (stat & OMAP_I2C_STAT_XRDY)
787 dev_err(dev->dev,
788 "XRDY IRQ while no "
789 "data to send\n");
790 if (stat & OMAP_I2C_STAT_XDR)
791 dev_err(dev->dev,
792 "XDR IRQ while no "
793 "data to send\n");
794 break;
795 }
796
797 /*
798 * OMAP3430 Errata 1.153: When an XRDY/XDR
799 * is hit, wait for XUDF before writing data
800 * to DATA_REG. Otherwise some data bytes can
801 * be lost while transferring them from the
802 * memory to the I2C interface.
803 */
804
805 if (dev->rev <= OMAP_I2C_REV_ON_3430) {
806 while (!(stat & OMAP_I2C_STAT_XUDF)) {
807 if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
808 omap_i2c_ack_stat(dev, stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
809 err |= OMAP_I2C_STAT_XUDF;
810 goto complete;
811 }
812 cpu_relax();
813 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
814 }
815 }
816
817 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
818 }
819 omap_i2c_ack_stat(dev,
820 stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
821 continue;
822 }
823 if (stat & OMAP_I2C_STAT_ROVR) {
824 dev_err(dev->dev, "Receive overrun\n");
825 dev->cmd_err |= OMAP_I2C_STAT_ROVR;
826 }
827 if (stat & OMAP_I2C_STAT_XUDF) {
828 dev_err(dev->dev, "Transmit underflow\n");
829 dev->cmd_err |= OMAP_I2C_STAT_XUDF;
830 }
831 }
832
833 return count ? IRQ_HANDLED : IRQ_NONE;
834 }
835
836 static const struct i2c_algorithm omap_i2c_algo = {
837 .master_xfer = omap_i2c_xfer,
838 .functionality = omap_i2c_func,
839 };
840
841 static int __init
842 omap_i2c_probe(struct platform_device *pdev)
843 {
844 struct omap_i2c_dev *dev;
845 struct i2c_adapter *adap;
846 struct resource *mem, *irq, *ioarea;
847 irq_handler_t isr;
848 int r;
849 u32 speed = 0;
850
851 /* NOTE: driver uses the static register mapping */
852 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
853 if (!mem) {
854 dev_err(&pdev->dev, "no mem resource?\n");
855 return -ENODEV;
856 }
857 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
858 if (!irq) {
859 dev_err(&pdev->dev, "no irq resource?\n");
860 return -ENODEV;
861 }
862
863 ioarea = request_mem_region(mem->start, resource_size(mem),
864 pdev->name);
865 if (!ioarea) {
866 dev_err(&pdev->dev, "I2C region already claimed\n");
867 return -EBUSY;
868 }
869
870 dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
871 if (!dev) {
872 r = -ENOMEM;
873 goto err_release_region;
874 }
875
876 if (pdev->dev.platform_data != NULL)
877 speed = *(u32 *)pdev->dev.platform_data;
878 else
879 speed = 100; /* Defualt speed */
880
881 dev->speed = speed;
882 dev->idle = 1;
883 dev->dev = &pdev->dev;
884 dev->irq = irq->start;
885 dev->base = ioremap(mem->start, resource_size(mem));
886 if (!dev->base) {
887 r = -ENOMEM;
888 goto err_free_mem;
889 }
890
891 platform_set_drvdata(pdev, dev);
892
893 if ((r = omap_i2c_get_clocks(dev)) != 0)
894 goto err_iounmap;
895
896 omap_i2c_unidle(dev);
897
898 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
899
900 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
901 u16 s;
902
903 /* Set up the fifo size - Get total size */
904 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
905 dev->fifo_size = 0x8 << s;
906
907 /*
908 * Set up notification threshold as half the total available
909 * size. This is to ensure that we can handle the status on int
910 * call back latencies.
911 */
912 dev->fifo_size = (dev->fifo_size / 2);
913 dev->b_hw = 1; /* Enable hardware fixes */
914 }
915
916 /* reset ASAP, clearing any IRQs */
917 omap_i2c_init(dev);
918
919 isr = (dev->rev < OMAP_I2C_REV_2) ? omap_i2c_rev1_isr : omap_i2c_isr;
920 r = request_irq(dev->irq, isr, 0, pdev->name, dev);
921
922 if (r) {
923 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
924 goto err_unuse_clocks;
925 }
926
927 dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
928 pdev->id, dev->rev >> 4, dev->rev & 0xf, dev->speed);
929
930 omap_i2c_idle(dev);
931
932 adap = &dev->adapter;
933 i2c_set_adapdata(adap, dev);
934 adap->owner = THIS_MODULE;
935 adap->class = I2C_CLASS_HWMON;
936 strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
937 adap->algo = &omap_i2c_algo;
938 adap->dev.parent = &pdev->dev;
939
940 /* i2c device drivers may be active on return from add_adapter() */
941 adap->nr = pdev->id;
942 r = i2c_add_numbered_adapter(adap);
943 if (r) {
944 dev_err(dev->dev, "failure adding adapter\n");
945 goto err_free_irq;
946 }
947
948 return 0;
949
950 err_free_irq:
951 free_irq(dev->irq, dev);
952 err_unuse_clocks:
953 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
954 omap_i2c_idle(dev);
955 omap_i2c_put_clocks(dev);
956 err_iounmap:
957 iounmap(dev->base);
958 err_free_mem:
959 platform_set_drvdata(pdev, NULL);
960 kfree(dev);
961 err_release_region:
962 release_mem_region(mem->start, resource_size(mem));
963
964 return r;
965 }
966
967 static int
968 omap_i2c_remove(struct platform_device *pdev)
969 {
970 struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
971 struct resource *mem;
972
973 platform_set_drvdata(pdev, NULL);
974
975 free_irq(dev->irq, dev);
976 i2c_del_adapter(&dev->adapter);
977 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
978 omap_i2c_put_clocks(dev);
979 iounmap(dev->base);
980 kfree(dev);
981 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
982 release_mem_region(mem->start, resource_size(mem));
983 return 0;
984 }
985
986 static struct platform_driver omap_i2c_driver = {
987 .probe = omap_i2c_probe,
988 .remove = omap_i2c_remove,
989 .driver = {
990 .name = "i2c_omap",
991 .owner = THIS_MODULE,
992 },
993 };
994
995 /* I2C may be needed to bring up other drivers */
996 static int __init
997 omap_i2c_init_driver(void)
998 {
999 return platform_driver_register(&omap_i2c_driver);
1000 }
1001 subsys_initcall(omap_i2c_init_driver);
1002
1003 static void __exit omap_i2c_exit_driver(void)
1004 {
1005 platform_driver_unregister(&omap_i2c_driver);
1006 }
1007 module_exit(omap_i2c_exit_driver);
1008
1009 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1010 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1011 MODULE_LICENSE("GPL");
1012 MODULE_ALIAS("platform:i2c_omap");
Linux for Ginger Game Console