drivers/media/video/isp/isph3a.h

   1 /*
   2  * isph3a.h
   3  *
   4  * Include file for H3A module in TI's OMAP3 Camera ISP
   5  *
   6  * Copyright (C) 2009 Texas Instruments, Inc.
   7  *
   8  * Contributors:
   9  *      Sergio Aguirre <saaguirre@ti.com>
  10  *      Troy Laramy
  11  *
  12  * This package is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  *
  16  * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
  17  * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
  18  * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  19  */
  20
  21 #ifndef OMAP_ISP_H3A_H
  22 #define OMAP_ISP_H3A_H
  23
  24 #include <plat/isp_user.h>
  25
  26 #define AEWB_PACKET_SIZE        16
  27 #define H3A_MAX_BUFF            5
  28 #define AEWB_SATURATION_LIMIT   0x3FF
  29
  30 /* Flags for changed registers */
  31 #define PCR_CHNG                (1 << 0)
  32 #define AEWWIN1_CHNG            (1 << 1)
  33 #define AEWINSTART_CHNG         (1 << 2)
  34 #define AEWINBLK_CHNG           (1 << 3)
  35 #define AEWSUBWIN_CHNG          (1 << 4)
  36 #define PRV_WBDGAIN_CHNG        (1 << 5)
  37 #define PRV_WBGAIN_CHNG         (1 << 6)
  38
  39 /* ISPH3A REGISTERS bits */
  40 #define ISPH3A_PCR_AF_EN        (1 << 0)
  41 #define ISPH3A_PCR_AF_ALAW_EN   (1 << 1)
  42 #define ISPH3A_PCR_AF_MED_EN    (1 << 2)
  43 #define ISPH3A_PCR_AF_BUSY      (1 << 15)
  44 #define ISPH3A_PCR_AEW_EN       (1 << 16)
  45 #define ISPH3A_PCR_AEW_ALAW_EN  (1 << 17)
  46 #define ISPH3A_PCR_AEW_BUSY     (1 << 18)
  47 #define ISPH3A_PCR_AEW_MASK     (ISPH3A_PCR_AEW_EN | ISPH3A_PCR_AEW_ALAW_EN | \
  48                                  ISPH3A_PCR_AEW_AVE2LMT_MASK)
  49
  50 #define WRITE_SAT_LIM(reg, sat_limit)                   \
  51         (reg = (reg & (~(ISPH3A_PCR_AEW_AVE2LMT_MASK))) \
  52          | (sat_limit << ISPH3A_PCR_AEW_AVE2LMT_SHIFT))
  53
  54 #define WRITE_ALAW(reg, alaw_en)                        \
  55         (reg = (reg & (~(ISPH3A_PCR_AEW_ALAW_EN)))      \
  56          | ((alaw_en & ISPH3A_PCR_AF_ALAW_EN)           \
  57             << ISPH3A_PCR_AEW_ALAW_EN_SHIFT))
  58
  59 #define WRITE_WIN_H(reg, height)                                \
  60         (reg = (reg & (~(ISPH3A_AEWWIN1_WINH_MASK)))            \
  61          | (((height >> 1) - 1) << ISPH3A_AEWWIN1_WINH_SHIFT))
  62
  63 #define WRITE_WIN_W(reg, width)                                 \
  64         (reg = (reg & (~(ISPH3A_AEWWIN1_WINW_MASK)))            \
  65          | (((width >> 1) - 1) << ISPH3A_AEWWIN1_WINW_SHIFT))
  66
  67 #define WRITE_VER_C(reg, ver_count)                             \
  68         (reg = (reg & ~(ISPH3A_AEWWIN1_WINVC_MASK))             \
  69          | ((ver_count - 1) << ISPH3A_AEWWIN1_WINVC_SHIFT))
  70
  71 #define WRITE_HOR_C(reg, hor_count)                             \
  72         (reg = (reg & ~(ISPH3A_AEWWIN1_WINHC_MASK))             \
  73          | ((hor_count - 1) << ISPH3A_AEWWIN1_WINHC_SHIFT))
  74
  75 #define WRITE_VER_WIN_ST(reg, ver_win_st)                       \
  76         (reg = (reg & ~(ISPH3A_AEWINSTART_WINSV_MASK))          \
  77          | (ver_win_st << ISPH3A_AEWINSTART_WINSV_SHIFT))
  78
  79 #define WRITE_HOR_WIN_ST(reg, hor_win_st)                       \
  80         (reg = (reg & ~(ISPH3A_AEWINSTART_WINSH_MASK))          \
  81          | (hor_win_st << ISPH3A_AEWINSTART_WINSH_SHIFT))
  82
  83 #define WRITE_BLK_VER_WIN_ST(reg, blk_win_st)           \
  84         (reg = (reg & ~(ISPH3A_AEWINBLK_WINSV_MASK))    \
  85          | (blk_win_st << ISPH3A_AEWINBLK_WINSV_SHIFT))
  86
  87 #define WRITE_BLK_WIN_H(reg, height)                            \
  88         (reg = (reg & ~(ISPH3A_AEWINBLK_WINH_MASK))             \
  89          | (((height >> 1) - 1) << ISPH3A_AEWINBLK_WINH_SHIFT))
  90
  91 #define WRITE_SUB_VER_INC(reg, sub_ver_inc)                             \
  92         (reg = (reg & ~(ISPH3A_AEWSUBWIN_AEWINCV_MASK))                 \
  93          | (((sub_ver_inc >> 1) - 1) << ISPH3A_AEWSUBWIN_AEWINCV_SHIFT))
  94
  95 #define WRITE_SUB_HOR_INC(reg, sub_hor_inc)                             \
  96         (reg = (reg & ~(ISPH3A_AEWSUBWIN_AEWINCH_MASK))                 \
  97          | (((sub_hor_inc >> 1) - 1) << ISPH3A_AEWSUBWIN_AEWINCH_SHIFT))
  98
  99 /**
 100  * struct isph3a_aewb_regs - Current value of AE, AWB configuration registers.
 101  * pcr: Peripheral control register.
 102  * win1: Control register.
 103  * start: Start position register.
 104  * blk: Black line register.
 105  * subwin: Configuration register.
 106  */
 107 struct isph3a_aewb_regs {
 108         u32 pcr;
 109         u32 win1;
 110         u32 start;
 111         u32 blk;
 112         u32 subwin;
 113 };
 114
 115 struct isp_h3a_device {
 116         spinlock_t *lock;               /* Lock for this struct */
 117
 118         u8 update;
 119         int pm_state;
 120         int wb_update;
 121
 122         struct isph3a_aewb_regs regs;
 123         struct ispprev_wbal h3awb_update;
 124         struct isph3a_aewb_config aewb_config_local;
 125         u16 win_count;
 126
 127         struct device *dev;
 128
 129         struct ispstat stat;
 130 };
 131
 132 int isph3a_aewb_configure(struct isp_h3a_device *isp_h3a,
 133                           struct isph3a_aewb_config *aewbcfg);
 134
 135 int isph3a_aewb_request_statistics(struct isp_h3a_device *isp_h3a,
 136                                    struct isph3a_aewb_data *aewbdata);
 137
 138 void isph3a_save_context(struct device *dev);
 139
 140 void isph3a_restore_context(struct device *dev);
 141
 142 void isph3a_aewb_enable(struct isp_h3a_device *isp_h3a, u8 enable);
 143
 144 int isph3a_aewb_busy(struct isp_h3a_device *isp_h3a);
 145
 146 void isph3a_aewb_suspend(struct isp_h3a_device *isp_h3a);
 147
 148 void isph3a_aewb_resume(struct isp_h3a_device *isp_h3a);
 149
 150 void isph3a_update_wb(struct isp_h3a_device *isp_h3a);
 151
 152 void isph3a_aewb_isr(struct isp_h3a_device *isp_h3a);
 153
 154 #endif          /* OMAP_ISP_H3A_H */