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Full support for Ginger Console
[linux-ginger.git] / drivers / media / video / ti-media / dm644x_ccdc.c
blobbc7a9ce5638620a40d186c9de83a9136fc2eedd5
1 /*
2 * Copyright (C) 2006-2009 Texas Instruments Inc
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 *
18 * CCDC hardware module for DM6446
19 * ------------------------------
20 *
21 * This module is for configuring CCD controller of DM6446 VPFE to capture
22 * Raw yuv or Bayer RGB data from a decoder. CCDC has several modules
23 * such as Defect Pixel Correction, Color Space Conversion etc to
24 * pre-process the Raw Bayer RGB data, before writing it to SDRAM. This
25 * module also allows application to configure individual
26 * module parameters through VPFE_CMD_S_CCDC_RAW_PARAMS IOCTL.
27 * To do so, application includes dm644x_ccdc.h and vpfe_capture.h header
28 * files. The setparams() API is called by vpfe_capture driver
29 * to configure module parameters. This file is named DM644x so that other
30 * variants such DM6443 may be supported using the same module.
31 *
32 * TODO: Test Raw bayer parameter settings and bayer capture
33 * Split module parameter structure to module specific ioctl structs
34 * investigate if enum used for user space type definition
35 * to be replaced by #defines or integer
36 */
37 #include <linux/platform_device.h>
38 #include <linux/uaccess.h>
39 #include <linux/videodev2.h>
40 #include <media/ti-media/dm644x_ccdc.h>
41 #include <media/ti-media/vpss.h>
42 #include "dm644x_ccdc_regs.h"
43 #include "ccdc_hw_device.h"
44
45 MODULE_LICENSE("GPL");
46 MODULE_DESCRIPTION("CCDC Driver for DM6446");
47 MODULE_AUTHOR("Texas Instruments");
48
49 static struct device *dev;
50
51 /* Object for CCDC raw mode */
52 static struct ccdc_params_raw ccdc_hw_params_raw = {
53 .pix_fmt = CCDC_PIXFMT_RAW,
54 .frm_fmt = CCDC_FRMFMT_PROGRESSIVE,
55 .win = CCDC_WIN_VGA,
56 .fid_pol = VPFE_PINPOL_POSITIVE,
57 .vd_pol = VPFE_PINPOL_POSITIVE,
58 .hd_pol = VPFE_PINPOL_POSITIVE,
59 .config_params = {
60 .data_sz = CCDC_DATA_10BITS,
61 },
62 };
63
64 /* Object for CCDC ycbcr mode */
65 static struct ccdc_params_ycbcr ccdc_hw_params_ycbcr = {
66 .pix_fmt = CCDC_PIXFMT_YCBCR_8BIT,
67 .frm_fmt = CCDC_FRMFMT_INTERLACED,
68 .win = CCDC_WIN_PAL,
69 .fid_pol = VPFE_PINPOL_POSITIVE,
70 .vd_pol = VPFE_PINPOL_POSITIVE,
71 .hd_pol = VPFE_PINPOL_POSITIVE,
72 .bt656_enable = 1,
73 .pix_order = CCDC_PIXORDER_CBYCRY,
74 .buf_type = CCDC_BUFTYPE_FLD_INTERLEAVED
75 };
76
77 #define CCDC_MAX_RAW_YUV_FORMATS 2
78
79 /* Raw Bayer formats */
80 static u32 ccdc_raw_bayer_pix_formats[] =
81 {V4L2_PIX_FMT_SBGGR8, V4L2_PIX_FMT_SBGGR16};
82
83 /* Raw YUV formats */
84 static u32 ccdc_raw_yuv_pix_formats[] =
85 {V4L2_PIX_FMT_UYVY, V4L2_PIX_FMT_YUYV};
86
87 static void *__iomem ccdc_base_addr;
88 static int ccdc_addr_size;
89 static enum vpfe_hw_if_type ccdc_if_type;
90
91 #define CCDC_SZ_REGS SZ_1K
92
93 static u32 ccdc_ctx[CCDC_SZ_REGS / sizeof(u32)];
94
95 /* register access routines */
96 static inline u32 regr(u32 offset)
97 {
98 return __raw_readl(ccdc_base_addr + offset);
99 }
100
101 static inline void regw(u32 val, u32 offset)
102 {
103 __raw_writel(val, ccdc_base_addr + offset);
104 }
105
106 static void ccdc_set_ccdc_base(void *addr, int size)
107 {
108 ccdc_base_addr = addr;
109 ccdc_addr_size = size;
110 }
111
112 static void ccdc_enable(int flag)
113 {
114 regw(flag, CCDC_PCR);
115 }
116
117 static void ccdc_enable_vport(int flag)
118 {
119 if (flag)
120 /* enable video port */
121 regw(CCDC_ENABLE_VIDEO_PORT, CCDC_FMTCFG);
122 else
123 regw(CCDC_DISABLE_VIDEO_PORT, CCDC_FMTCFG);
124 }
125
126 /*
127 * ccdc_setwin()
128 * This function will configure the window size
129 * to be capture in CCDC reg
130 */
131 void ccdc_setwin(struct v4l2_rect *image_win,
132 enum ccdc_frmfmt frm_fmt,
133 int ppc)
134 {
135 int horz_start, horz_nr_pixels;
136 int vert_start, vert_nr_lines;
137 int val = 0, mid_img = 0;
138
139 dev_dbg(dev, "\nStarting ccdc_setwin...");
140 /*
141 * ppc - per pixel count. indicates how many pixels per cell
142 * output to SDRAM. example, for ycbcr, it is one y and one c, so 2.
143 * raw capture this is 1
144 */
145 horz_start = image_win->left << (ppc - 1);
146 horz_nr_pixels = (image_win->width << (ppc - 1)) - 1;
147 regw((horz_start << CCDC_HORZ_INFO_SPH_SHIFT) | horz_nr_pixels,
148 CCDC_HORZ_INFO);
149
150 vert_start = image_win->top;
151
152 if (frm_fmt == CCDC_FRMFMT_INTERLACED) {
153 vert_nr_lines = (image_win->height >> 1) - 1;
154 vert_start >>= 1;
155 /* Since first line doesn't have any data */
156 vert_start += 1;
157 /* configure VDINT0 */
158 val = (vert_start << CCDC_VDINT_VDINT0_SHIFT);
159 regw(val, CCDC_VDINT);
160
161 } else {
162 /* Since first line doesn't have any data */
163 vert_start += 1;
164 vert_nr_lines = image_win->height - 1;
165 /*
166 * configure VDINT0 and VDINT1. VDINT1 will be at half
167 * of image height
168 */
169 mid_img = vert_start + (image_win->height / 2);
170 val = (vert_start << CCDC_VDINT_VDINT0_SHIFT) |
171 (mid_img & CCDC_VDINT_VDINT1_MASK);
172 regw(val, CCDC_VDINT);
173
174 }
175 regw((vert_start << CCDC_VERT_START_SLV0_SHIFT) | vert_start,
176 CCDC_VERT_START);
177 regw(vert_nr_lines, CCDC_VERT_LINES);
178 dev_dbg(dev, "\nEnd of ccdc_setwin...");
179 }
180
181 static void ccdc_readregs(void)
182 {
183 unsigned int val = 0;
184
185 val = regr(CCDC_ALAW);
186 dev_notice(dev, "\nReading 0x%x to ALAW...\n", val);
187 val = regr(CCDC_CLAMP);
188 dev_notice(dev, "\nReading 0x%x to CLAMP...\n", val);
189 val = regr(CCDC_DCSUB);
190 dev_notice(dev, "\nReading 0x%x to DCSUB...\n", val);
191 val = regr(CCDC_BLKCMP);
192 dev_notice(dev, "\nReading 0x%x to BLKCMP...\n", val);
193 val = regr(CCDC_FPC_ADDR);
194 dev_notice(dev, "\nReading 0x%x to FPC_ADDR...\n", val);
195 val = regr(CCDC_FPC);
196 dev_notice(dev, "\nReading 0x%x to FPC...\n", val);
197 val = regr(CCDC_FMTCFG);
198 dev_notice(dev, "\nReading 0x%x to FMTCFG...\n", val);
199 val = regr(CCDC_COLPTN);
200 dev_notice(dev, "\nReading 0x%x to COLPTN...\n", val);
201 val = regr(CCDC_FMT_HORZ);
202 dev_notice(dev, "\nReading 0x%x to FMT_HORZ...\n", val);
203 val = regr(CCDC_FMT_VERT);
204 dev_notice(dev, "\nReading 0x%x to FMT_VERT...\n", val);
205 val = regr(CCDC_HSIZE_OFF);
206 dev_notice(dev, "\nReading 0x%x to HSIZE_OFF...\n", val);
207 val = regr(CCDC_SDOFST);
208 dev_notice(dev, "\nReading 0x%x to SDOFST...\n", val);
209 val = regr(CCDC_VP_OUT);
210 dev_notice(dev, "\nReading 0x%x to VP_OUT...\n", val);
211 val = regr(CCDC_SYN_MODE);
212 dev_notice(dev, "\nReading 0x%x to SYN_MODE...\n", val);
213 val = regr(CCDC_HORZ_INFO);
214 dev_notice(dev, "\nReading 0x%x to HORZ_INFO...\n", val);
215 val = regr(CCDC_VERT_START);
216 dev_notice(dev, "\nReading 0x%x to VERT_START...\n", val);
217 val = regr(CCDC_VERT_LINES);
218 dev_notice(dev, "\nReading 0x%x to VERT_LINES...\n", val);
219 }
220
221 static int validate_ccdc_param(struct ccdc_config_params_raw *ccdcparam)
222 {
223 if (ccdcparam->alaw.enable) {
224 if ((ccdcparam->alaw.gama_wd > CCDC_GAMMA_BITS_09_0) ||
225 (ccdcparam->alaw.gama_wd < CCDC_GAMMA_BITS_15_6) ||
226 (ccdcparam->alaw.gama_wd < ccdcparam->data_sz)) {
227 dev_dbg(dev, "\nInvalid data line select");
228 return -1;
229 }
230 }
231 return 0;
232 }
233
234 static int ccdc_update_raw_params(struct ccdc_config_params_raw *raw_params)
235 {
236 struct ccdc_config_params_raw *config_params =
237 &ccdc_hw_params_raw.config_params;
238 unsigned int *fpc_virtaddr = NULL;
239 unsigned int *fpc_physaddr = NULL;
240
241 memcpy(config_params, raw_params, sizeof(*raw_params));
242 /*
243 * allocate memory for fault pixel table and copy the user
244 * values to the table
245 */
246 if (!config_params->fault_pxl.enable)
247 return 0;
248
249 fpc_physaddr = (unsigned int *)config_params->fault_pxl.fpc_table_addr;
250 fpc_virtaddr = (unsigned int *)phys_to_virt(
251 (unsigned long)fpc_physaddr);
252 /*
253 * Allocate memory for FPC table if current
254 * FPC table buffer is not big enough to
255 * accomodate FPC Number requested
256 */
257 if (raw_params->fault_pxl.fp_num != config_params->fault_pxl.fp_num) {
258 if (fpc_physaddr != NULL) {
259 free_pages((unsigned long)fpc_physaddr,
260 get_order
261 (config_params->fault_pxl.fp_num *
262 FP_NUM_BYTES));
263 }
264
265 /* Allocate memory for FPC table */
266 fpc_virtaddr =
267 (unsigned int *)__get_free_pages(GFP_KERNEL | GFP_DMA,
268 get_order(raw_params->
269 fault_pxl.fp_num *
270 FP_NUM_BYTES));
271
272 if (fpc_virtaddr == NULL) {
273 dev_dbg(dev,
274 "\nUnable to allocate memory for FPC");
275 return -EFAULT;
276 }
277 fpc_physaddr =
278 (unsigned int *)virt_to_phys((void *)fpc_virtaddr);
279 }
280
281 /* Copy number of fault pixels and FPC table */
282 config_params->fault_pxl.fp_num = raw_params->fault_pxl.fp_num;
283 if (copy_from_user(fpc_virtaddr,
284 (void __user *)raw_params->fault_pxl.fpc_table_addr,
285 config_params->fault_pxl.fp_num * FP_NUM_BYTES)) {
286 dev_dbg(dev, "\n copy_from_user failed");
287 return -EFAULT;
288 }
289 config_params->fault_pxl.fpc_table_addr = (unsigned int)fpc_physaddr;
290 return 0;
291 }
292
293 static int ccdc_close(struct device *dev)
294 {
295 struct ccdc_config_params_raw *config_params =
296 &ccdc_hw_params_raw.config_params;
297 unsigned int *fpc_physaddr = NULL, *fpc_virtaddr = NULL;
298
299 fpc_physaddr = (unsigned int *)config_params->fault_pxl.fpc_table_addr;
300
301 if (fpc_physaddr != NULL) {
302 fpc_virtaddr = (unsigned int *)
303 phys_to_virt((unsigned long)fpc_physaddr);
304 free_pages((unsigned long)fpc_virtaddr,
305 get_order(config_params->fault_pxl.fp_num *
306 FP_NUM_BYTES));
307 }
308 return 0;
309 }
310
311 /*
312 * ccdc_restore_defaults()
313 * This function will write defaults to all CCDC registers
314 */
315 static void ccdc_restore_defaults(void)
316 {
317 int i;
318
319 /* disable CCDC */
320 ccdc_enable(0);
321 /* set all registers to default value */
322 for (i = 4; i <= 0x94; i += 4)
323 regw(0, i);
324 regw(CCDC_NO_CULLING, CCDC_CULLING);
325 regw(CCDC_GAMMA_BITS_11_2, CCDC_ALAW);
326 }
327
328 static int ccdc_open(struct device *device)
329 {
330 dev = device;
331 ccdc_restore_defaults();
332 if (ccdc_if_type == VPFE_RAW_BAYER)
333 ccdc_enable_vport(1);
334 return 0;
335 }
336
337 static void ccdc_sbl_reset(void)
338 {
339 vpss_clear_wbl_overflow(VPSS_PCR_CCDC_WBL_O);
340 }
341
342 /* Parameter operations */
343 static int ccdc_set_params(void __user *params)
344 {
345 struct ccdc_config_params_raw ccdc_raw_params;
346 int x;
347
348 if (ccdc_if_type != VPFE_RAW_BAYER)
349 return -EINVAL;
350
351 x = copy_from_user(&ccdc_raw_params, params, sizeof(ccdc_raw_params));
352 if (x) {
353 dev_dbg(dev, "ccdc_set_params: error in copying"
354 "ccdc params, %d\n", x);
355 return -EFAULT;
356 }
357
358 if (!validate_ccdc_param(&ccdc_raw_params)) {
359 if (!ccdc_update_raw_params(&ccdc_raw_params))
360 return 0;
361 }
362 return -EINVAL;
363 }
364
365 /*
366 * ccdc_config_ycbcr()
367 * This function will configure CCDC for YCbCr video capture
368 */
369 void ccdc_config_ycbcr(void)
370 {
371 struct ccdc_params_ycbcr *params = &ccdc_hw_params_ycbcr;
372 u32 syn_mode;
373
374 dev_dbg(dev, "\nStarting ccdc_config_ycbcr...");
375 /*
376 * first restore the CCDC registers to default values
377 * This is important since we assume default values to be set in
378 * a lot of registers that we didn't touch
379 */
380 ccdc_restore_defaults();
381
382 /*
383 * configure pixel format, frame format, configure video frame
384 * format, enable output to SDRAM, enable internal timing generator
385 * and 8bit pack mode
386 */
387 syn_mode = (((params->pix_fmt & CCDC_SYN_MODE_INPMOD_MASK) <<
388 CCDC_SYN_MODE_INPMOD_SHIFT) |
389 ((params->frm_fmt & CCDC_SYN_FLDMODE_MASK) <<
390 CCDC_SYN_FLDMODE_SHIFT) | CCDC_VDHDEN_ENABLE |
391 CCDC_WEN_ENABLE | CCDC_DATA_PACK_ENABLE);
392
393 /* setup BT.656 sync mode */
394 if (params->bt656_enable) {
395 regw(CCDC_REC656IF_BT656_EN, CCDC_REC656IF);
396
397 /*
398 * configure the FID, VD, HD pin polarity,
399 * fld,hd pol positive, vd negative, 8-bit data
400 */
401 syn_mode |= CCDC_SYN_MODE_VD_POL_NEGATIVE;
402 if (ccdc_if_type == VPFE_BT656_10BIT)
403 syn_mode |= CCDC_SYN_MODE_10BITS;
404 else
405 syn_mode |= CCDC_SYN_MODE_8BITS;
406 /*
407 * Enable A-Law
408 */
409 regw(regr(CCDC_ALAW) | CCDC_ALAW_ENABLE, CCDC_ALAW);
410 } else {
411 /* y/c external sync mode */
412 syn_mode |= (((params->fid_pol & CCDC_FID_POL_MASK) <<
413 CCDC_FID_POL_SHIFT) |
414 ((params->hd_pol & CCDC_HD_POL_MASK) <<
415 CCDC_HD_POL_SHIFT) |
416 ((params->vd_pol & CCDC_VD_POL_MASK) <<
417 CCDC_VD_POL_SHIFT));
418 }
419 regw(syn_mode, CCDC_SYN_MODE);
420
421 /* configure video window */
422 ccdc_setwin(&params->win, params->frm_fmt, 2);
423
424 /*
425 * configure the order of y cb cr in SDRAM, and disable latch
426 * internal register on vsync
427 */
428 if (ccdc_if_type == VPFE_BT656_10BIT)
429 regw((params->pix_order << CCDC_CCDCFG_Y8POS_SHIFT) |
430 CCDC_LATCH_ON_VSYNC_DISABLE | CCDC_CCDCFG_BW656_10BIT,
431 CCDC_CCDCFG);
432 else
433 regw((params->pix_order << CCDC_CCDCFG_Y8POS_SHIFT) |
434 CCDC_LATCH_ON_VSYNC_DISABLE, CCDC_CCDCFG);
435
436 /*
437 * configure the horizontal line offset. This should be a
438 * on 32 byte bondary. So clear LSB 5 bits
439 */
440 regw(((params->win.width * 2 + 31) & ~0x1f), CCDC_HSIZE_OFF);
441
442 /* configure the memory line offset */
443 if (params->buf_type == CCDC_BUFTYPE_FLD_INTERLEAVED)
444 /* two fields are interleaved in memory */
445 regw(CCDC_SDOFST_FIELD_INTERLEAVED, CCDC_SDOFST);
446
447 ccdc_sbl_reset();
448 dev_dbg(dev, "\nEnd of ccdc_config_ycbcr...\n");
449 }
450
451 static void ccdc_config_black_clamp(struct ccdc_black_clamp *bclamp)
452 {
453 u32 val;
454
455 if (!bclamp->enable) {
456 /* configure DCSub */
457 val = (bclamp->dc_sub) & CCDC_BLK_DC_SUB_MASK;
458 regw(val, CCDC_DCSUB);
459 dev_dbg(dev, "\nWriting 0x%x to DCSUB...\n", val);
460 regw(CCDC_CLAMP_DEFAULT_VAL, CCDC_CLAMP);
461 dev_dbg(dev, "\nWriting 0x0000 to CLAMP...\n");
462 return;
463 }
464 /*
465 * Configure gain, Start pixel, No of line to be avg,
466 * No of pixel/line to be avg, & Enable the Black clamping
467 */
468 val = ((bclamp->sgain & CCDC_BLK_SGAIN_MASK) |
469 ((bclamp->start_pixel & CCDC_BLK_ST_PXL_MASK) <<
470 CCDC_BLK_ST_PXL_SHIFT) |
471 ((bclamp->sample_ln & CCDC_BLK_SAMPLE_LINE_MASK) <<
472 CCDC_BLK_SAMPLE_LINE_SHIFT) |
473 ((bclamp->sample_pixel & CCDC_BLK_SAMPLE_LN_MASK) <<
474 CCDC_BLK_SAMPLE_LN_SHIFT) | CCDC_BLK_CLAMP_ENABLE);
475 regw(val, CCDC_CLAMP);
476 dev_dbg(dev, "\nWriting 0x%x to CLAMP...\n", val);
477 /* If Black clamping is enable then make dcsub 0 */
478 regw(CCDC_DCSUB_DEFAULT_VAL, CCDC_DCSUB);
479 dev_dbg(dev, "\nWriting 0x00000000 to DCSUB...\n");
480 }
481
482 static void ccdc_config_black_compense(struct ccdc_black_compensation *bcomp)
483 {
484 u32 val;
485
486 val = ((bcomp->b & CCDC_BLK_COMP_MASK) |
487 ((bcomp->gb & CCDC_BLK_COMP_MASK) <<
488 CCDC_BLK_COMP_GB_COMP_SHIFT) |
489 ((bcomp->gr & CCDC_BLK_COMP_MASK) <<
490 CCDC_BLK_COMP_GR_COMP_SHIFT) |
491 ((bcomp->r & CCDC_BLK_COMP_MASK) <<
492 CCDC_BLK_COMP_R_COMP_SHIFT));
493 regw(val, CCDC_BLKCMP);
494 }
495
496 static void ccdc_config_fpc(struct ccdc_fault_pixel *fpc)
497 {
498 u32 val;
499
500 /* Initially disable FPC */
501 val = CCDC_FPC_DISABLE;
502 regw(val, CCDC_FPC);
503
504 if (!fpc->enable)
505 return;
506
507 /* Configure Fault pixel if needed */
508 regw(fpc->fpc_table_addr, CCDC_FPC_ADDR);
509 dev_dbg(dev, "\nWriting 0x%x to FPC_ADDR...\n",
510 (fpc->fpc_table_addr));
511 /* Write the FPC params with FPC disable */
512 val = fpc->fp_num & CCDC_FPC_FPC_NUM_MASK;
513 regw(val, CCDC_FPC);
514
515 dev_dbg(dev, "\nWriting 0x%x to FPC...\n", val);
516 /* read the FPC register */
517 val = regr(CCDC_FPC) | CCDC_FPC_ENABLE;
518 regw(val, CCDC_FPC);
519 dev_dbg(dev, "\nWriting 0x%x to FPC...\n", val);
520 }
521
522 /*
523 * ccdc_config_raw()
524 * This function will configure CCDC for Raw capture mode
525 */
526 void ccdc_config_raw(void)
527 {
528 struct ccdc_params_raw *params = &ccdc_hw_params_raw;
529 struct ccdc_config_params_raw *config_params =
530 &ccdc_hw_params_raw.config_params;
531 unsigned int syn_mode = 0;
532 unsigned int val;
533
534 dev_dbg(dev, "\nStarting ccdc_config_raw...");
535
536 /* Reset CCDC */
537 ccdc_restore_defaults();
538
539 /* Disable latching function registers on VSYNC */
540 regw(CCDC_LATCH_ON_VSYNC_DISABLE, CCDC_CCDCFG);
541
542 /*
543 * Configure the vertical sync polarity(SYN_MODE.VDPOL),
544 * horizontal sync polarity (SYN_MODE.HDPOL), frame id polarity
545 * (SYN_MODE.FLDPOL), frame format(progressive or interlace),
546 * data size(SYNMODE.DATSIZ), &pixel format (Input mode), output
547 * SDRAM, enable internal timing generator
548 */
549 syn_mode =
550 (((params->vd_pol & CCDC_VD_POL_MASK) << CCDC_VD_POL_SHIFT) |
551 ((params->hd_pol & CCDC_HD_POL_MASK) << CCDC_HD_POL_SHIFT) |
552 ((params->fid_pol & CCDC_FID_POL_MASK) << CCDC_FID_POL_SHIFT) |
553 ((params->frm_fmt & CCDC_FRM_FMT_MASK) << CCDC_FRM_FMT_SHIFT) |
554 ((config_params->data_sz & CCDC_DATA_SZ_MASK) <<
555 CCDC_DATA_SZ_SHIFT) |
556 ((params->pix_fmt & CCDC_PIX_FMT_MASK) << CCDC_PIX_FMT_SHIFT) |
557 CCDC_WEN_ENABLE | CCDC_VDHDEN_ENABLE);
558
559 /* Enable and configure aLaw register if needed */
560 if (config_params->alaw.enable) {
561 val = ((config_params->alaw.gama_wd &
562 CCDC_ALAW_GAMA_WD_MASK) | CCDC_ALAW_ENABLE);
563 regw(val, CCDC_ALAW);
564 dev_dbg(dev, "\nWriting 0x%x to ALAW...\n", val);
565 }
566
567 /* Configure video window */
568 ccdc_setwin(&params->win, params->frm_fmt, CCDC_PPC_RAW);
569
570 /* Configure Black Clamp */
571 ccdc_config_black_clamp(&config_params->blk_clamp);
572
573 /* Configure Black level compensation */
574 ccdc_config_black_compense(&config_params->blk_comp);
575
576 /* Configure Fault Pixel Correction */
577 ccdc_config_fpc(&config_params->fault_pxl);
578
579 /* If data size is 8 bit then pack the data */
580 if ((config_params->data_sz == CCDC_DATA_8BITS) ||
581 config_params->alaw.enable)
582 syn_mode |= CCDC_DATA_PACK_ENABLE;
583
584 #ifdef CONFIG_DM644X_VIDEO_PORT_ENABLE
585 /* enable video port */
586 val = CCDC_ENABLE_VIDEO_PORT;
587 #else
588 /* disable video port */
589 val = CCDC_DISABLE_VIDEO_PORT;
590 #endif
591
592 if (config_params->data_sz == CCDC_DATA_8BITS)
593 val |= (CCDC_DATA_10BITS & CCDC_FMTCFG_VPIN_MASK)
594 << CCDC_FMTCFG_VPIN_SHIFT;
595 else
596 val |= (config_params->data_sz & CCDC_FMTCFG_VPIN_MASK)
597 << CCDC_FMTCFG_VPIN_SHIFT;
598 /* Write value in FMTCFG */
599 regw(val, CCDC_FMTCFG);
600
601 dev_dbg(dev, "\nWriting 0x%x to FMTCFG...\n", val);
602 /* Configure the color pattern according to mt9t001 sensor */
603 regw(CCDC_COLPTN_VAL, CCDC_COLPTN);
604
605 dev_dbg(dev, "\nWriting 0xBB11BB11 to COLPTN...\n");
606 /*
607 * Configure Data formatter(Video port) pixel selection
608 * (FMT_HORZ, FMT_VERT)
609 */
610 val = ((params->win.left & CCDC_FMT_HORZ_FMTSPH_MASK) <<
611 CCDC_FMT_HORZ_FMTSPH_SHIFT) |
612 (params->win.width & CCDC_FMT_HORZ_FMTLNH_MASK);
613 regw(val, CCDC_FMT_HORZ);
614
615 dev_dbg(dev, "\nWriting 0x%x to FMT_HORZ...\n", val);
616 val = (params->win.top & CCDC_FMT_VERT_FMTSLV_MASK)
617 << CCDC_FMT_VERT_FMTSLV_SHIFT;
618 if (params->frm_fmt == CCDC_FRMFMT_PROGRESSIVE)
619 val |= (params->win.height) & CCDC_FMT_VERT_FMTLNV_MASK;
620 else
621 val |= (params->win.height >> 1) & CCDC_FMT_VERT_FMTLNV_MASK;
622
623 dev_dbg(dev, "\nparams->win.height 0x%x ...\n",
624 params->win.height);
625 regw(val, CCDC_FMT_VERT);
626
627 dev_dbg(dev, "\nWriting 0x%x to FMT_VERT...\n", val);
628
629 dev_dbg(dev, "\nbelow regw(val, FMT_VERT)...");
630
631 /*
632 * Configure Horizontal offset register. If pack 8 is enabled then
633 * 1 pixel will take 1 byte
634 */
635 if ((config_params->data_sz == CCDC_DATA_8BITS) ||
636 config_params->alaw.enable)
637 regw((params->win.width + CCDC_32BYTE_ALIGN_VAL) &
638 CCDC_HSIZE_OFF_MASK, CCDC_HSIZE_OFF);
639 else
640 /* else one pixel will take 2 byte */
641 regw(((params->win.width * CCDC_TWO_BYTES_PER_PIXEL) +
642 CCDC_32BYTE_ALIGN_VAL) & CCDC_HSIZE_OFF_MASK,
643 CCDC_HSIZE_OFF);
644
645 /* Set value for SDOFST */
646 if (params->frm_fmt == CCDC_FRMFMT_INTERLACED) {
647 if (params->image_invert_enable) {
648 /* For intelace inverse mode */
649 regw(CCDC_INTERLACED_IMAGE_INVERT, CCDC_SDOFST);
650 dev_dbg(dev, "\nWriting 0x4B6D to SDOFST...\n");
651 }
652
653 else {
654 /* For intelace non inverse mode */
655 regw(CCDC_INTERLACED_NO_IMAGE_INVERT, CCDC_SDOFST);
656 dev_dbg(dev, "\nWriting 0x0249 to SDOFST...\n");
657 }
658 } else if (params->frm_fmt == CCDC_FRMFMT_PROGRESSIVE) {
659 regw(CCDC_PROGRESSIVE_NO_IMAGE_INVERT, CCDC_SDOFST);
660 dev_dbg(dev, "\nWriting 0x0000 to SDOFST...\n");
661 }
662
663 /*
664 * Configure video port pixel selection (VPOUT)
665 * Here -1 is to make the height value less than FMT_VERT.FMTLNV
666 */
667 if (params->frm_fmt == CCDC_FRMFMT_PROGRESSIVE)
668 val = (((params->win.height - 1) & CCDC_VP_OUT_VERT_NUM_MASK))
669 << CCDC_VP_OUT_VERT_NUM_SHIFT;
670 else
671 val =
672 ((((params->win.height >> CCDC_INTERLACED_HEIGHT_SHIFT) -
673 1) & CCDC_VP_OUT_VERT_NUM_MASK)) <<
674 CCDC_VP_OUT_VERT_NUM_SHIFT;
675
676 val |= ((((params->win.width))) & CCDC_VP_OUT_HORZ_NUM_MASK)
677 << CCDC_VP_OUT_HORZ_NUM_SHIFT;
678 val |= (params->win.left) & CCDC_VP_OUT_HORZ_ST_MASK;
679 regw(val, CCDC_VP_OUT);
680
681 dev_dbg(dev, "\nWriting 0x%x to VP_OUT...\n", val);
682 regw(syn_mode, CCDC_SYN_MODE);
683 dev_dbg(dev, "\nWriting 0x%x to SYN_MODE...\n", syn_mode);
684
685 ccdc_sbl_reset();
686 dev_dbg(dev, "\nend of ccdc_config_raw...");
687 ccdc_readregs();
688 }
689
690 static int ccdc_configure(void)
691 {
692 if (ccdc_if_type == VPFE_RAW_BAYER)
693 ccdc_config_raw();
694 else
695 ccdc_config_ycbcr();
696 return 0;
697 }
698
699 static int ccdc_set_buftype(enum ccdc_buftype buf_type)
700 {
701 if (ccdc_if_type == VPFE_RAW_BAYER)
702 ccdc_hw_params_raw.buf_type = buf_type;
703 else
704 ccdc_hw_params_ycbcr.buf_type = buf_type;
705 return 0;
706 }
707
708 static enum ccdc_buftype ccdc_get_buftype(void)
709 {
710 if (ccdc_if_type == VPFE_RAW_BAYER)
711 return ccdc_hw_params_raw.buf_type;
712 return ccdc_hw_params_ycbcr.buf_type;
713 }
714
715 static int ccdc_enum_pix(u32 *pix, int i)
716 {
717 int ret = -EINVAL;
718 if (ccdc_if_type == VPFE_RAW_BAYER) {
719 if (i < ARRAY_SIZE(ccdc_raw_bayer_pix_formats)) {
720 *pix = ccdc_raw_bayer_pix_formats[i];
721 ret = 0;
722 }
723 } else {
724 if (i < ARRAY_SIZE(ccdc_raw_yuv_pix_formats)) {
725 *pix = ccdc_raw_yuv_pix_formats[i];
726 ret = 0;
727 }
728 }
729 return ret;
730 }
731
732 static int ccdc_set_pixel_format(u32 pixfmt)
733 {
734 if (ccdc_if_type == VPFE_RAW_BAYER) {
735 ccdc_hw_params_raw.pix_fmt = CCDC_PIXFMT_RAW;
736 if (pixfmt == V4L2_PIX_FMT_SBGGR8)
737 ccdc_hw_params_raw.config_params.alaw.enable = 1;
738 else if (pixfmt != V4L2_PIX_FMT_SBGGR16)
739 return -EINVAL;
740 } else {
741 if (pixfmt == V4L2_PIX_FMT_YUYV)
742 ccdc_hw_params_ycbcr.pix_order = CCDC_PIXORDER_YCBYCR;
743 else if (pixfmt == V4L2_PIX_FMT_UYVY)
744 ccdc_hw_params_ycbcr.pix_order = CCDC_PIXORDER_CBYCRY;
745 else
746 return -EINVAL;
747 }
748 return 0;
749 }
750
751 static u32 ccdc_get_pixel_format(void)
752 {
753 struct ccdc_a_law *alaw =
754 &ccdc_hw_params_raw.config_params.alaw;
755 u32 pixfmt;
756
757 if (ccdc_if_type == VPFE_RAW_BAYER)
758 if (alaw->enable)
759 pixfmt = V4L2_PIX_FMT_SBGGR8;
760 else
761 pixfmt = V4L2_PIX_FMT_SBGGR16;
762 else {
763 if (ccdc_hw_params_ycbcr.pix_order == CCDC_PIXORDER_YCBYCR)
764 pixfmt = V4L2_PIX_FMT_YUYV;
765 else
766 pixfmt = V4L2_PIX_FMT_UYVY;
767 }
768 return pixfmt;
769 }
770
771 static int ccdc_set_image_window(struct v4l2_rect *win)
772 {
773 if (ccdc_if_type == VPFE_RAW_BAYER)
774 ccdc_hw_params_raw.win = *win;
775 else
776 ccdc_hw_params_ycbcr.win = *win;
777 return 0;
778 }
779
780 static void ccdc_get_image_window(struct v4l2_rect *win)
781 {
782 if (ccdc_if_type == VPFE_RAW_BAYER)
783 *win = ccdc_hw_params_raw.win;
784 else
785 *win = ccdc_hw_params_ycbcr.win;
786 }
787
788 static unsigned int ccdc_get_line_length(void)
789 {
790 struct ccdc_config_params_raw *config_params =
791 &ccdc_hw_params_raw.config_params;
792 unsigned int len;
793
794 if (ccdc_if_type == VPFE_RAW_BAYER) {
795 if ((config_params->alaw.enable) ||
796 (config_params->data_sz == CCDC_DATA_8BITS))
797 len = ccdc_hw_params_raw.win.width;
798 else
799 len = ccdc_hw_params_raw.win.width * 2;
800 } else
801 len = ccdc_hw_params_ycbcr.win.width * 2;
802 return ALIGN(len, 32);
803 }
804
805 static int ccdc_set_frame_format(enum ccdc_frmfmt frm_fmt)
806 {
807 if (ccdc_if_type == VPFE_RAW_BAYER)
808 ccdc_hw_params_raw.frm_fmt = frm_fmt;
809 else
810 ccdc_hw_params_ycbcr.frm_fmt = frm_fmt;
811 return 0;
812 }
813
814 static enum ccdc_frmfmt ccdc_get_frame_format(void)
815 {
816 if (ccdc_if_type == VPFE_RAW_BAYER)
817 return ccdc_hw_params_raw.frm_fmt;
818 else
819 return ccdc_hw_params_ycbcr.frm_fmt;
820 }
821
822 static int ccdc_getfid(void)
823 {
824 return (regr(CCDC_SYN_MODE) >> 15) & 1;
825 }
826
827 /* misc operations */
828 static inline void ccdc_setfbaddr(unsigned long addr)
829 {
830 regw(addr & 0xffffffe0, CCDC_SDR_ADDR);
831 }
832
833 static int ccdc_set_hw_if_params(struct vpfe_hw_if_param *params)
834 {
835 ccdc_if_type = params->if_type;
836
837 switch (params->if_type) {
838 case VPFE_BT656:
839 case VPFE_YCBCR_SYNC_16:
840 case VPFE_YCBCR_SYNC_8:
841 case VPFE_BT656_10BIT:
842 ccdc_hw_params_ycbcr.vd_pol = params->vdpol;
843 ccdc_hw_params_ycbcr.hd_pol = params->hdpol;
844 break;
845 default:
846 /* TODO add support for raw bayer here */
847 return -EINVAL;
848 }
849 return 0;
850 }
851
852 static void ccdc_save_context(void)
853 {
854 ccdc_ctx[CCDC_PCR] = regr(CCDC_PCR);
855 ccdc_ctx[CCDC_SYN_MODE] = regr(CCDC_SYN_MODE);
856 ccdc_ctx[CCDC_HD_VD_WID] = regr(CCDC_HD_VD_WID);
857 ccdc_ctx[CCDC_PIX_LINES] = regr(CCDC_PIX_LINES);
858 ccdc_ctx[CCDC_HORZ_INFO] = regr(CCDC_HORZ_INFO);
859 ccdc_ctx[CCDC_VERT_START] = regr(CCDC_VERT_START);
860 ccdc_ctx[CCDC_VERT_LINES] = regr(CCDC_VERT_LINES);
861 ccdc_ctx[CCDC_CULLING] = regr(CCDC_CULLING);
862 ccdc_ctx[CCDC_HSIZE_OFF] = regr(CCDC_HSIZE_OFF);
863 ccdc_ctx[CCDC_SDOFST] = regr(CCDC_SDOFST);
864 ccdc_ctx[CCDC_SDR_ADDR] = regr(CCDC_SDR_ADDR);
865 ccdc_ctx[CCDC_CLAMP] = regr(CCDC_CLAMP);
866 ccdc_ctx[CCDC_DCSUB] = regr(CCDC_DCSUB);
867 ccdc_ctx[CCDC_COLPTN] = regr(CCDC_COLPTN);
868 ccdc_ctx[CCDC_BLKCMP] = regr(CCDC_BLKCMP);
869 ccdc_ctx[CCDC_FPC] = regr(CCDC_FPC);
870 ccdc_ctx[CCDC_FPC_ADDR] = regr(CCDC_FPC_ADDR);
871 ccdc_ctx[CCDC_VDINT] = regr(CCDC_VDINT);
872 ccdc_ctx[CCDC_ALAW] = regr(CCDC_ALAW);
873 ccdc_ctx[CCDC_REC656IF] = regr(CCDC_REC656IF);
874 ccdc_ctx[CCDC_CCDCFG] = regr(CCDC_CCDCFG);
875 ccdc_ctx[CCDC_FMTCFG] = regr(CCDC_FMTCFG);
876 ccdc_ctx[CCDC_FMT_HORZ] = regr(CCDC_FMT_HORZ);
877 ccdc_ctx[CCDC_FMT_VERT] = regr(CCDC_FMT_VERT);
878 ccdc_ctx[CCDC_FMT_ADDR0] = regr(CCDC_FMT_ADDR0);
879 ccdc_ctx[CCDC_FMT_ADDR1] = regr(CCDC_FMT_ADDR1);
880 ccdc_ctx[CCDC_FMT_ADDR2] = regr(CCDC_FMT_ADDR2);
881 ccdc_ctx[CCDC_FMT_ADDR3] = regr(CCDC_FMT_ADDR3);
882 ccdc_ctx[CCDC_FMT_ADDR4] = regr(CCDC_FMT_ADDR4);
883 ccdc_ctx[CCDC_FMT_ADDR5] = regr(CCDC_FMT_ADDR5);
884 ccdc_ctx[CCDC_FMT_ADDR6] = regr(CCDC_FMT_ADDR6);
885 ccdc_ctx[CCDC_FMT_ADDR7] = regr(CCDC_FMT_ADDR7);
886 ccdc_ctx[CCDC_PRGEVEN_0] = regr(CCDC_PRGEVEN_0);
887 ccdc_ctx[CCDC_PRGEVEN_1] = regr(CCDC_PRGEVEN_1);
888 ccdc_ctx[CCDC_PRGODD_0] = regr(CCDC_PRGODD_0);
889 ccdc_ctx[CCDC_PRGODD_1] = regr(CCDC_PRGODD_1);
890 ccdc_ctx[CCDC_VP_OUT] = regr(CCDC_VP_OUT);
891 }
892
893 static void ccdc_restore_context(void)
894 {
895 regw(ccdc_ctx[CCDC_SYN_MODE], CCDC_SYN_MODE);
896 regw(ccdc_ctx[CCDC_HD_VD_WID], CCDC_HD_VD_WID);
897 regw(ccdc_ctx[CCDC_PIX_LINES], CCDC_PIX_LINES);
898 regw(ccdc_ctx[CCDC_HORZ_INFO], CCDC_HORZ_INFO);
899 regw(ccdc_ctx[CCDC_VERT_START], CCDC_VERT_START);
900 regw(ccdc_ctx[CCDC_VERT_LINES], CCDC_VERT_LINES);
901 regw(ccdc_ctx[CCDC_CULLING], CCDC_CULLING);
902 regw(ccdc_ctx[CCDC_HSIZE_OFF], CCDC_HSIZE_OFF);
903 regw(ccdc_ctx[CCDC_SDOFST], CCDC_SDOFST);
904 regw(ccdc_ctx[CCDC_SDR_ADDR], CCDC_SDR_ADDR);
905 regw(ccdc_ctx[CCDC_CLAMP], CCDC_CLAMP);
906 regw(ccdc_ctx[CCDC_DCSUB], CCDC_DCSUB);
907 regw(ccdc_ctx[CCDC_COLPTN], CCDC_COLPTN);
908 regw(ccdc_ctx[CCDC_BLKCMP], CCDC_BLKCMP);
909 regw(ccdc_ctx[CCDC_FPC], CCDC_FPC);
910 regw(ccdc_ctx[CCDC_FPC_ADDR], CCDC_FPC_ADDR);
911 regw(ccdc_ctx[CCDC_VDINT], CCDC_VDINT);
912 regw(ccdc_ctx[CCDC_ALAW], CCDC_ALAW);
913 regw(ccdc_ctx[CCDC_REC656IF], CCDC_REC656IF);
914 regw(ccdc_ctx[CCDC_CCDCFG], CCDC_CCDCFG);
915 regw(ccdc_ctx[CCDC_FMTCFG], CCDC_FMTCFG);
916 regw(ccdc_ctx[CCDC_FMT_HORZ], CCDC_FMT_HORZ);
917 regw(ccdc_ctx[CCDC_FMT_VERT], CCDC_FMT_VERT);
918 regw(ccdc_ctx[CCDC_FMT_ADDR0], CCDC_FMT_ADDR0);
919 regw(ccdc_ctx[CCDC_FMT_ADDR1], CCDC_FMT_ADDR1);
920 regw(ccdc_ctx[CCDC_FMT_ADDR2], CCDC_FMT_ADDR2);
921 regw(ccdc_ctx[CCDC_FMT_ADDR3], CCDC_FMT_ADDR3);
922 regw(ccdc_ctx[CCDC_FMT_ADDR4], CCDC_FMT_ADDR4);
923 regw(ccdc_ctx[CCDC_FMT_ADDR5], CCDC_FMT_ADDR5);
924 regw(ccdc_ctx[CCDC_FMT_ADDR6], CCDC_FMT_ADDR6);
925 regw(ccdc_ctx[CCDC_FMT_ADDR7], CCDC_FMT_ADDR7);
926 regw(ccdc_ctx[CCDC_PRGEVEN_0], CCDC_PRGEVEN_0);
927 regw(ccdc_ctx[CCDC_PRGEVEN_1], CCDC_PRGEVEN_1);
928 regw(ccdc_ctx[CCDC_PRGODD_0], CCDC_PRGODD_0);
929 regw(ccdc_ctx[CCDC_PRGODD_1], CCDC_PRGODD_1);
930 regw(ccdc_ctx[CCDC_VP_OUT], CCDC_VP_OUT);
931 regw(ccdc_ctx[CCDC_PCR], CCDC_PCR);
932 }
933 static struct ccdc_hw_device ccdc_hw_dev = {
934 .name = "DM6446 CCDC",
935 .owner = THIS_MODULE,
936 .hw_ops = {
937 .open = ccdc_open,
938 .close = ccdc_close,
939 .set_ccdc_base = ccdc_set_ccdc_base,
940 .reset = ccdc_sbl_reset,
941 .enable = ccdc_enable,
942 .set_hw_if_params = ccdc_set_hw_if_params,
943 .set_params = ccdc_set_params,
944 .configure = ccdc_configure,
945 .set_buftype = ccdc_set_buftype,
946 .get_buftype = ccdc_get_buftype,
947 .enum_pix = ccdc_enum_pix,
948 .set_pixel_format = ccdc_set_pixel_format,
949 .get_pixel_format = ccdc_get_pixel_format,
950 .set_frame_format = ccdc_set_frame_format,
951 .get_frame_format = ccdc_get_frame_format,
952 .set_image_window = ccdc_set_image_window,
953 .get_image_window = ccdc_get_image_window,
954 .get_line_length = ccdc_get_line_length,
955 .setfbaddr = ccdc_setfbaddr,
956 .getfid = ccdc_getfid,
957 .save_context = ccdc_save_context,
958 .restore_context = ccdc_restore_context,
959 },
960 };
961
962 static int dm644x_ccdc_init(void)
963 {
964 printk(KERN_NOTICE "dm644x_ccdc_init\n");
965 if (vpfe_register_ccdc_device(&ccdc_hw_dev) < 0)
966 return -1;
967 printk(KERN_NOTICE "%s is registered with vpfe.\n",
968 ccdc_hw_dev.name);
969 return 0;
970 }
971
972 static void dm644x_ccdc_exit(void)
973 {
974 vpfe_unregister_ccdc_device(&ccdc_hw_dev);
975 }
976
977 module_init(dm644x_ccdc_init);
978 module_exit(dm644x_ccdc_exit);
Linux for Ginger Game Console