| blob | b18d166f18159c94d2fac1eb5e422c2138866589 |
1 /*
2 * Copyright (C) 2006-2009 Texas Instruments Inc
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18 #ifndef _DM644X_CCDC_REGS_H
19 #define _DM644X_CCDC_REGS_H
21 /**************************************************************************\
22 * Register OFFSET Definitions
23 \**************************************************************************/
24 #define CCDC_PID 0x0
25 #define CCDC_PCR 0x4
26 #define CCDC_SYN_MODE 0x8
27 #define CCDC_HD_VD_WID 0xc
28 #define CCDC_PIX_LINES 0x10
29 #define CCDC_HORZ_INFO 0x14
30 #define CCDC_VERT_START 0x18
31 #define CCDC_VERT_LINES 0x1c
32 #define CCDC_CULLING 0x20
33 #define CCDC_HSIZE_OFF 0x24
34 #define CCDC_SDOFST 0x28
35 #define CCDC_SDR_ADDR 0x2c
36 #define CCDC_CLAMP 0x30
37 #define CCDC_DCSUB 0x34
38 #define CCDC_COLPTN 0x38
39 #define CCDC_BLKCMP 0x3c
40 #define CCDC_FPC 0x40
41 #define CCDC_FPC_ADDR 0x44
42 #define CCDC_VDINT 0x48
43 #define CCDC_ALAW 0x4c
44 #define CCDC_REC656IF 0x50
45 #define CCDC_CCDCFG 0x54
46 #define CCDC_FMTCFG 0x58
47 #define CCDC_FMT_HORZ 0x5c
48 #define CCDC_FMT_VERT 0x60
49 #define CCDC_FMT_ADDR0 0x64
50 #define CCDC_FMT_ADDR1 0x68
51 #define CCDC_FMT_ADDR2 0x6c
52 #define CCDC_FMT_ADDR3 0x70
53 #define CCDC_FMT_ADDR4 0x74
54 #define CCDC_FMT_ADDR5 0x78
55 #define CCDC_FMT_ADDR6 0x7c
56 #define CCDC_FMT_ADDR7 0x80
57 #define CCDC_PRGEVEN_0 0x84
58 #define CCDC_PRGEVEN_1 0x88
59 #define CCDC_PRGODD_0 0x8c
60 #define CCDC_PRGODD_1 0x90
61 #define CCDC_VP_OUT 0x94
64 /***************************************************************
65 * Define for various register bit mask and shifts for CCDC
66 ****************************************************************/
67 #define CCDC_FID_POL_MASK 1
68 #define CCDC_FID_POL_SHIFT 4
69 #define CCDC_HD_POL_MASK 1
70 #define CCDC_HD_POL_SHIFT 3
71 #define CCDC_VD_POL_MASK 1
72 #define CCDC_VD_POL_SHIFT 2
73 #define CCDC_HSIZE_OFF_MASK 0xffffffe0
74 #define CCDC_32BYTE_ALIGN_VAL 31
75 #define CCDC_FRM_FMT_MASK 0x1
76 #define CCDC_FRM_FMT_SHIFT 7
77 #define CCDC_DATA_SZ_MASK 7
78 #define CCDC_DATA_SZ_SHIFT 8
79 #define CCDC_PIX_FMT_MASK 3
80 #define CCDC_PIX_FMT_SHIFT 12
81 #define CCDC_VP2SDR_DISABLE 0xFFFBFFFF
82 #define CCDC_WEN_ENABLE (1 << 17)
83 #define CCDC_SDR2RSZ_DISABLE 0xFFF7FFFF
84 #define CCDC_VDHDEN_ENABLE (1 << 16)
85 #define CCDC_LPF_ENABLE (1 << 14)
86 #define CCDC_ALAW_ENABLE (1 << 3)
87 #define CCDC_ALAW_GAMA_WD_MASK 7
88 #define CCDC_BLK_CLAMP_ENABLE (1 << 31)
89 #define CCDC_BLK_SGAIN_MASK 0x1F
90 #define CCDC_BLK_ST_PXL_MASK 0x7FFF
91 #define CCDC_BLK_ST_PXL_SHIFT 10
92 #define CCDC_BLK_SAMPLE_LN_MASK 7
93 #define CCDC_BLK_SAMPLE_LN_SHIFT 28
94 #define CCDC_BLK_SAMPLE_LINE_MASK 7
95 #define CCDC_BLK_SAMPLE_LINE_SHIFT 25
96 #define CCDC_BLK_DC_SUB_MASK 0x03FFF
97 #define CCDC_BLK_COMP_MASK 0xFF
98 #define CCDC_BLK_COMP_GB_COMP_SHIFT 8
99 #define CCDC_BLK_COMP_GR_COMP_SHIFT 16
100 #define CCDC_BLK_COMP_R_COMP_SHIFT 24
101 #define CCDC_LATCH_ON_VSYNC_DISABLE (1 << 15)
102 #define CCDC_FPC_ENABLE (1 << 15)
103 #define CCDC_FPC_DISABLE 0
104 #define CCDC_FPC_FPC_NUM_MASK 0x7FFF
105 #define CCDC_DATA_PACK_ENABLE (1 << 11)
106 #define CCDC_FMTCFG_VPIN_MASK 7
107 #define CCDC_FMTCFG_VPIN_SHIFT 12
108 #define CCDC_FMT_HORZ_FMTLNH_MASK 0x1FFF
109 #define CCDC_FMT_HORZ_FMTSPH_MASK 0x1FFF
110 #define CCDC_FMT_HORZ_FMTSPH_SHIFT 16
111 #define CCDC_FMT_VERT_FMTLNV_MASK 0x1FFF
112 #define CCDC_FMT_VERT_FMTSLV_MASK 0x1FFF
113 #define CCDC_FMT_VERT_FMTSLV_SHIFT 16
114 #define CCDC_VP_OUT_VERT_NUM_MASK 0x3FFF
115 #define CCDC_VP_OUT_VERT_NUM_SHIFT 17
116 #define CCDC_VP_OUT_HORZ_NUM_MASK 0x1FFF
117 #define CCDC_VP_OUT_HORZ_NUM_SHIFT 4
118 #define CCDC_VP_OUT_HORZ_ST_MASK 0xF
119 #define CCDC_HORZ_INFO_SPH_SHIFT 16
120 #define CCDC_VERT_START_SLV0_SHIFT 16
121 #define CCDC_VDINT_VDINT0_SHIFT 16
122 #define CCDC_VDINT_VDINT1_MASK 0xFFFF
123 #define CCDC_PPC_RAW 1
124 #define CCDC_DCSUB_DEFAULT_VAL 0
125 #define CCDC_CLAMP_DEFAULT_VAL 0
126 #define CCDC_ENABLE_VIDEO_PORT 0x8000
127 #define CCDC_DISABLE_VIDEO_PORT 0
128 #define CCDC_COLPTN_VAL 0xBB11BB11
129 #define CCDC_TWO_BYTES_PER_PIXEL 2
130 #define CCDC_INTERLACED_IMAGE_INVERT 0x4B6D
131 #define CCDC_INTERLACED_NO_IMAGE_INVERT 0x0249
132 #define CCDC_PROGRESSIVE_IMAGE_INVERT 0x4000
133 #define CCDC_PROGRESSIVE_NO_IMAGE_INVERT 0
134 #define CCDC_INTERLACED_HEIGHT_SHIFT 1
135 #define CCDC_SYN_MODE_INPMOD_SHIFT 12
136 #define CCDC_SYN_MODE_INPMOD_MASK 3
137 #define CCDC_SYN_MODE_8BITS (7 << 8)
138 #define CCDC_SYN_MODE_10BITS (6 << 8)
139 #define CCDC_SYN_MODE_11BITS (5 << 8)
140 #define CCDC_SYN_MODE_12BITS (4 << 8)
141 #define CCDC_SYN_MODE_13BITS (3 << 8)
142 #define CCDC_SYN_MODE_14BITS (2 << 8)
143 #define CCDC_SYN_MODE_15BITS (1 << 8)
144 #define CCDC_SYN_MODE_16BITS (0 << 8)
145 #define CCDC_SYN_FLDMODE_MASK 1
146 #define CCDC_SYN_FLDMODE_SHIFT 7
147 #define CCDC_REC656IF_BT656_EN 3
148 #define CCDC_SYN_MODE_VD_POL_NEGATIVE (1 << 2)
149 #define CCDC_CCDCFG_Y8POS_SHIFT 11
150 #define CCDC_CCDCFG_BW656_10BIT (1 << 5)
151 #define CCDC_SDOFST_FIELD_INTERLEAVED 0x249
152 #define CCDC_NO_CULLING 0xffff00ff
153 #endif