drivers/net/vmxnet3/vmxnet3_defs.h

   1 /*
   2  * Linux driver for VMware's vmxnet3 ethernet NIC.
   3  *
   4  * Copyright (C) 2008-2009, VMware, Inc. All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License as published by the
   8  * Free Software Foundation; version 2 of the License and no later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  13  * NON INFRINGEMENT.  See the GNU General Public License for more
  14  * details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * The full GNU General Public License is included in this distribution in
  21  * the file called "COPYING".
  22  *
  23  * Maintained by: Shreyas Bhatewara <pv-drivers@vmware.com>
  24  *
  25  */
  26
  27 #ifndef _VMXNET3_DEFS_H_
  28 #define _VMXNET3_DEFS_H_
  29
  30 #include "upt1_defs.h"
  31
  32 /* all registers are 32 bit wide */
  33 /* BAR 1 */
  34 enum {
  35         VMXNET3_REG_VRRS        = 0x0,  /* Vmxnet3 Revision Report Selection */
  36         VMXNET3_REG_UVRS        = 0x8,  /* UPT Version Report Selection */
  37         VMXNET3_REG_DSAL        = 0x10, /* Driver Shared Address Low */
  38         VMXNET3_REG_DSAH        = 0x18, /* Driver Shared Address High */
  39         VMXNET3_REG_CMD         = 0x20, /* Command */
  40         VMXNET3_REG_MACL        = 0x28, /* MAC Address Low */
  41         VMXNET3_REG_MACH        = 0x30, /* MAC Address High */
  42         VMXNET3_REG_ICR         = 0x38, /* Interrupt Cause Register */
  43         VMXNET3_REG_ECR         = 0x40  /* Event Cause Register */
  44 };
  45
  46 /* BAR 0 */
  47 enum {
  48         VMXNET3_REG_IMR         = 0x0,   /* Interrupt Mask Register */
  49         VMXNET3_REG_TXPROD      = 0x600, /* Tx Producer Index */
  50         VMXNET3_REG_RXPROD      = 0x800, /* Rx Producer Index for ring 1 */
  51         VMXNET3_REG_RXPROD2     = 0xA00  /* Rx Producer Index for ring 2 */
  52 };
  53
  54 #define VMXNET3_PT_REG_SIZE     4096    /* BAR 0 */
  55 #define VMXNET3_VD_REG_SIZE     4096    /* BAR 1 */
  56
  57 #define VMXNET3_REG_ALIGN       8       /* All registers are 8-byte aligned. */
  58 #define VMXNET3_REG_ALIGN_MASK  0x7
  59
  60 /* I/O Mapped access to registers */
  61 #define VMXNET3_IO_TYPE_PT              0
  62 #define VMXNET3_IO_TYPE_VD              1
  63 #define VMXNET3_IO_ADDR(type, reg)      (((type) << 24) | ((reg) & 0xFFFFFF))
  64 #define VMXNET3_IO_TYPE(addr)           ((addr) >> 24)
  65 #define VMXNET3_IO_REG(addr)            ((addr) & 0xFFFFFF)
  66
  67 enum {
  68         VMXNET3_CMD_FIRST_SET = 0xCAFE0000,
  69         VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET,
  70         VMXNET3_CMD_QUIESCE_DEV,
  71         VMXNET3_CMD_RESET_DEV,
  72         VMXNET3_CMD_UPDATE_RX_MODE,
  73         VMXNET3_CMD_UPDATE_MAC_FILTERS,
  74         VMXNET3_CMD_UPDATE_VLAN_FILTERS,
  75         VMXNET3_CMD_UPDATE_RSSIDT,
  76         VMXNET3_CMD_UPDATE_IML,
  77         VMXNET3_CMD_UPDATE_PMCFG,
  78         VMXNET3_CMD_UPDATE_FEATURE,
  79         VMXNET3_CMD_LOAD_PLUGIN,
  80
  81         VMXNET3_CMD_FIRST_GET = 0xF00D0000,
  82         VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET,
  83         VMXNET3_CMD_GET_STATS,
  84         VMXNET3_CMD_GET_LINK,
  85         VMXNET3_CMD_GET_PERM_MAC_LO,
  86         VMXNET3_CMD_GET_PERM_MAC_HI,
  87         VMXNET3_CMD_GET_DID_LO,
  88         VMXNET3_CMD_GET_DID_HI,
  89         VMXNET3_CMD_GET_DEV_EXTRA_INFO,
  90         VMXNET3_CMD_GET_CONF_INTR
  91 };
  92
  93 struct Vmxnet3_TxDesc {
  94         u64             addr;
  95
  96         u32             len:14;
  97         u32             gen:1;      /* generation bit */
  98         u32             rsvd:1;
  99         u32             dtype:1;    /* descriptor type */
 100         u32             ext1:1;
 101         u32             msscof:14;  /* MSS, checksum offset, flags */
 102
 103         u32             hlen:10;    /* header len */
 104         u32             om:2;       /* offload mode */
 105         u32             eop:1;      /* End Of Packet */
 106         u32             cq:1;       /* completion request */
 107         u32             ext2:1;
 108         u32             ti:1;       /* VLAN Tag Insertion */
 109         u32             tci:16;     /* Tag to Insert */
 110 };
 111
 112 /* TxDesc.OM values */
 113 #define VMXNET3_OM_NONE         0
 114 #define VMXNET3_OM_CSUM         2
 115 #define VMXNET3_OM_TSO          3
 116
 117 /* fields in TxDesc we access w/o using bit fields */
 118 #define VMXNET3_TXD_EOP_SHIFT   12
 119 #define VMXNET3_TXD_CQ_SHIFT    13
 120 #define VMXNET3_TXD_GEN_SHIFT   14
 121
 122 #define VMXNET3_TXD_CQ          (1 << VMXNET3_TXD_CQ_SHIFT)
 123 #define VMXNET3_TXD_EOP         (1 << VMXNET3_TXD_EOP_SHIFT)
 124 #define VMXNET3_TXD_GEN         (1 << VMXNET3_TXD_GEN_SHIFT)
 125
 126 #define VMXNET3_HDR_COPY_SIZE   128
 127
 128
 129 struct Vmxnet3_TxDataDesc {
 130         u8              data[VMXNET3_HDR_COPY_SIZE];
 131 };
 132
 133
 134 struct Vmxnet3_TxCompDesc {
 135         u32             txdIdx:12;    /* Index of the EOP TxDesc */
 136         u32             ext1:20;
 137
 138         u32             ext2;
 139         u32             ext3;
 140
 141         u32             rsvd:24;
 142         u32             type:7;       /* completion type */
 143         u32             gen:1;        /* generation bit */
 144 };
 145
 146
 147 struct Vmxnet3_RxDesc {
 148         u64             addr;
 149
 150         u32             len:14;
 151         u32             btype:1;      /* Buffer Type */
 152         u32             dtype:1;      /* Descriptor type */
 153         u32             rsvd:15;
 154         u32             gen:1;        /* Generation bit */
 155
 156         u32             ext1;
 157 };
 158
 159 /* values of RXD.BTYPE */
 160 #define VMXNET3_RXD_BTYPE_HEAD   0    /* head only */
 161 #define VMXNET3_RXD_BTYPE_BODY   1    /* body only */
 162
 163 /* fields in RxDesc we access w/o using bit fields */
 164 #define VMXNET3_RXD_BTYPE_SHIFT  14
 165 #define VMXNET3_RXD_GEN_SHIFT    31
 166
 167
 168 struct Vmxnet3_RxCompDesc {
 169         u32             rxdIdx:12;    /* Index of the RxDesc */
 170         u32             ext1:2;
 171         u32             eop:1;        /* End of Packet */
 172         u32             sop:1;        /* Start of Packet */
 173         u32             rqID:10;      /* rx queue/ring ID */
 174         u32             rssType:4;    /* RSS hash type used */
 175         u32             cnc:1;        /* Checksum Not Calculated */
 176         u32             ext2:1;
 177
 178         u32             rssHash;      /* RSS hash value */
 179
 180         u32             len:14;       /* data length */
 181         u32             err:1;        /* Error */
 182         u32             ts:1;         /* Tag is stripped */
 183         u32             tci:16;       /* Tag stripped */
 184
 185         u32             csum:16;
 186         u32             tuc:1;        /* TCP/UDP Checksum Correct */
 187         u32             udp:1;        /* UDP packet */
 188         u32             tcp:1;        /* TCP packet */
 189         u32             ipc:1;        /* IP Checksum Correct */
 190         u32             v6:1;         /* IPv6 */
 191         u32             v4:1;         /* IPv4 */
 192         u32             frg:1;        /* IP Fragment */
 193         u32             fcs:1;        /* Frame CRC correct */
 194         u32             type:7;       /* completion type */
 195         u32             gen:1;        /* generation bit */
 196 };
 197
 198 /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.dword[3] */
 199 #define VMXNET3_RCD_TUC_SHIFT   16
 200 #define VMXNET3_RCD_IPC_SHIFT   19
 201
 202 /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.qword[1] */
 203 #define VMXNET3_RCD_TYPE_SHIFT  56
 204 #define VMXNET3_RCD_GEN_SHIFT   63
 205
 206 /* csum OK for TCP/UDP pkts over IP */
 207 #define VMXNET3_RCD_CSUM_OK (1 << VMXNET3_RCD_TUC_SHIFT | \
 208                              1 << VMXNET3_RCD_IPC_SHIFT)
 209
 210 /* value of RxCompDesc.rssType */
 211 enum {
 212         VMXNET3_RCD_RSS_TYPE_NONE     = 0,
 213         VMXNET3_RCD_RSS_TYPE_IPV4     = 1,
 214         VMXNET3_RCD_RSS_TYPE_TCPIPV4  = 2,
 215         VMXNET3_RCD_RSS_TYPE_IPV6     = 3,
 216         VMXNET3_RCD_RSS_TYPE_TCPIPV6  = 4,
 217 };
 218
 219
 220 /* a union for accessing all cmd/completion descriptors */
 221 union Vmxnet3_GenericDesc {
 222         u64                             qword[2];
 223         u32                             dword[4];
 224         u16                             word[8];
 225         struct Vmxnet3_TxDesc           txd;
 226         struct Vmxnet3_RxDesc           rxd;
 227         struct Vmxnet3_TxCompDesc       tcd;
 228         struct Vmxnet3_RxCompDesc       rcd;
 229 };
 230
 231 #define VMXNET3_INIT_GEN       1
 232
 233 /* Max size of a single tx buffer */
 234 #define VMXNET3_MAX_TX_BUF_SIZE  (1 << 14)
 235
 236 /* # of tx desc needed for a tx buffer size */
 237 #define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / \
 238                                   VMXNET3_MAX_TX_BUF_SIZE)
 239
 240 /* max # of tx descs for a non-tso pkt */
 241 #define VMXNET3_MAX_TXD_PER_PKT 16
 242
 243 /* Max size of a single rx buffer */
 244 #define VMXNET3_MAX_RX_BUF_SIZE  ((1 << 14) - 1)
 245 /* Minimum size of a type 0 buffer */
 246 #define VMXNET3_MIN_T0_BUF_SIZE  128
 247 #define VMXNET3_MAX_CSUM_OFFSET  1024
 248
 249 /* Ring base address alignment */
 250 #define VMXNET3_RING_BA_ALIGN   512
 251 #define VMXNET3_RING_BA_MASK    (VMXNET3_RING_BA_ALIGN - 1)
 252
 253 /* Ring size must be a multiple of 32 */
 254 #define VMXNET3_RING_SIZE_ALIGN 32
 255 #define VMXNET3_RING_SIZE_MASK  (VMXNET3_RING_SIZE_ALIGN - 1)
 256
 257 /* Max ring size */
 258 #define VMXNET3_TX_RING_MAX_SIZE   4096
 259 #define VMXNET3_TC_RING_MAX_SIZE   4096
 260 #define VMXNET3_RX_RING_MAX_SIZE   4096
 261 #define VMXNET3_RC_RING_MAX_SIZE   8192
 262
 263 /* a list of reasons for queue stop */
 264
 265 enum {
 266  VMXNET3_ERR_NOEOP        = 0x80000000,  /* cannot find the EOP desc of a pkt */
 267  VMXNET3_ERR_TXD_REUSE    = 0x80000001,  /* reuse TxDesc before tx completion */
 268  VMXNET3_ERR_BIG_PKT      = 0x80000002,  /* too many TxDesc for a pkt */
 269  VMXNET3_ERR_DESC_NOT_SPT = 0x80000003,  /* descriptor type not supported */
 270  VMXNET3_ERR_SMALL_BUF    = 0x80000004,  /* type 0 buffer too small */
 271  VMXNET3_ERR_STRESS       = 0x80000005,  /* stress option firing in vmkernel */
 272  VMXNET3_ERR_SWITCH       = 0x80000006,  /* mode switch failure */
 273  VMXNET3_ERR_TXD_INVALID  = 0x80000007,  /* invalid TxDesc */
 274 };
 275
 276 /* completion descriptor types */
 277 #define VMXNET3_CDTYPE_TXCOMP      0    /* Tx Completion Descriptor */
 278 #define VMXNET3_CDTYPE_RXCOMP      3    /* Rx Completion Descriptor */
 279
 280 enum {
 281         VMXNET3_GOS_BITS_UNK    = 0,   /* unknown */
 282         VMXNET3_GOS_BITS_32     = 1,
 283         VMXNET3_GOS_BITS_64     = 2,
 284 };
 285
 286 #define VMXNET3_GOS_TYPE_LINUX  1
 287
 288
 289 struct Vmxnet3_GOSInfo {
 290         u32                             gosBits:2;      /* 32-bit or 64-bit? */
 291         u32                             gosType:4;   /* which guest */
 292         u32                             gosVer:16;   /* gos version */
 293         u32                             gosMisc:10;  /* other info about gos */
 294 };
 295
 296
 297 struct Vmxnet3_DriverInfo {
 298         u32                             version;
 299         struct Vmxnet3_GOSInfo          gos;
 300         u32                             vmxnet3RevSpt;
 301         u32                             uptVerSpt;
 302 };
 303
 304
 305 #define VMXNET3_REV1_MAGIC  0xbabefee1
 306
 307 /*
 308  * QueueDescPA must be 128 bytes aligned. It points to an array of
 309  * Vmxnet3_TxQueueDesc followed by an array of Vmxnet3_RxQueueDesc.
 310  * The number of Vmxnet3_TxQueueDesc/Vmxnet3_RxQueueDesc are specified by
 311  * Vmxnet3_MiscConf.numTxQueues/numRxQueues, respectively.
 312  */
 313 #define VMXNET3_QUEUE_DESC_ALIGN  128
 314
 315
 316 struct Vmxnet3_MiscConf {
 317         struct Vmxnet3_DriverInfo driverInfo;
 318         u64             uptFeatures;
 319         u64             ddPA;         /* driver data PA */
 320         u64             queueDescPA;  /* queue descriptor table PA */
 321         u32             ddLen;        /* driver data len */
 322         u32             queueDescLen; /* queue desc. table len in bytes */
 323         u32             mtu;
 324         u16             maxNumRxSG;
 325         u8              numTxQueues;
 326         u8              numRxQueues;
 327         u32             reserved[4];
 328 };
 329
 330
 331 struct Vmxnet3_TxQueueConf {
 332         u64             txRingBasePA;
 333         u64             dataRingBasePA;
 334         u64             compRingBasePA;
 335         u64             ddPA;         /* driver data */
 336         u64             reserved;
 337         u32             txRingSize;   /* # of tx desc */
 338         u32             dataRingSize; /* # of data desc */
 339         u32             compRingSize; /* # of comp desc */
 340         u32             ddLen;        /* size of driver data */
 341         u8              intrIdx;
 342         u8              _pad[7];
 343 };
 344
 345
 346 struct Vmxnet3_RxQueueConf {
 347         u64             rxRingBasePA[2];
 348         u64             compRingBasePA;
 349         u64             ddPA;            /* driver data */
 350         u64             reserved;
 351         u32             rxRingSize[2];   /* # of rx desc */
 352         u32             compRingSize;    /* # of rx comp desc */
 353         u32             ddLen;           /* size of driver data */
 354         u8              intrIdx;
 355         u8              _pad[7];
 356 };
 357
 358
 359 enum vmxnet3_intr_mask_mode {
 360         VMXNET3_IMM_AUTO   = 0,
 361         VMXNET3_IMM_ACTIVE = 1,
 362         VMXNET3_IMM_LAZY   = 2
 363 };
 364
 365 enum vmxnet3_intr_type {
 366         VMXNET3_IT_AUTO = 0,
 367         VMXNET3_IT_INTX = 1,
 368         VMXNET3_IT_MSI  = 2,
 369         VMXNET3_IT_MSIX = 3
 370 };
 371
 372 #define VMXNET3_MAX_TX_QUEUES  8
 373 #define VMXNET3_MAX_RX_QUEUES  16
 374 /* addition 1 for events */
 375 #define VMXNET3_MAX_INTRS      25
 376
 377
 378 struct Vmxnet3_IntrConf {
 379         bool            autoMask;
 380         u8              numIntrs;      /* # of interrupts */
 381         u8              eventIntrIdx;
 382         u8              modLevels[VMXNET3_MAX_INTRS];   /* moderation level for
 383                                                          * each intr */
 384         u32             reserved[3];
 385 };
 386
 387 /* one bit per VLAN ID, the size is in the units of u32 */
 388 #define VMXNET3_VFT_SIZE  (4096 / (sizeof(u32) * 8))
 389
 390
 391 struct Vmxnet3_QueueStatus {
 392         bool            stopped;
 393         u8              _pad[3];
 394         u32             error;
 395 };
 396
 397
 398 struct Vmxnet3_TxQueueCtrl {
 399         u32             txNumDeferred;
 400         u32             txThreshold;
 401         u64             reserved;
 402 };
 403
 404
 405 struct Vmxnet3_RxQueueCtrl {
 406         bool            updateRxProd;
 407         u8              _pad[7];
 408         u64             reserved;
 409 };
 410
 411 enum {
 412         VMXNET3_RXM_UCAST     = 0x01,  /* unicast only */
 413         VMXNET3_RXM_MCAST     = 0x02,  /* multicast passing the filters */
 414         VMXNET3_RXM_BCAST     = 0x04,  /* broadcast only */
 415         VMXNET3_RXM_ALL_MULTI = 0x08,  /* all multicast */
 416         VMXNET3_RXM_PROMISC   = 0x10  /* promiscuous */
 417 };
 418
 419 struct Vmxnet3_RxFilterConf {
 420         u32             rxMode;       /* VMXNET3_RXM_xxx */
 421         u16             mfTableLen;   /* size of the multicast filter table */
 422         u16             _pad1;
 423         u64             mfTablePA;    /* PA of the multicast filters table */
 424         u32             vfTable[VMXNET3_VFT_SIZE]; /* vlan filter */
 425 };
 426
 427
 428 #define VMXNET3_PM_MAX_FILTERS        6
 429 #define VMXNET3_PM_MAX_PATTERN_SIZE   128
 430 #define VMXNET3_PM_MAX_MASK_SIZE      (VMXNET3_PM_MAX_PATTERN_SIZE / 8)
 431
 432 #define VMXNET3_PM_WAKEUP_MAGIC       0x01  /* wake up on magic pkts */
 433 #define VMXNET3_PM_WAKEUP_FILTER      0x02  /* wake up on pkts matching
 434                                              * filters */
 435
 436
 437 struct Vmxnet3_PM_PktFilter {
 438         u8              maskSize;
 439         u8              patternSize;
 440         u8              mask[VMXNET3_PM_MAX_MASK_SIZE];
 441         u8              pattern[VMXNET3_PM_MAX_PATTERN_SIZE];
 442         u8              pad[6];
 443 };
 444
 445
 446 struct Vmxnet3_PMConf {
 447         u16             wakeUpEvents;  /* VMXNET3_PM_WAKEUP_xxx */
 448         u8              numFilters;
 449         u8              pad[5];
 450         struct Vmxnet3_PM_PktFilter filters[VMXNET3_PM_MAX_FILTERS];
 451 };
 452
 453
 454 struct Vmxnet3_VariableLenConfDesc {
 455         u32             confVer;
 456         u32             confLen;
 457         u64             confPA;
 458 };
 459
 460
 461 struct Vmxnet3_TxQueueDesc {
 462         struct Vmxnet3_TxQueueCtrl              ctrl;
 463         struct Vmxnet3_TxQueueConf              conf;
 464
 465         /* Driver read after a GET command */
 466         struct Vmxnet3_QueueStatus              status;
 467         struct UPT1_TxStats                     stats;
 468         u8                                      _pad[88]; /* 128 aligned */
 469 };
 470
 471
 472 struct Vmxnet3_RxQueueDesc {
 473         struct Vmxnet3_RxQueueCtrl              ctrl;
 474         struct Vmxnet3_RxQueueConf              conf;
 475         /* Driver read after a GET commad */
 476         struct Vmxnet3_QueueStatus              status;
 477         struct UPT1_RxStats                     stats;
 478         u8                                    __pad[88]; /* 128 aligned */
 479 };
 480
 481
 482 struct Vmxnet3_DSDevRead {
 483         /* read-only region for device, read by dev in response to a SET cmd */
 484         struct Vmxnet3_MiscConf                 misc;
 485         struct Vmxnet3_IntrConf                 intrConf;
 486         struct Vmxnet3_RxFilterConf             rxFilterConf;
 487         struct Vmxnet3_VariableLenConfDesc      rssConfDesc;
 488         struct Vmxnet3_VariableLenConfDesc      pmConfDesc;
 489         struct Vmxnet3_VariableLenConfDesc      pluginConfDesc;
 490 };
 491
 492 /* All structures in DriverShared are padded to multiples of 8 bytes */
 493 struct Vmxnet3_DriverShared {
 494         u32                             magic;
 495         /* make devRead start at 64bit boundaries */
 496         u32                                     pad;
 497         struct Vmxnet3_DSDevRead                devRead;
 498         u32                                     ecr;
 499         u32                                     reserved[5];
 500 };
 501
 502
 503 #define VMXNET3_ECR_RQERR       (1 << 0)
 504 #define VMXNET3_ECR_TQERR       (1 << 1)
 505 #define VMXNET3_ECR_LINK        (1 << 2)
 506 #define VMXNET3_ECR_DIC         (1 << 3)
 507 #define VMXNET3_ECR_DEBUG       (1 << 4)
 508
 509 /* flip the gen bit of a ring */
 510 #define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1)
 511
 512 /* only use this if moving the idx won't affect the gen bit */
 513 #define VMXNET3_INC_RING_IDX_ONLY(idx, ring_size) \
 514         do {\
 515                 (idx)++;\
 516                 if (unlikely((idx) == (ring_size))) {\
 517                         (idx) = 0;\
 518                 } \
 519         } while (0)
 520
 521 #define VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid) \
 522         (vfTable[vid >> 5] |= (1 << (vid & 31)))
 523 #define VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid) \
 524         (vfTable[vid >> 5] &= ~(1 << (vid & 31)))
 525
 526 #define VMXNET3_VFTABLE_ENTRY_IS_SET(vfTable, vid) \
 527         ((vfTable[vid >> 5] & (1 << (vid & 31))) != 0)
 528
 529 #define VMXNET3_MAX_MTU     9000
 530 #define VMXNET3_MIN_MTU     60
 531
 532 #define VMXNET3_LINK_UP         (10000 << 16 | 1)    /* 10 Gbps, up */
 533 #define VMXNET3_LINK_DOWN       0
 534
 535 #endif /* _VMXNET3_DEFS_H_ */