drivers/scsi/mvsas/mv_64xx.h

   1 /*
   2  * Marvell 88SE64xx hardware specific head file
   3  *
   4  * Copyright 2007 Red Hat, Inc.
   5  * Copyright 2008 Marvell. <kewei@marvell.com>
   6  *
   7  * This file is licensed under GPLv2.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; version 2 of the
  12  * License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
  22  * USA
  23 */
  24
  25 #ifndef _MVS64XX_REG_H_
  26 #define _MVS64XX_REG_H_
  27
  28 #include <linux/types.h>
  29
  30 #define MAX_LINK_RATE           SAS_LINK_RATE_3_0_GBPS
  31
  32 /* enhanced mode registers (BAR4) */
  33 enum hw_registers {
  34         MVS_GBL_CTL             = 0x04,  /* global control */
  35         MVS_GBL_INT_STAT        = 0x08,  /* global irq status */
  36         MVS_GBL_PI              = 0x0C,  /* ports implemented bitmask */
  37
  38         MVS_PHY_CTL             = 0x40,  /* SOC PHY Control */
  39         MVS_PORTS_IMP           = 0x9C,  /* SOC Port Implemented */
  40
  41         MVS_GBL_PORT_TYPE       = 0xa0,  /* port type */
  42
  43         MVS_CTL                 = 0x100, /* SAS/SATA port configuration */
  44         MVS_PCS                 = 0x104, /* SAS/SATA port control/status */
  45         MVS_CMD_LIST_LO         = 0x108, /* cmd list addr */
  46         MVS_CMD_LIST_HI         = 0x10C,
  47         MVS_RX_FIS_LO           = 0x110, /* RX FIS list addr */
  48         MVS_RX_FIS_HI           = 0x114,
  49
  50         MVS_TX_CFG              = 0x120, /* TX configuration */
  51         MVS_TX_LO               = 0x124, /* TX (delivery) ring addr */
  52         MVS_TX_HI               = 0x128,
  53
  54         MVS_TX_PROD_IDX         = 0x12C, /* TX producer pointer */
  55         MVS_TX_CONS_IDX         = 0x130, /* TX consumer pointer (RO) */
  56         MVS_RX_CFG              = 0x134, /* RX configuration */
  57         MVS_RX_LO               = 0x138, /* RX (completion) ring addr */
  58         MVS_RX_HI               = 0x13C,
  59         MVS_RX_CONS_IDX         = 0x140, /* RX consumer pointer (RO) */
  60
  61         MVS_INT_COAL            = 0x148, /* Int coalescing config */
  62         MVS_INT_COAL_TMOUT      = 0x14C, /* Int coalescing timeout */
  63         MVS_INT_STAT            = 0x150, /* Central int status */
  64         MVS_INT_MASK            = 0x154, /* Central int enable */
  65         MVS_INT_STAT_SRS_0      = 0x158, /* SATA register set status */
  66         MVS_INT_MASK_SRS_0      = 0x15C,
  67
  68                                          /* ports 1-3 follow after this */
  69         MVS_P0_INT_STAT         = 0x160, /* port0 interrupt status */
  70         MVS_P0_INT_MASK         = 0x164, /* port0 interrupt mask */
  71                                          /* ports 5-7 follow after this */
  72         MVS_P4_INT_STAT         = 0x200, /* Port4 interrupt status */
  73         MVS_P4_INT_MASK         = 0x204, /* Port4 interrupt enable mask */
  74
  75                                          /* ports 1-3 follow after this */
  76         MVS_P0_SER_CTLSTAT      = 0x180, /* port0 serial control/status */
  77                                          /* ports 5-7 follow after this */
  78         MVS_P4_SER_CTLSTAT      = 0x220, /* port4 serial control/status */
  79
  80         MVS_CMD_ADDR            = 0x1B8, /* Command register port (addr) */
  81         MVS_CMD_DATA            = 0x1BC, /* Command register port (data) */
  82
  83                                          /* ports 1-3 follow after this */
  84         MVS_P0_CFG_ADDR         = 0x1C0, /* port0 phy register address */
  85         MVS_P0_CFG_DATA         = 0x1C4, /* port0 phy register data */
  86                                          /* ports 5-7 follow after this */
  87         MVS_P4_CFG_ADDR         = 0x230, /* Port4 config address */
  88         MVS_P4_CFG_DATA         = 0x234, /* Port4 config data */
  89
  90                                          /* ports 1-3 follow after this */
  91         MVS_P0_VSR_ADDR         = 0x1E0, /* port0 VSR address */
  92         MVS_P0_VSR_DATA         = 0x1E4, /* port0 VSR data */
  93                                          /* ports 5-7 follow after this */
  94         MVS_P4_VSR_ADDR         = 0x250, /* port4 VSR addr */
  95         MVS_P4_VSR_DATA         = 0x254, /* port4 VSR data */
  96 };
  97
  98 enum pci_cfg_registers {
  99         PCR_PHY_CTL             = 0x40,
 100         PCR_PHY_CTL2            = 0x90,
 101         PCR_DEV_CTRL            = 0xE8,
 102         PCR_LINK_STAT           = 0xF2,
 103 };
 104
 105 /*  SAS/SATA Vendor Specific Port Registers */
 106 enum sas_sata_vsp_regs {
 107         VSR_PHY_STAT            = 0x00, /* Phy Status */
 108         VSR_PHY_MODE1           = 0x01, /* phy tx */
 109         VSR_PHY_MODE2           = 0x02, /* tx scc */
 110         VSR_PHY_MODE3           = 0x03, /* pll */
 111         VSR_PHY_MODE4           = 0x04, /* VCO */
 112         VSR_PHY_MODE5           = 0x05, /* Rx */
 113         VSR_PHY_MODE6           = 0x06, /* CDR */
 114         VSR_PHY_MODE7           = 0x07, /* Impedance */
 115         VSR_PHY_MODE8           = 0x08, /* Voltage */
 116         VSR_PHY_MODE9           = 0x09, /* Test */
 117         VSR_PHY_MODE10          = 0x0A, /* Power */
 118         VSR_PHY_MODE11          = 0x0B, /* Phy Mode */
 119         VSR_PHY_VS0             = 0x0C, /* Vednor Specific 0 */
 120         VSR_PHY_VS1             = 0x0D, /* Vednor Specific 1 */
 121 };
 122
 123 enum chip_register_bits {
 124         PHY_MIN_SPP_PHYS_LINK_RATE_MASK = (0xF << 8),
 125         PHY_MAX_SPP_PHYS_LINK_RATE_MASK = (0xF << 12),
 126         PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET = (16),
 127         PHY_NEG_SPP_PHYS_LINK_RATE_MASK =
 128                         (0xF << PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET),
 129 };
 130
 131 #define MAX_SG_ENTRY            64
 132
 133 struct mvs_prd {
 134         __le64                  addr;           /* 64-bit buffer address */
 135         __le32                  reserved;
 136         __le32                  len;            /* 16-bit length */
 137 };
 138
 139 #define SPI_CTRL_REG                            0xc0
 140 #define SPI_CTRL_VENDOR_ENABLE          (1U<<29)
 141 #define SPI_CTRL_SPIRDY                         (1U<<22)
 142 #define SPI_CTRL_SPISTART                       (1U<<20)
 143
 144 #define SPI_CMD_REG             0xc4
 145 #define SPI_DATA_REG            0xc8
 146
 147 #define SPI_CTRL_REG_64XX               0x10
 148 #define SPI_CMD_REG_64XX                0x14
 149 #define SPI_DATA_REG_64XX               0x18
 150
 151 #endif