drivers/scsi/mvsas/mv_chips.h

   1 /*
   2  * Marvell 88SE64xx/88SE94xx register IO interface
   3  *
   4  * Copyright 2007 Red Hat, Inc.
   5  * Copyright 2008 Marvell. <kewei@marvell.com>
   6  *
   7  * This file is licensed under GPLv2.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; version 2 of the
  12  * License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
  22  * USA
  23 */
  24
  25
  26 #ifndef _MV_CHIPS_H_
  27 #define _MV_CHIPS_H_
  28
  29 #define mr32(reg)       readl(regs + reg)
  30 #define mw32(reg, val)  writel((val), regs + reg)
  31 #define mw32_f(reg, val)        do {                    \
  32                                 mw32(reg, val); \
  33                                 mr32(reg);      \
  34                         } while (0)
  35
  36 #define iow32(reg, val)         outl(val, (unsigned long)(regs + reg))
  37 #define ior32(reg)              inl((unsigned long)(regs + reg))
  38 #define iow16(reg, val)         outw((unsigned long)(val, regs + reg))
  39 #define ior16(reg)              inw((unsigned long)(regs + reg))
  40 #define iow8(reg, val)          outb((unsigned long)(val, regs + reg))
  41 #define ior8(reg)               inb((unsigned long)(regs + reg))
  42
  43 static inline u32 mvs_cr32(struct mvs_info *mvi, u32 addr)
  44 {
  45         void __iomem *regs = mvi->regs;
  46         mw32(MVS_CMD_ADDR, addr);
  47         return mr32(MVS_CMD_DATA);
  48 }
  49
  50 static inline void mvs_cw32(struct mvs_info *mvi, u32 addr, u32 val)
  51 {
  52         void __iomem *regs = mvi->regs;
  53         mw32(MVS_CMD_ADDR, addr);
  54         mw32(MVS_CMD_DATA, val);
  55 }
  56
  57 static inline u32 mvs_read_phy_ctl(struct mvs_info *mvi, u32 port)
  58 {
  59         void __iomem *regs = mvi->regs;
  60         return (port < 4) ? mr32(MVS_P0_SER_CTLSTAT + port * 4) :
  61                 mr32(MVS_P4_SER_CTLSTAT + (port - 4) * 4);
  62 }
  63
  64 static inline void mvs_write_phy_ctl(struct mvs_info *mvi, u32 port, u32 val)
  65 {
  66         void __iomem *regs = mvi->regs;
  67         if (port < 4)
  68                 mw32(MVS_P0_SER_CTLSTAT + port * 4, val);
  69         else
  70                 mw32(MVS_P4_SER_CTLSTAT + (port - 4) * 4, val);
  71 }
  72
  73 static inline u32 mvs_read_port(struct mvs_info *mvi, u32 off,
  74                                 u32 off2, u32 port)
  75 {
  76         void __iomem *regs = mvi->regs + off;
  77         void __iomem *regs2 = mvi->regs + off2;
  78         return (port < 4) ? readl(regs + port * 8) :
  79                 readl(regs2 + (port - 4) * 8);
  80 }
  81
  82 static inline void mvs_write_port(struct mvs_info *mvi, u32 off, u32 off2,
  83                                 u32 port, u32 val)
  84 {
  85         void __iomem *regs = mvi->regs + off;
  86         void __iomem *regs2 = mvi->regs + off2;
  87         if (port < 4)
  88                 writel(val, regs + port * 8);
  89         else
  90                 writel(val, regs2 + (port - 4) * 8);
  91 }
  92
  93 static inline u32 mvs_read_port_cfg_data(struct mvs_info *mvi, u32 port)
  94 {
  95         return mvs_read_port(mvi, MVS_P0_CFG_DATA,
  96                         MVS_P4_CFG_DATA, port);
  97 }
  98
  99 static inline void mvs_write_port_cfg_data(struct mvs_info *mvi,
 100                                                 u32 port, u32 val)
 101 {
 102         mvs_write_port(mvi, MVS_P0_CFG_DATA,
 103                         MVS_P4_CFG_DATA, port, val);
 104 }
 105
 106 static inline void mvs_write_port_cfg_addr(struct mvs_info *mvi,
 107                                                 u32 port, u32 addr)
 108 {
 109         mvs_write_port(mvi, MVS_P0_CFG_ADDR,
 110                         MVS_P4_CFG_ADDR, port, addr);
 111         mdelay(10);
 112 }
 113
 114 static inline u32 mvs_read_port_vsr_data(struct mvs_info *mvi, u32 port)
 115 {
 116         return mvs_read_port(mvi, MVS_P0_VSR_DATA,
 117                         MVS_P4_VSR_DATA, port);
 118 }
 119
 120 static inline void mvs_write_port_vsr_data(struct mvs_info *mvi,
 121                                                 u32 port, u32 val)
 122 {
 123         mvs_write_port(mvi, MVS_P0_VSR_DATA,
 124                         MVS_P4_VSR_DATA, port, val);
 125 }
 126
 127 static inline void mvs_write_port_vsr_addr(struct mvs_info *mvi,
 128                                                 u32 port, u32 addr)
 129 {
 130         mvs_write_port(mvi, MVS_P0_VSR_ADDR,
 131                         MVS_P4_VSR_ADDR, port, addr);
 132         mdelay(10);
 133 }
 134
 135 static inline u32 mvs_read_port_irq_stat(struct mvs_info *mvi, u32 port)
 136 {
 137         return mvs_read_port(mvi, MVS_P0_INT_STAT,
 138                         MVS_P4_INT_STAT, port);
 139 }
 140
 141 static inline void mvs_write_port_irq_stat(struct mvs_info *mvi,
 142                                                 u32 port, u32 val)
 143 {
 144         mvs_write_port(mvi, MVS_P0_INT_STAT,
 145                         MVS_P4_INT_STAT, port, val);
 146 }
 147
 148 static inline u32 mvs_read_port_irq_mask(struct mvs_info *mvi, u32 port)
 149 {
 150         return mvs_read_port(mvi, MVS_P0_INT_MASK,
 151                         MVS_P4_INT_MASK, port);
 152
 153 }
 154
 155 static inline void mvs_write_port_irq_mask(struct mvs_info *mvi,
 156                                                 u32 port, u32 val)
 157 {
 158         mvs_write_port(mvi, MVS_P0_INT_MASK,
 159                         MVS_P4_INT_MASK, port, val);
 160 }
 161
 162 static inline void __devinit mvs_phy_hacks(struct mvs_info *mvi)
 163 {
 164         u32 tmp;
 165
 166         /* workaround for SATA R-ERR, to ignore phy glitch */
 167         tmp = mvs_cr32(mvi, CMD_PHY_TIMER);
 168         tmp &= ~(1 << 9);
 169         tmp |= (1 << 10);
 170         mvs_cw32(mvi, CMD_PHY_TIMER, tmp);
 171
 172         /* enable retry 127 times */
 173         mvs_cw32(mvi, CMD_SAS_CTL1, 0x7f7f);
 174
 175         /* extend open frame timeout to max */
 176         tmp = mvs_cr32(mvi, CMD_SAS_CTL0);
 177         tmp &= ~0xffff;
 178         tmp |= 0x3fff;
 179         mvs_cw32(mvi, CMD_SAS_CTL0, tmp);
 180
 181         /* workaround for WDTIMEOUT , set to 550 ms */
 182         mvs_cw32(mvi, CMD_WD_TIMER, 0x7a0000);
 183
 184         /* not to halt for different port op during wideport link change */
 185         mvs_cw32(mvi, CMD_APP_ERR_CONFIG, 0xffefbf7d);
 186
 187         /* workaround for Seagate disk not-found OOB sequence, recv
 188          * COMINIT before sending out COMWAKE */
 189         tmp = mvs_cr32(mvi, CMD_PHY_MODE_21);
 190         tmp &= 0x0000ffff;
 191         tmp |= 0x00fa0000;
 192         mvs_cw32(mvi, CMD_PHY_MODE_21, tmp);
 193
 194         tmp = mvs_cr32(mvi, CMD_PHY_TIMER);
 195         tmp &= 0x1fffffff;
 196         tmp |= (2U << 29);      /* 8 ms retry */
 197         mvs_cw32(mvi, CMD_PHY_TIMER, tmp);
 198 }
 199
 200 static inline void mvs_int_sata(struct mvs_info *mvi)
 201 {
 202         u32 tmp;
 203         void __iomem *regs = mvi->regs;
 204         tmp = mr32(MVS_INT_STAT_SRS_0);
 205         if (tmp)
 206                 mw32(MVS_INT_STAT_SRS_0, tmp);
 207         MVS_CHIP_DISP->clear_active_cmds(mvi);
 208 }
 209
 210 static inline void mvs_int_full(struct mvs_info *mvi)
 211 {
 212         void __iomem *regs = mvi->regs;
 213         u32 tmp, stat;
 214         int i;
 215
 216         stat = mr32(MVS_INT_STAT);
 217         mvs_int_rx(mvi, false);
 218
 219         for (i = 0; i < mvi->chip->n_phy; i++) {
 220                 tmp = (stat >> i) & (CINT_PORT | CINT_PORT_STOPPED);
 221                 if (tmp)
 222                         mvs_int_port(mvi, i, tmp);
 223         }
 224
 225         if (stat & CINT_SRS)
 226                 mvs_int_sata(mvi);
 227
 228         mw32(MVS_INT_STAT, stat);
 229 }
 230
 231 static inline void mvs_start_delivery(struct mvs_info *mvi, u32 tx)
 232 {
 233         void __iomem *regs = mvi->regs;
 234         mw32(MVS_TX_PROD_IDX, tx);
 235 }
 236
 237 static inline u32 mvs_rx_update(struct mvs_info *mvi)
 238 {
 239         void __iomem *regs = mvi->regs;
 240         return mr32(MVS_RX_CONS_IDX);
 241 }
 242
 243 static inline u32 mvs_get_prd_size(void)
 244 {
 245         return sizeof(struct mvs_prd);
 246 }
 247
 248 static inline u32 mvs_get_prd_count(void)
 249 {
 250         return MAX_SG_ENTRY;
 251 }
 252
 253 static inline void mvs_show_pcie_usage(struct mvs_info *mvi)
 254 {
 255         u16 link_stat, link_spd;
 256         const char *spd[] = {
 257                 "UnKnown",
 258                 "2.5",
 259                 "5.0",
 260         };
 261         if (mvi->flags & MVF_FLAG_SOC || mvi->id > 0)
 262                 return;
 263
 264         pci_read_config_word(mvi->pdev, PCR_LINK_STAT, &link_stat);
 265         link_spd = (link_stat & PLS_LINK_SPD) >> PLS_LINK_SPD_OFFS;
 266         if (link_spd >= 3)
 267                 link_spd = 0;
 268         dev_printk(KERN_INFO, mvi->dev,
 269                 "mvsas: PCI-E x%u, Bandwidth Usage: %s Gbps\n",
 270                (link_stat & PLS_NEG_LINK_WD) >> PLS_NEG_LINK_WD_OFFS,
 271                spd[link_spd]);
 272 }
 273
 274 static inline u32 mvs_hw_max_link_rate(void)
 275 {
 276         return MAX_LINK_RATE;
 277 }
 278
 279 #endif  /* _MV_CHIPS_H_ */
 280