drivers/serial/sh-sci.h

   1 #include <linux/serial_core.h>
   2 #include <asm/io.h>
   3 #include <linux/gpio.h>
   4
   5 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
   6 #include <asm/regs306x.h>
   7 #endif
   8 #if defined(CONFIG_H8S2678)
   9 #include <asm/regs267x.h>
  10 #endif
  11
  12 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
  13     defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  14     defined(CONFIG_CPU_SUBTYPE_SH7708) || \
  15     defined(CONFIG_CPU_SUBTYPE_SH7709)
  16 # define SCPCR  0xA4000116 /* 16 bit SCI and SCIF */
  17 # define SCPDR  0xA4000136 /* 8  bit SCI and SCIF */
  18 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
  19 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
  20 # define SCIF0          0xA4400000
  21 # define SCIF2          0xA4410000
  22 # define SCSMR_Ir       0xA44A0000
  23 # define IRDA_SCIF      SCIF0
  24 # define SCPCR 0xA4000116
  25 # define SCPDR 0xA4000136
  26
  27 /* Set the clock source,
  28  * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
  29  * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
  30  */
  31 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
  32 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
  33       defined(CONFIG_CPU_SUBTYPE_SH7721)
  34 # define SCSCR_INIT(port)  0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
  35 # define PORT_PTCR         0xA405011EUL
  36 # define PORT_PVCR         0xA4050122UL
  37 # define SCIF_ORER         0x0200   /* overrun error bit */
  38 #elif defined(CONFIG_SH_RTS7751R2D)
  39 # define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
  40 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
  41 # define SCIF_ORER 0x0001   /* overrun error bit */
  42 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  43 #elif defined(CONFIG_CPU_SUBTYPE_SH7750)  || \
  44       defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
  45       defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
  46       defined(CONFIG_CPU_SUBTYPE_SH7091)  || \
  47       defined(CONFIG_CPU_SUBTYPE_SH7751)  || \
  48       defined(CONFIG_CPU_SUBTYPE_SH7751R)
  49 # define SCSPTR1 0xffe0001c /* 8  bit SCI */
  50 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
  51 # define SCIF_ORER 0x0001   /* overrun error bit */
  52 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
  53         0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
  54         0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
  55 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
  56 # define SCSPTR0 0xfe600024 /* 16 bit SCIF */
  57 # define SCSPTR1 0xfe610024 /* 16 bit SCIF */
  58 # define SCSPTR2 0xfe620024 /* 16 bit SCIF */
  59 # define SCIF_ORER 0x0001  /* overrun error bit */
  60 # define SCSCR_INIT(port)          0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  61 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
  62 # define SCSPTR0 0xA4400000       /* 16 bit SCIF */
  63 # define SCIF_ORER 0x0001   /* overrun error bit */
  64 # define PACR 0xa4050100
  65 # define PBCR 0xa4050102
  66 # define SCSCR_INIT(port)          0x3B
  67 #elif defined(CONFIG_CPU_SUBTYPE_SH7343)
  68 # define SCSPTR0 0xffe00010     /* 16 bit SCIF */
  69 # define SCSPTR1 0xffe10010     /* 16 bit SCIF */
  70 # define SCSPTR2 0xffe20010     /* 16 bit SCIF */
  71 # define SCSPTR3 0xffe30010     /* 16 bit SCIF */
  72 # define SCSCR_INIT(port) 0x32  /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
  73 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
  74 # define PADR                   0xA4050120
  75 # define PSDR                   0xA405013e
  76 # define PWDR                   0xA4050166
  77 # define PSCR                   0xA405011E
  78 # define SCIF_ORER              0x0001  /* overrun error bit */
  79 # define SCSCR_INIT(port)       0x0038  /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  80 #elif defined(CONFIG_CPU_SUBTYPE_SH7366)
  81 # define SCPDR0                 0xA405013E      /* 16 bit SCIF0 PSDR */
  82 # define SCSPTR0                SCPDR0
  83 # define SCIF_ORER              0x0001  /* overrun error bit */
  84 # define SCSCR_INIT(port)       0x0038  /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  85 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
  86 # define SCSPTR0                0xa4050160
  87 # define SCSPTR1                0xa405013e
  88 # define SCSPTR2                0xa4050160
  89 # define SCSPTR3                0xa405013e
  90 # define SCSPTR4                0xa4050128
  91 # define SCSPTR5                0xa4050128
  92 # define SCIF_ORER              0x0001  /* overrun error bit */
  93 # define SCSCR_INIT(port)       0x0038  /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  94 #elif defined(CONFIG_CPU_SUBTYPE_SH7724)
  95 # define SCIF_ORER              0x0001  /* overrun error bit */
  96 # define SCSCR_INIT(port)       0x0038  /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  97 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
  98 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
  99 # define SCIF_ORER 0x0001   /* overrun error bit */
 100 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 101 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
 102 # define SCIF_BASE_ADDR    0x01030000
 103 # define SCIF_ADDR_SH5     PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
 104 # define SCIF_PTR2_OFFS    0x0000020
 105 # define SCIF_LSR2_OFFS    0x0000024
 106 # define SCSPTR2           ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
 107 # define SCLSR2            ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
 108 # define SCSCR_INIT(port)  0x38         /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
 109 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
 110 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
 111 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
 112 #elif defined(CONFIG_H8S2678)
 113 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
 114 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
 115 #elif defined(CONFIG_CPU_SUBTYPE_SH7757)
 116 # define SCSPTR0 0xfe4b0020
 117 # define SCSPTR1 0xfe4b0020
 118 # define SCSPTR2 0xfe4b0020
 119 # define SCIF_ORER 0x0001
 120 # define SCSCR_INIT(port)       0x38
 121 # define SCIF_ONLY
 122 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
 123 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */
 124 # define SCSPTR1 0xffe08024 /* 16 bit SCIF */
 125 # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
 126 # define SCIF_ORER 0x0001  /* overrun error bit */
 127 # define SCSCR_INIT(port)       0x38    /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 128 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
 129 # define SCSPTR0 0xff923020 /* 16 bit SCIF */
 130 # define SCSPTR1 0xff924020 /* 16 bit SCIF */
 131 # define SCSPTR2 0xff925020 /* 16 bit SCIF */
 132 # define SCIF_ORER 0x0001  /* overrun error bit */
 133 # define SCSCR_INIT(port)       0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
 134 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
 135 # define SCSPTR0        0xffe00024      /* 16 bit SCIF */
 136 # define SCSPTR1        0xffe10024      /* 16 bit SCIF */
 137 # define SCIF_ORER      0x0001          /* Overrun error bit */
 138 # define SCSCR_INIT(port)       0x3a    /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 139 #elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \
 140       defined(CONFIG_CPU_SUBTYPE_SH7786)
 141 # define SCSPTR0        0xffea0024      /* 16 bit SCIF */
 142 # define SCSPTR1        0xffeb0024      /* 16 bit SCIF */
 143 # define SCSPTR2        0xffec0024      /* 16 bit SCIF */
 144 # define SCSPTR3        0xffed0024      /* 16 bit SCIF */
 145 # define SCSPTR4        0xffee0024      /* 16 bit SCIF */
 146 # define SCSPTR5        0xffef0024      /* 16 bit SCIF */
 147 # define SCIF_ORER      0x0001          /* Overrun error bit */
 148 # define SCSCR_INIT(port)       0x3a    /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 149 #elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \
 150       defined(CONFIG_CPU_SUBTYPE_SH7203) || \
 151       defined(CONFIG_CPU_SUBTYPE_SH7206) || \
 152       defined(CONFIG_CPU_SUBTYPE_SH7263)
 153 # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
 154 # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
 155 # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
 156 # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
 157 # if defined(CONFIG_CPU_SUBTYPE_SH7201)
 158 #  define SCSPTR4 0xfffeA020 /* 16 bit SCIF */
 159 #  define SCSPTR5 0xfffeA820 /* 16 bit SCIF */
 160 #  define SCSPTR6 0xfffeB020 /* 16 bit SCIF */
 161 #  define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
 162 # endif
 163 # define SCSCR_INIT(port)       0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 164 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
 165 # define SCSPTR0 0xf8400020 /* 16 bit SCIF */
 166 # define SCSPTR1 0xf8410020 /* 16 bit SCIF */
 167 # define SCSPTR2 0xf8420020 /* 16 bit SCIF */
 168 # define SCIF_ORER 0x0001  /* overrun error bit */
 169 # define SCSCR_INIT(port)       0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 170 #elif defined(CONFIG_CPU_SUBTYPE_SHX3)
 171 # define SCSPTR0 0xffc30020             /* 16 bit SCIF */
 172 # define SCSPTR1 0xffc40020             /* 16 bit SCIF */
 173 # define SCSPTR2 0xffc50020             /* 16 bit SCIF */
 174 # define SCSPTR3 0xffc60020             /* 16 bit SCIF */
 175 # define SCIF_ORER 0x0001               /* Overrun error bit */
 176 # define SCSCR_INIT(port)       0x38    /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 177 #else
 178 # error CPU subtype not defined
 179 #endif
 180
 181 /* SCSCR */
 182 #define SCI_CTRL_FLAGS_TIE  0x80 /* all */
 183 #define SCI_CTRL_FLAGS_RIE  0x40 /* all */
 184 #define SCI_CTRL_FLAGS_TE   0x20 /* all */
 185 #define SCI_CTRL_FLAGS_RE   0x10 /* all */
 186 #if defined(CONFIG_CPU_SUBTYPE_SH7750)  || \
 187     defined(CONFIG_CPU_SUBTYPE_SH7091)  || \
 188     defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 189     defined(CONFIG_CPU_SUBTYPE_SH7722)  || \
 190     defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
 191     defined(CONFIG_CPU_SUBTYPE_SH7751)  || \
 192     defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
 193     defined(CONFIG_CPU_SUBTYPE_SH7763)  || \
 194     defined(CONFIG_CPU_SUBTYPE_SH7780)  || \
 195     defined(CONFIG_CPU_SUBTYPE_SH7785)  || \
 196     defined(CONFIG_CPU_SUBTYPE_SH7786)  || \
 197     defined(CONFIG_CPU_SUBTYPE_SHX3)
 198 #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
 199 #else
 200 #define SCI_CTRL_FLAGS_REIE 0
 201 #endif
 202 /*      SCI_CTRL_FLAGS_MPIE 0x08  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 203 /*      SCI_CTRL_FLAGS_TEIE 0x04  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 204 /*      SCI_CTRL_FLAGS_CKE1 0x02  * all */
 205 /*      SCI_CTRL_FLAGS_CKE0 0x01  * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
 206
 207 /* SCxSR SCI */
 208 #define SCI_TDRE  0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 209 #define SCI_RDRF  0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 210 #define SCI_ORER  0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 211 #define SCI_FER   0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 212 #define SCI_PER   0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 213 #define SCI_TEND  0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 214 /*      SCI_MPB   0x02  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 215 /*      SCI_MPBT  0x01  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 216
 217 #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
 218
 219 /* SCxSR SCIF */
 220 #define SCIF_ER    0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 221 #define SCIF_TEND  0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 222 #define SCIF_TDFE  0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 223 #define SCIF_BRK   0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 224 #define SCIF_FER   0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 225 #define SCIF_PER   0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 226 #define SCIF_RDF   0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 227 #define SCIF_DR    0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 228
 229 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 230     defined(CONFIG_CPU_SUBTYPE_SH7720) || \
 231     defined(CONFIG_CPU_SUBTYPE_SH7721)
 232 # define SCIF_ORER    0x0200
 233 # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
 234 # define SCIF_RFDC_MASK 0x007f
 235 # define SCIF_TXROOM_MAX 64
 236 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
 237 # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK )
 238 # define SCIF_RFDC_MASK 0x007f
 239 # define SCIF_TXROOM_MAX 64
 240 /* SH7763 SCIF2 support */
 241 # define SCIF2_RFDC_MASK 0x001f
 242 # define SCIF2_TXROOM_MAX 16
 243 #else
 244 # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
 245 # define SCIF_RFDC_MASK 0x001f
 246 # define SCIF_TXROOM_MAX 16
 247 #endif
 248
 249 #ifndef SCIF_ORER
 250 #define SCIF_ORER       0x0000
 251 #endif
 252
 253 #define SCxSR_TEND(port)        (((port)->type == PORT_SCI) ? SCI_TEND   : SCIF_TEND)
 254 #define SCxSR_ERRORS(port)      (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
 255 #define SCxSR_RDxF(port)        (((port)->type == PORT_SCI) ? SCI_RDRF   : SCIF_RDF)
 256 #define SCxSR_TDxE(port)        (((port)->type == PORT_SCI) ? SCI_TDRE   : SCIF_TDFE)
 257 #define SCxSR_FER(port)         (((port)->type == PORT_SCI) ? SCI_FER    : SCIF_FER)
 258 #define SCxSR_PER(port)         (((port)->type == PORT_SCI) ? SCI_PER    : SCIF_PER)
 259 #define SCxSR_BRK(port)         (((port)->type == PORT_SCI) ? 0x00       : SCIF_BRK)
 260 #define SCxSR_ORER(port)        (((port)->type == PORT_SCI) ? SCI_ORER   : SCIF_ORER)
 261
 262 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 263     defined(CONFIG_CPU_SUBTYPE_SH7720) || \
 264     defined(CONFIG_CPU_SUBTYPE_SH7721)
 265 # define SCxSR_RDxF_CLEAR(port)  (sci_in(port, SCxSR) & 0xfffc)
 266 # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
 267 # define SCxSR_TDxE_CLEAR(port)  (sci_in(port, SCxSR) & 0xffdf)
 268 # define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3)
 269 #else
 270 # define SCxSR_RDxF_CLEAR(port)  (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
 271 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
 272 # define SCxSR_TDxE_CLEAR(port)  (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
 273 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
 274 #endif
 275
 276 /* SCFCR */
 277 #define SCFCR_RFRST 0x0002
 278 #define SCFCR_TFRST 0x0004
 279 #define SCFCR_TCRST 0x4000
 280 #define SCFCR_MCE   0x0008
 281
 282 #define SCI_MAJOR               204
 283 #define SCI_MINOR_START         8
 284
 285 /* Generic serial flags */
 286 #define SCI_RX_THROTTLE         0x0000001
 287
 288 #define SCI_MAGIC 0xbabeface
 289
 290 /*
 291  * Events are used to schedule things to happen at timer-interrupt
 292  * time, instead of at rs interrupt time.
 293  */
 294 #define SCI_EVENT_WRITE_WAKEUP  0
 295
 296 #define SCI_IN(size, offset)                                    \
 297   if ((size) == 8) {                                            \
 298     return ioread8(port->membase + (offset));                   \
 299   } else {                                                      \
 300     return ioread16(port->membase + (offset));                  \
 301   }
 302 #define SCI_OUT(size, offset, value)                            \
 303   if ((size) == 8) {                                            \
 304     iowrite8(value, port->membase + (offset));                  \
 305   } else if ((size) == 16) {                                    \
 306     iowrite16(value, port->membase + (offset));                 \
 307   }
 308
 309 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
 310   static inline unsigned int sci_##name##_in(struct uart_port *port)    \
 311   {                                                                     \
 312     if (port->type == PORT_SCIF) {                                      \
 313       SCI_IN(scif_size, scif_offset)                                    \
 314     } else {    /* PORT_SCI or PORT_SCIFA */                            \
 315       SCI_IN(sci_size, sci_offset);                                     \
 316     }                                                                   \
 317   }                                                                     \
 318   static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
 319   {                                                                     \
 320     if (port->type == PORT_SCIF) {                                      \
 321       SCI_OUT(scif_size, scif_offset, value)                            \
 322     } else {    /* PORT_SCI or PORT_SCIFA */                            \
 323       SCI_OUT(sci_size, sci_offset, value);                             \
 324     }                                                                   \
 325   }
 326
 327 #ifdef CONFIG_H8300
 328 /* h8300 don't have SCIF */
 329 #define CPU_SCIF_FNS(name)                                              \
 330   static inline unsigned int sci_##name##_in(struct uart_port *port)    \
 331   {                                                                     \
 332     return 0;                                                           \
 333   }                                                                     \
 334   static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
 335   {                                                                     \
 336   }
 337 #else
 338 #define CPU_SCIF_FNS(name, scif_offset, scif_size)                      \
 339   static inline unsigned int sci_##name##_in(struct uart_port *port)    \
 340   {                                                                     \
 341     SCI_IN(scif_size, scif_offset);                                     \
 342   }                                                                     \
 343   static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
 344   {                                                                     \
 345     SCI_OUT(scif_size, scif_offset, value);                             \
 346   }
 347 #endif
 348
 349 #define CPU_SCI_FNS(name, sci_offset, sci_size)                         \
 350   static inline unsigned int sci_##name##_in(struct uart_port* port)    \
 351   {                                                                     \
 352     SCI_IN(sci_size, sci_offset);                                       \
 353   }                                                                     \
 354   static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
 355   {                                                                     \
 356     SCI_OUT(sci_size, sci_offset, value);                               \
 357   }
 358
 359 #ifdef CONFIG_CPU_SH3
 360 #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
 361 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 362                                 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
 363                                  h8_sci_offset, h8_sci_size) \
 364   CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
 365 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
 366           CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
 367 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 368       defined(CONFIG_CPU_SUBTYPE_SH7720) || \
 369       defined(CONFIG_CPU_SUBTYPE_SH7721)
 370 #define SCIF_FNS(name, scif_offset, scif_size) \
 371   CPU_SCIF_FNS(name, scif_offset, scif_size)
 372 #else
 373 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 374                  sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
 375                  h8_sci_offset, h8_sci_size) \
 376   CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
 377 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
 378   CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
 379 #endif
 380 #elif defined(__H8300H__) || defined(__H8300S__)
 381 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 382                  sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
 383                  h8_sci_offset, h8_sci_size) \
 384   CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
 385 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
 386   CPU_SCIF_FNS(name)
 387 #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
 388       defined(CONFIG_CPU_SUBTYPE_SH7724)
 389         #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \
 390                 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size)
 391         #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
 392                 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
 393 #else
 394 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 395                  sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
 396                  h8_sci_offset, h8_sci_size) \
 397   CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
 398 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
 399   CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
 400 #endif
 401
 402 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 403     defined(CONFIG_CPU_SUBTYPE_SH7720) || \
 404     defined(CONFIG_CPU_SUBTYPE_SH7721)
 405
 406 SCIF_FNS(SCSMR,  0x00, 16)
 407 SCIF_FNS(SCBRR,  0x04,  8)
 408 SCIF_FNS(SCSCR,  0x08, 16)
 409 SCIF_FNS(SCTDSR, 0x0c,  8)
 410 SCIF_FNS(SCFER,  0x10, 16)
 411 SCIF_FNS(SCxSR,  0x14, 16)
 412 SCIF_FNS(SCFCR,  0x18, 16)
 413 SCIF_FNS(SCFDR,  0x1c, 16)
 414 SCIF_FNS(SCxTDR, 0x20,  8)
 415 SCIF_FNS(SCxRDR, 0x24,  8)
 416 SCIF_FNS(SCLSR,  0x24, 16)
 417 #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
 418       defined(CONFIG_CPU_SUBTYPE_SH7724)
 419 SCIx_FNS(SCSMR,  0x00, 16, 0x00, 16)
 420 SCIx_FNS(SCBRR,  0x04,  8, 0x04,  8)
 421 SCIx_FNS(SCSCR,  0x08, 16, 0x08, 16)
 422 SCIx_FNS(SCxTDR, 0x20,  8, 0x0c,  8)
 423 SCIx_FNS(SCxSR,  0x14, 16, 0x10, 16)
 424 SCIx_FNS(SCxRDR, 0x24,  8, 0x14,  8)
 425 SCIx_FNS(SCSPTR, 0,     0,    0,  0)
 426 SCIF_FNS(SCTDSR, 0x0c,  8)
 427 SCIF_FNS(SCFER,  0x10, 16)
 428 SCIF_FNS(SCFCR,  0x18, 16)
 429 SCIF_FNS(SCFDR,  0x1c, 16)
 430 SCIF_FNS(SCLSR,  0x24, 16)
 431 #else
 432 /*      reg      SCI/SH3   SCI/SH4  SCIF/SH3   SCIF/SH4  SCI/H8*/
 433 /*      name     off  sz   off  sz   off  sz   off  sz   off  sz*/
 434 SCIx_FNS(SCSMR,  0x00,  8, 0x00,  8, 0x00,  8, 0x00, 16, 0x00,  8)
 435 SCIx_FNS(SCBRR,  0x02,  8, 0x04,  8, 0x02,  8, 0x04,  8, 0x01,  8)
 436 SCIx_FNS(SCSCR,  0x04,  8, 0x08,  8, 0x04,  8, 0x08, 16, 0x02,  8)
 437 SCIx_FNS(SCxTDR, 0x06,  8, 0x0c,  8, 0x06,  8, 0x0C,  8, 0x03,  8)
 438 SCIx_FNS(SCxSR,  0x08,  8, 0x10,  8, 0x08, 16, 0x10, 16, 0x04,  8)
 439 SCIx_FNS(SCxRDR, 0x0a,  8, 0x14,  8, 0x0A,  8, 0x14,  8, 0x05,  8)
 440 SCIF_FNS(SCFCR,                      0x0c,  8, 0x18, 16)
 441 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
 442     defined(CONFIG_CPU_SUBTYPE_SH7780) || \
 443     defined(CONFIG_CPU_SUBTYPE_SH7785) || \
 444     defined(CONFIG_CPU_SUBTYPE_SH7786)
 445 SCIF_FNS(SCFDR,                      0x0e, 16, 0x1C, 16)
 446 SCIF_FNS(SCTFDR,                     0x0e, 16, 0x1C, 16)
 447 SCIF_FNS(SCRFDR,                     0x0e, 16, 0x20, 16)
 448 SCIF_FNS(SCSPTR,                        0,  0, 0x24, 16)
 449 SCIF_FNS(SCLSR,                         0,  0, 0x28, 16)
 450 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
 451 SCIF_FNS(SCFDR,                         0,  0, 0x1C, 16)
 452 SCIF_FNS(SCSPTR2,                       0,  0, 0x20, 16)
 453 SCIF_FNS(SCLSR2,                        0,  0, 0x24, 16)
 454 SCIF_FNS(SCTFDR,                     0x0e, 16, 0x1C, 16)
 455 SCIF_FNS(SCRFDR,                     0x0e, 16, 0x20, 16)
 456 SCIF_FNS(SCSPTR,                        0,  0, 0x24, 16)
 457 SCIF_FNS(SCLSR,                         0,  0, 0x28, 16)
 458 #else
 459 SCIF_FNS(SCFDR,                      0x0e, 16, 0x1C, 16)
 460 #if defined(CONFIG_CPU_SUBTYPE_SH7722)
 461 SCIF_FNS(SCSPTR,                        0,  0, 0, 0)
 462 #else
 463 SCIF_FNS(SCSPTR,                        0,  0, 0x20, 16)
 464 #endif
 465 SCIF_FNS(SCLSR,                         0,  0, 0x24, 16)
 466 #endif
 467 #endif
 468 #define sci_in(port, reg) sci_##reg##_in(port)
 469 #define sci_out(port, reg, value) sci_##reg##_out(port, value)
 470
 471 /* H8/300 series SCI pins assignment */
 472 #if defined(__H8300H__) || defined(__H8300S__)
 473 static const struct __attribute__((packed)) {
 474         int port;             /* GPIO port no */
 475         unsigned short rx,tx; /* GPIO bit no */
 476 } h8300_sci_pins[] = {
 477 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
 478         {    /* SCI0 */
 479                 .port = H8300_GPIO_P9,
 480                 .rx   = H8300_GPIO_B2,
 481                 .tx   = H8300_GPIO_B0,
 482         },
 483         {    /* SCI1 */
 484                 .port = H8300_GPIO_P9,
 485                 .rx   = H8300_GPIO_B3,
 486                 .tx   = H8300_GPIO_B1,
 487         },
 488         {    /* SCI2 */
 489                 .port = H8300_GPIO_PB,
 490                 .rx   = H8300_GPIO_B7,
 491                 .tx   = H8300_GPIO_B6,
 492         }
 493 #elif defined(CONFIG_H8S2678)
 494         {    /* SCI0 */
 495                 .port = H8300_GPIO_P3,
 496                 .rx   = H8300_GPIO_B2,
 497                 .tx   = H8300_GPIO_B0,
 498         },
 499         {    /* SCI1 */
 500                 .port = H8300_GPIO_P3,
 501                 .rx   = H8300_GPIO_B3,
 502                 .tx   = H8300_GPIO_B1,
 503         },
 504         {    /* SCI2 */
 505                 .port = H8300_GPIO_P5,
 506                 .rx   = H8300_GPIO_B1,
 507                 .tx   = H8300_GPIO_B0,
 508         }
 509 #endif
 510 };
 511 #endif
 512
 513 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
 514     defined(CONFIG_CPU_SUBTYPE_SH7707) || \
 515     defined(CONFIG_CPU_SUBTYPE_SH7708) || \
 516     defined(CONFIG_CPU_SUBTYPE_SH7709)
 517 static inline int sci_rxd_in(struct uart_port *port)
 518 {
 519         if (port->mapbase == 0xfffffe80)
 520                 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */
 521         if (port->mapbase == 0xa4000150)
 522                 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
 523         if (port->mapbase == 0xa4000140)
 524                 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
 525         return 1;
 526 }
 527 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
 528 static inline int sci_rxd_in(struct uart_port *port)
 529 {
 530         if (port->mapbase == SCIF0)
 531                 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
 532         if (port->mapbase == SCIF2)
 533                 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
 534         return 1;
 535 }
 536 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
 537 static inline int sci_rxd_in(struct uart_port *port)
 538 {
 539           return sci_in(port,SCxSR)&0x0010 ? 1 : 0;
 540 }
 541 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
 542       defined(CONFIG_CPU_SUBTYPE_SH7721)
 543 static inline int sci_rxd_in(struct uart_port *port)
 544 {
 545         if (port->mapbase == 0xa4430000)
 546                 return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
 547         else if (port->mapbase == 0xa4438000)
 548                 return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
 549         return 1;
 550 }
 551 #elif defined(CONFIG_CPU_SUBTYPE_SH7750)  || \
 552       defined(CONFIG_CPU_SUBTYPE_SH7751)  || \
 553       defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
 554       defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 555       defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
 556       defined(CONFIG_CPU_SUBTYPE_SH7091)
 557 static inline int sci_rxd_in(struct uart_port *port)
 558 {
 559         if (port->mapbase == 0xffe00000)
 560                 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
 561         if (port->mapbase == 0xffe80000)
 562                 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
 563         return 1;
 564 }
 565 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
 566 static inline int sci_rxd_in(struct uart_port *port)
 567 {
 568         if (port->mapbase == 0xffe80000)
 569                 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
 570         return 1;
 571 }
 572 #elif defined(CONFIG_CPU_SUBTYPE_SH7757)
 573 static inline int sci_rxd_in(struct uart_port *port)
 574 {
 575         if (port->mapbase == 0xfe4b0000)
 576                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0;
 577         if (port->mapbase == 0xfe4c0000)
 578                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0;
 579         if (port->mapbase == 0xfe4d0000)
 580                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0;
 581 }
 582 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
 583 static inline int sci_rxd_in(struct uart_port *port)
 584 {
 585         if (port->mapbase == 0xfe600000)
 586                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 587         if (port->mapbase == 0xfe610000)
 588                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 589         if (port->mapbase == 0xfe620000)
 590                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 591         return 1;
 592 }
 593 #elif defined(CONFIG_CPU_SUBTYPE_SH7343)
 594 static inline int sci_rxd_in(struct uart_port *port)
 595 {
 596         if (port->mapbase == 0xffe00000)
 597                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 598         if (port->mapbase == 0xffe10000)
 599                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 600         if (port->mapbase == 0xffe20000)
 601                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 602         if (port->mapbase == 0xffe30000)
 603                 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
 604         return 1;
 605 }
 606 #elif defined(CONFIG_CPU_SUBTYPE_SH7366)
 607 static inline int sci_rxd_in(struct uart_port *port)
 608 {
 609         if (port->mapbase == 0xffe00000)
 610                 return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
 611         return 1;
 612 }
 613 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
 614 static inline int sci_rxd_in(struct uart_port *port)
 615 {
 616         if (port->mapbase == 0xffe00000)
 617                 return ctrl_inb(PSDR) & 0x02 ? 1 : 0; /* SCIF0 */
 618         if (port->mapbase == 0xffe10000)
 619                 return ctrl_inb(PADR) & 0x40 ? 1 : 0; /* SCIF1 */
 620         if (port->mapbase == 0xffe20000)
 621                 return ctrl_inb(PWDR) & 0x04 ? 1 : 0; /* SCIF2 */
 622
 623         return 1;
 624 }
 625 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
 626 static inline int sci_rxd_in(struct uart_port *port)
 627 {
 628         if (port->mapbase == 0xffe00000)
 629                 return ctrl_inb(SCSPTR0) & 0x0008 ? 1 : 0; /* SCIF0 */
 630         if (port->mapbase == 0xffe10000)
 631                 return ctrl_inb(SCSPTR1) & 0x0020 ? 1 : 0; /* SCIF1 */
 632         if (port->mapbase == 0xffe20000)
 633                 return ctrl_inb(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF2 */
 634         if (port->mapbase == 0xa4e30000)
 635                 return ctrl_inb(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF3 */
 636         if (port->mapbase == 0xa4e40000)
 637                 return ctrl_inb(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF4 */
 638         if (port->mapbase == 0xa4e50000)
 639                 return ctrl_inb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */
 640         return 1;
 641 }
 642 #elif defined(CONFIG_CPU_SUBTYPE_SH7724)
 643 #  define SCFSR    0x0010
 644 #  define SCASSR   0x0014
 645 static inline int sci_rxd_in(struct uart_port *port)
 646 {
 647         if (port->type == PORT_SCIF)
 648                 return ctrl_inw((port->mapbase + SCFSR))  & SCIF_BRK ? 1 : 0;
 649         if (port->type == PORT_SCIFA)
 650                 return ctrl_inw((port->mapbase + SCASSR)) & SCIF_BRK ? 1 : 0;
 651         return 1;
 652 }
 653 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
 654 static inline int sci_rxd_in(struct uart_port *port)
 655 {
 656          return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */
 657 }
 658 #elif defined(__H8300H__) || defined(__H8300S__)
 659 static inline int sci_rxd_in(struct uart_port *port)
 660 {
 661         int ch = (port->mapbase - SMR0) >> 3;
 662         return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
 663 }
 664 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
 665 static inline int sci_rxd_in(struct uart_port *port)
 666 {
 667         if (port->mapbase == 0xffe00000)
 668                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 669         if (port->mapbase == 0xffe08000)
 670                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 671         if (port->mapbase == 0xffe10000)
 672                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF/IRDA */
 673
 674         return 1;
 675 }
 676 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
 677 static inline int sci_rxd_in(struct uart_port *port)
 678 {
 679         if (port->mapbase == 0xff923000)
 680                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 681         if (port->mapbase == 0xff924000)
 682                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 683         if (port->mapbase == 0xff925000)
 684                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 685         return 1;
 686 }
 687 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
 688 static inline int sci_rxd_in(struct uart_port *port)
 689 {
 690         if (port->mapbase == 0xffe00000)
 691                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 692         if (port->mapbase == 0xffe10000)
 693                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 694         return 1;
 695 }
 696 #elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \
 697       defined(CONFIG_CPU_SUBTYPE_SH7786)
 698 static inline int sci_rxd_in(struct uart_port *port)
 699 {
 700         if (port->mapbase == 0xffea0000)
 701                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 702         if (port->mapbase == 0xffeb0000)
 703                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 704         if (port->mapbase == 0xffec0000)
 705                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 706         if (port->mapbase == 0xffed0000)
 707                 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
 708         if (port->mapbase == 0xffee0000)
 709                 return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */
 710         if (port->mapbase == 0xffef0000)
 711                 return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
 712         return 1;
 713 }
 714 #elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \
 715       defined(CONFIG_CPU_SUBTYPE_SH7203) || \
 716       defined(CONFIG_CPU_SUBTYPE_SH7206) || \
 717       defined(CONFIG_CPU_SUBTYPE_SH7263)
 718 static inline int sci_rxd_in(struct uart_port *port)
 719 {
 720         if (port->mapbase == 0xfffe8000)
 721                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 722         if (port->mapbase == 0xfffe8800)
 723                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 724         if (port->mapbase == 0xfffe9000)
 725                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 726         if (port->mapbase == 0xfffe9800)
 727                 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
 728 #if defined(CONFIG_CPU_SUBTYPE_SH7201)
 729         if (port->mapbase == 0xfffeA000)
 730                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 731         if (port->mapbase == 0xfffeA800)
 732                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 733         if (port->mapbase == 0xfffeB000)
 734                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 735         if (port->mapbase == 0xfffeB800)
 736                 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
 737 #endif
 738         return 1;
 739 }
 740 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
 741 static inline int sci_rxd_in(struct uart_port *port)
 742 {
 743         if (port->mapbase == 0xf8400000)
 744                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 745         if (port->mapbase == 0xf8410000)
 746                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 747         if (port->mapbase == 0xf8420000)
 748                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 749         return 1;
 750 }
 751 #elif defined(CONFIG_CPU_SUBTYPE_SHX3)
 752 static inline int sci_rxd_in(struct uart_port *port)
 753 {
 754         if (port->mapbase == 0xffc30000)
 755                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 756         if (port->mapbase == 0xffc40000)
 757                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 758         if (port->mapbase == 0xffc50000)
 759                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 760         if (port->mapbase == 0xffc60000)
 761                 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
 762         return 1;
 763 }
 764 #endif
 765
 766 /*
 767  * Values for the BitRate Register (SCBRR)
 768  *
 769  * The values are actually divisors for a frequency which can
 770  * be internal to the SH3 (14.7456MHz) or derived from an external
 771  * clock source.  This driver assumes the internal clock is used;
 772  * to support using an external clock source, config options or
 773  * possibly command-line options would need to be added.
 774  *
 775  * Also, to support speeds below 2400 (why?) the lower 2 bits of
 776  * the SCSMR register would also need to be set to non-zero values.
 777  *
 778  * -- Greg Banks 27Feb2000
 779  *
 780  * Answer: The SCBRR register is only eight bits, and the value in
 781  * it gets larger with lower baud rates. At around 2400 (depending on
 782  * the peripherial module clock) you run out of bits. However the
 783  * lower two bits of SCSMR allow the module clock to be divided down,
 784  * scaling the value which is needed in SCBRR.
 785  *
 786  * -- Stuart Menefy - 23 May 2000
 787  *
 788  * I meant, why would anyone bother with bitrates below 2400.
 789  *
 790  * -- Greg Banks - 7Jul2000
 791  *
 792  * You "speedist"!  How will I use my 110bps ASR-33 teletype with paper
 793  * tape reader as a console!
 794  *
 795  * -- Mitch Davis - 15 Jul 2000
 796  */
 797
 798 #if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
 799     defined(CONFIG_CPU_SUBTYPE_SH7785) || \
 800     defined(CONFIG_CPU_SUBTYPE_SH7786)
 801 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
 802 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 803       defined(CONFIG_CPU_SUBTYPE_SH7720) || \
 804       defined(CONFIG_CPU_SUBTYPE_SH7721)
 805 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
 806 #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
 807       defined(CONFIG_CPU_SUBTYPE_SH7724)
 808 static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
 809 {
 810         if (port->type == PORT_SCIF)
 811                 return (clk+16*bps)/(32*bps)-1;
 812         else
 813                 return ((clk*2)+16*bps)/(16*bps)-1;
 814 }
 815 #define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
 816 #elif defined(__H8300H__) || defined(__H8300S__)
 817 #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
 818 #else /* Generic SH */
 819 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
 820 #endif