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Full support for Ginger Console
[linux-ginger.git] / drivers / staging / otus / hal / hpreg.c
blobd9894fe5f4ec0243b63b4ab2bc44d23f9dce49cc
1 /*
2 * Copyright (c) 2000-2005 ZyDAS Technology Corporation
3 * Copyright (c) 2007-2008 Atheros Communications Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17 /* */
18 /* Module Name : hpreg.c */
19 /* */
20 /* Abstract */
21 /* This module contains Regulatory Table and related function. */
22 /* */
23 /* NOTES */
24 /* None */
25 /* */
26 /************************************************************************/
27 #include "../80211core/cprecomp.h"
28 #include "hpani.h"
29 #include "hpreg.h"
30 #include "hpusb.h"
31
32 /* used throughout this file... */
33 #define N(a) (sizeof (a) / sizeof (a[0]))
34
35 #define HAL_MODE_11A_TURBO HAL_MODE_108A
36 #define HAL_MODE_11G_TURBO HAL_MODE_108G
37
38 #if 0
39 enum {
40 /* test groups */
41 FCC = 0x10,
42 MKK = 0x40,
43 ETSI = 0x30,
44 SD_NO_CTL = 0xe0,
45 NO_CTL = 0xff,
46 /* test modes */
47 CTL_MODE_M = 0x0f,
48 CTL_11A = 0,
49 CTL_11B = 1,
50 CTL_11G = 2,
51 CTL_TURBO = 3,
52 CTL_108G = 4,
53 CTL_2GHT20 = 5,
54 CTL_5GHT20 = 6,
55 CTL_2GHT40 = 7,
56 CTL_5GHT40 = 8
57 };
58 #endif
59
60 /*
61 * The following are flags for different requirements per reg domain.
62 * These requirements are either inhereted from the reg domain pair or
63 * from the unitary reg domain if the reg domain pair flags value is
64 * 0
65 */
66
67 enum {
68 NO_REQ = 0x00000000,
69 DISALLOW_ADHOC_11A = 0x00000001,
70 DISALLOW_ADHOC_11A_TURB = 0x00000002,
71 NEED_NFC = 0x00000004,
72
73 ADHOC_PER_11D = 0x00000008, /* Start Ad-Hoc mode */
74 ADHOC_NO_11A = 0x00000010,
75
76 PUBLIC_SAFETY_DOMAIN = 0x00000020, /* public safety domain */
77 LIMIT_FRAME_4MS = 0x00000040, /* 4msec limit on the frame length */
78 };
79
80 #define MKK5GHZ_FLAG1 (DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS)
81 #define MKK5GHZ_FLAG2 (DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC| LIMIT_FRAME_4MS)
82
83 typedef enum {
84 DFS_UNINIT_DOMAIN = 0, /* Uninitialized dfs domain */
85 DFS_FCC_DOMAIN = 1, /* FCC3 dfs domain */
86 DFS_ETSI_DOMAIN = 2, /* ETSI dfs domain */
87 } HAL_DFS_DOMAIN;
88
89 /*
90 * Used to set the RegDomain bitmask which chooses which frequency
91 * band specs are used.
92 */
93
94 #define BMLEN 2 /* Use 2 64 bit uint for channel bitmask
95 NB: Must agree with macro below (BM) */
96 #define BMZERO {(u64_t) 0, (u64_t) 0} /* BMLEN zeros */
97
98 #if 0
99
100 #define BM(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh, _fi, _fj, _fk, _fl) \
101 {((((_fa >= 0) && (_fa < 64)) ? (((u64_t) 1) << _fa) : (u64_t) 0) | \
102 (((_fb >= 0) && (_fb < 64)) ? (((u64_t) 1) << _fb) : (u64_t) 0) | \
103 (((_fc >= 0) && (_fc < 64)) ? (((u64_t) 1) << _fc) : (u64_t) 0) | \
104 (((_fd >= 0) && (_fd < 64)) ? (((u64_t) 1) << _fd) : (u64_t) 0) | \
105 (((_fe >= 0) && (_fe < 64)) ? (((u64_t) 1) << _fe) : (u64_t) 0) | \
106 (((_ff >= 0) && (_ff < 64)) ? (((u64_t) 1) << _ff) : (u64_t) 0) | \
107 (((_fg >= 0) && (_fg < 64)) ? (((u64_t) 1) << _fg) : (u64_t) 0) | \
108 (((_fh >= 0) && (_fh < 64)) ? (((u64_t) 1) << _fh) : (u64_t) 0) | \
109 (((_fi >= 0) && (_fi < 64)) ? (((u64_t) 1) << _fi) : (u64_t) 0) | \
110 (((_fj >= 0) && (_fj < 64)) ? (((u64_t) 1) << _fj) : (u64_t) 0) | \
111 (((_fk >= 0) && (_fk < 64)) ? (((u64_t) 1) << _fk) : (u64_t) 0) | \
112 (((_fl >= 0) && (_fl < 64)) ? (((u64_t) 1) << _fl) : (u64_t) 0) | \
113 ((((_fa > 63) && (_fa < 128)) ? (((u64_t) 1) << (_fa - 64)) : (u64_t) 0) | \
114 (((_fb > 63) && (_fb < 128)) ? (((u64_t) 1) << (_fb - 64)) : (u64_t) 0) | \
115 (((_fc > 63) && (_fc < 128)) ? (((u64_t) 1) << (_fc - 64)) : (u64_t) 0) | \
116 (((_fd > 63) && (_fd < 128)) ? (((u64_t) 1) << (_fd - 64)) : (u64_t) 0) | \
117 (((_fe > 63) && (_fe < 128)) ? (((u64_t) 1) << (_fe - 64)) : (u64_t) 0) | \
118 (((_ff > 63) && (_ff < 128)) ? (((u64_t) 1) << (_ff - 64)) : (u64_t) 0) | \
119 (((_fg > 63) && (_fg < 128)) ? (((u64_t) 1) << (_fg - 64)) : (u64_t) 0) | \
120 (((_fh > 63) && (_fh < 128)) ? (((u64_t) 1) << (_fh - 64)) : (u64_t) 0) | \
121 (((_fi > 63) && (_fi < 128)) ? (((u64_t) 1) << (_fi - 64)) : (u64_t) 0) | \
122 (((_fj > 63) && (_fj < 128)) ? (((u64_t) 1) << (_fj - 64)) : (u64_t) 0) | \
123 (((_fk > 63) && (_fk < 128)) ? (((u64_t) 1) << (_fk - 64)) : (u64_t) 0) | \
124 (((_fl > 63) && (_fl < 128)) ? (((u64_t) 1) << (_fl - 64)) : (u64_t) 0)))}
125
126 #else
127
128 #define BM(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh, _fi, _fj, _fk, _fl) \
129 {((((_fa >= 0) && (_fa < 64)) ? (((u64_t) 1) << (_fa&0x3f)) : (u64_t) 0) | \
130 (((_fb >= 0) && (_fb < 64)) ? (((u64_t) 1) << (_fb&0x3f)) : (u64_t) 0) | \
131 (((_fc >= 0) && (_fc < 64)) ? (((u64_t) 1) << (_fc&0x3f)) : (u64_t) 0) | \
132 (((_fd >= 0) && (_fd < 64)) ? (((u64_t) 1) << (_fd&0x3f)) : (u64_t) 0) | \
133 (((_fe >= 0) && (_fe < 64)) ? (((u64_t) 1) << (_fe&0x3f)) : (u64_t) 0) | \
134 (((_ff >= 0) && (_ff < 64)) ? (((u64_t) 1) << (_ff&0x3f)) : (u64_t) 0) | \
135 (((_fg >= 0) && (_fg < 64)) ? (((u64_t) 1) << (_fg&0x3f)) : (u64_t) 0) | \
136 (((_fh >= 0) && (_fh < 64)) ? (((u64_t) 1) << (_fh&0x3f)) : (u64_t) 0) | \
137 (((_fi >= 0) && (_fi < 64)) ? (((u64_t) 1) << (_fi&0x3f)) : (u64_t) 0) | \
138 (((_fj >= 0) && (_fj < 64)) ? (((u64_t) 1) << (_fj&0x3f)) : (u64_t) 0) | \
139 (((_fk >= 0) && (_fk < 64)) ? (((u64_t) 1) << (_fk&0x3f)) : (u64_t) 0) | \
140 (((_fl >= 0) && (_fl < 64)) ? (((u64_t) 1) << (_fl&0x3f)) : (u64_t) 0) | \
141 ((((_fa > 63) && (_fa < 128)) ? (((u64_t) 1) << ((_fa - 64)&0x3f)) : (u64_t) 0) | \
142 (((_fb > 63) && (_fb < 128)) ? (((u64_t) 1) << ((_fb - 64)&0x3f)) : (u64_t) 0) | \
143 (((_fc > 63) && (_fc < 128)) ? (((u64_t) 1) << ((_fc - 64)&0x3f)) : (u64_t) 0) | \
144 (((_fd > 63) && (_fd < 128)) ? (((u64_t) 1) << ((_fd - 64)&0x3f)) : (u64_t) 0) | \
145 (((_fe > 63) && (_fe < 128)) ? (((u64_t) 1) << ((_fe - 64)&0x3f)) : (u64_t) 0) | \
146 (((_ff > 63) && (_ff < 128)) ? (((u64_t) 1) << ((_ff - 64)&0x3f)) : (u64_t) 0) | \
147 (((_fg > 63) && (_fg < 128)) ? (((u64_t) 1) << ((_fg - 64)&0x3f)) : (u64_t) 0) | \
148 (((_fh > 63) && (_fh < 128)) ? (((u64_t) 1) << ((_fh - 64)&0x3f)) : (u64_t) 0) | \
149 (((_fi > 63) && (_fi < 128)) ? (((u64_t) 1) << ((_fi - 64)&0x3f)) : (u64_t) 0) | \
150 (((_fj > 63) && (_fj < 128)) ? (((u64_t) 1) << ((_fj - 64)&0x3f)) : (u64_t) 0) | \
151 (((_fk > 63) && (_fk < 128)) ? (((u64_t) 1) << ((_fk - 64)&0x3f)) : (u64_t) 0) | \
152 (((_fl > 63) && (_fl < 128)) ? (((u64_t) 1) << ((_fl - 64)&0x3f)) : (u64_t) 0)))}
153
154 #endif
155
156 /* Mask to check whether a domain is a multidomain or a single
157 domain */
158
159 #define MULTI_DOMAIN_MASK 0xFF00
160
161
162 /*
163 * The following describe the bit masks for different passive scan
164 * capability/requirements per regdomain.
165 */
166 #define NO_PSCAN 0x0ULL
167 #define PSCAN_FCC 0x0000000000000001ULL
168 #define PSCAN_FCC_T 0x0000000000000002ULL
169 #define PSCAN_ETSI 0x0000000000000004ULL
170 #define PSCAN_MKK1 0x0000000000000008ULL
171 #define PSCAN_MKK2 0x0000000000000010ULL
172 #define PSCAN_MKKA 0x0000000000000020ULL
173 #define PSCAN_MKKA_G 0x0000000000000040ULL
174 #define PSCAN_ETSIA 0x0000000000000080ULL
175 #define PSCAN_ETSIB 0x0000000000000100ULL
176 #define PSCAN_ETSIC 0x0000000000000200ULL
177 #define PSCAN_WWR 0x0000000000000400ULL
178 #define PSCAN_MKKA1 0x0000000000000800ULL
179 #define PSCAN_MKKA1_G 0x0000000000001000ULL
180 #define PSCAN_MKKA2 0x0000000000002000ULL
181 #define PSCAN_MKKA2_G 0x0000000000004000ULL
182 #define PSCAN_MKK3 0x0000000000008000ULL
183 #define PSCAN_DEFER 0x7FFFFFFFFFFFFFFFULL
184 #define IS_ECM_CHAN 0x8000000000000000ULL
185
186 /*
187 * THE following table is the mapping of regdomain pairs specified by
188 * an 8 bit regdomain value to the individual unitary reg domains
189 */
190
191 typedef struct reg_dmn_pair_mapping {
192 u16_t regDmnEnum; /* 16 bit reg domain pair */
193 u16_t regDmn5GHz; /* 5GHz reg domain */
194 u16_t regDmn2GHz; /* 2GHz reg domain */
195 u32_t flags5GHz; /* Requirements flags (AdHoc
196 disallow, noise floor cal needed,
197 etc) */
198 u32_t flags2GHz; /* Requirements flags (AdHoc
199 disallow, noise floor cal needed,
200 etc) */
201 u64_t pscanMask; /* Passive Scan flags which
202 can override unitary domain
203 passive scan flags. This
204 value is used as a mask on
205 the unitary flags*/
206 u16_t singleCC; /* Country code of single country if
207 a one-on-one mapping exists */
208 } REG_DMN_PAIR_MAPPING;
209
210 static REG_DMN_PAIR_MAPPING regDomainPairs[] = {
211 {NO_ENUMRD, FCC2, DEBUG_REG_DMN, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
212 {NULL1_WORLD, NULL1, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
213 {NULL1_ETSIB, NULL1, ETSIB, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
214 {NULL1_ETSIC, NULL1, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
215
216 {FCC2_FCCA, FCC2, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
217 {FCC2_WORLD, FCC2, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
218 {FCC2_ETSIC, FCC2, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
219 {FCC3_FCCA, FCC3, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
220 {FCC3_WORLD, FCC3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
221 {FCC4_FCCA, FCC4, FCCA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
222 {FCC5_FCCA, FCC5, FCCA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
223 {FCC6_FCCA, FCC6, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
224 {FCC6_WORLD, FCC6, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
225
226 {ETSI1_WORLD, ETSI1, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
227 {ETSI2_WORLD, ETSI2, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
228 {ETSI3_WORLD, ETSI3, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
229 {ETSI4_WORLD, ETSI4, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
230 {ETSI5_WORLD, ETSI5, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
231 {ETSI6_WORLD, ETSI6, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
232
233 {ETSI3_ETSIA, ETSI3, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
234 {FRANCE_RES, ETSI3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
235
236 {FCC1_WORLD, FCC1, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
237 {FCC1_FCCA, FCC1, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
238 {APL1_WORLD, APL1, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
239 {APL2_WORLD, APL2, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
240 {APL3_WORLD, APL3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
241 {APL4_WORLD, APL4, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
242 {APL5_WORLD, APL5, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
243 {APL6_WORLD, APL6, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
244 {APL8_WORLD, APL8, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
245 {APL9_WORLD, APL9, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
246
247 {APL3_FCCA, APL3, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
248 {APL1_ETSIC, APL1, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
249 {APL2_ETSIC, APL2, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
250 {APL2_FCCA, APL2, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
251 {APL2_APLD, APL2, APLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0},
252 {APL7_FCCA, APL7, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
253
254 {MKK1_MKKA, MKK1, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA, CTRY_JAPAN },
255 {MKK1_MKKB, MKK1, MKKA, MKK5GHZ_FLAG2, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN1 },
256 {MKK1_FCCA, MKK1, FCCA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1, CTRY_JAPAN2 },
257 {MKK1_MKKA1, MKK1, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN4 },
258 {MKK1_MKKA2, MKK1, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN5 },
259 {MKK1_MKKC, MKK1, MKKC, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1, CTRY_JAPAN6 },
260
261 /* MKK2 */
262 {MKK2_MKKA, MKK2, MKKA, MKK5GHZ_FLAG2, NEED_NFC, PSCAN_MKK2 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN3 },
263
264 /* MKK3 */
265 {MKK3_MKKA, MKK3, MKKA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN25 },
266 {MKK3_MKKB, MKK3, MKKA, MKK5GHZ_FLAG2, NEED_NFC, PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN7 },
267 {MKK3_MKKA1, MKK3, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN26 },
268 {MKK3_MKKA2, MKK3, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN8 },
269 {MKK3_MKKC, MKK3, MKKC, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN9 },
270 {MKK3_FCCA, MKK3, FCCA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN27 },
271
272 /* MKK4 */
273 {MKK4_MKKB, MKK4, MKKA, MKK5GHZ_FLAG2, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN10 },
274 {MKK4_MKKA1, MKK4, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN28 },
275 {MKK4_MKKA2, MKK4, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK3 |PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN11 },
276 {MKK4_MKKC, MKK4, MKKC, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK3, CTRY_JAPAN12 },
277 {MKK4_FCCA, MKK4, FCCA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN29 },
278 {MKK4_MKKA, MKK4, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA, CTRY_JAPAN36 },
279
280 /* MKK5 */
281 {MKK5_MKKB, MKK5, MKKA, MKK5GHZ_FLAG2, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN13 },
282 {MKK5_MKKA2, MKK5, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN14 },
283 {MKK5_MKKC, MKK5, MKKC, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK3, CTRY_JAPAN15 },
284
285 /* MKK6 */
286 {MKK6_MKKB, MKK6, MKKA, MKK5GHZ_FLAG2, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN16 },
287 {MKK6_MKKA2, MKK6, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN17 },
288 {MKK6_MKKC, MKK6, MKKC, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1, CTRY_JAPAN18 },
289 {MKK6_MKKA1, MKK6, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN30 },
290 {MKK6_FCCA, MKK6, FCCA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN31 },
291
292 /* MKK7 */
293 {MKK7_MKKB, MKK7, MKKA, MKK5GHZ_FLAG2, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN19 },
294 {MKK7_MKKA, MKK7, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN20 },
295 {MKK7_MKKC, MKK7, MKKC, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3, CTRY_JAPAN21 },
296 {MKK7_MKKA1, MKK7, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN32 },
297 {MKK7_FCCA, MKK7, FCCA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN33 },
298
299 /* MKK8 */
300 {MKK8_MKKB, MKK8, MKKA, MKK5GHZ_FLAG2, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN22 },
301 {MKK8_MKKA2, MKK8, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN23 },
302 {MKK8_MKKC, MKK8, MKKC, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 , CTRY_JAPAN24 },
303
304 /* MKK9 */
305 {MKK9_MKKA, MKK9, MKKA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN34 },
306 {MKK9_FCCA, MKK9, FCCA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN37 },
307 {MKK9_MKKA1, MKK9, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN38 },
308 {MKK9_MKKC, MKK9, MKKC, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN39 },
309 {MKK9_MKKA2, MKK9, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN40 },
310
311 /* MKK10 */
312 {MKK10_MKKA, MKK10, MKKA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN35 },
313 {MKK10_FCCA, MKK10, FCCA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN41 },
314 {MKK10_MKKA1, MKK10, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN42 },
315 {MKK10_MKKC, MKK10, MKKC, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN43 },
316 {MKK10_MKKA2, MKK10, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN44 },
317
318 /* MKK11 */
319 {MKK11_MKKA, MKK11, MKKA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN45 },
320 {MKK11_FCCA, MKK11, FCCA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN46 },
321 {MKK11_MKKA1, MKK11, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN47 },
322 {MKK11_MKKC, MKK11, MKKC, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN48 },
323 {MKK11_MKKA2, MKK11, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN49 },
324
325 /* MKK12 */
326 {MKK12_MKKA, MKK12, MKKA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN50 },
327 {MKK12_FCCA, MKK12, FCCA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN51 },
328 {MKK12_MKKA1, MKK12, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN52 },
329 {MKK12_MKKC, MKK12, MKKC, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN53 },
330 {MKK12_MKKA2, MKK12, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN54 },
331
332
333 /* These are super domains */
334 {WOR0_WORLD, WOR0_WORLD, WOR0_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
335 {WOR1_WORLD, WOR1_WORLD, WOR1_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
336 {WOR2_WORLD, WOR2_WORLD, WOR2_WORLD, DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
337 {WOR3_WORLD, WOR3_WORLD, WOR3_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
338 {WOR4_WORLD, WOR4_WORLD, WOR4_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
339 {WOR5_ETSIC, WOR5_ETSIC, WOR5_ETSIC, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
340 {WOR01_WORLD, WOR01_WORLD, WOR01_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
341 {WOR02_WORLD, WOR02_WORLD, WOR02_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
342 {EU1_WORLD, EU1_WORLD, EU1_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
343 {WOR9_WORLD, WOR9_WORLD, WOR9_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
344 {WORA_WORLD, WORA_WORLD, WORA_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
345 };
346
347 /*
348 * The following table is the master list for all different freqeuncy
349 * bands with the complete matrix of all possible flags and settings
350 * for each band if it is used in ANY reg domain.
351 */
352
353 #define DEF_REGDMN FCC1_FCCA
354 #define DEF_DMN_5 FCC1
355 #define DEF_DMN_2 FCCA
356 #define COUNTRY_ERD_FLAG 0x8000
357 #define WORLDWIDE_ROAMING_FLAG 0x4000
358 #define SUPER_DOMAIN_MASK 0x0fff
359 #define COUNTRY_CODE_MASK 0x03ff
360 #define CF_INTERFERENCE (CHANNEL_CW_INT | CHANNEL_RADAR_INT)
361 #define CHANNEL_14 (2484) /* 802.11g operation is not permitted on channel 14 */
362 #define IS_11G_CH14(_ch,_cf) \
363 (((_ch) == CHANNEL_14) && ((_cf) == CHANNEL_G))
364
365 #define YES TRUE
366 #define NO FALSE
367
368 enum {
369 CTRY_DEBUG = 0x1ff, /* debug country code */
370 CTRY_DEFAULT = 0 /* default country code */
371 };
372
373 typedef struct {
374 HAL_CTRY_CODE countryCode;
375 HAL_REG_DOMAIN regDmnEnum;
376 const char* isoName;
377 const char* name;
378 HAL_BOOL allow11g;
379 HAL_BOOL allow11aTurbo;
380 HAL_BOOL allow11gTurbo;
381 HAL_BOOL allow11na; /* HT-40 allowed in 5GHz? */
382 HAL_BOOL allow11ng; /* HT-40 allowed in 2GHz? */
383 u16_t outdoorChanStart;
384 } COUNTRY_CODE_TO_ENUM_RD;
385
386 static COUNTRY_CODE_TO_ENUM_RD allCountries[] = {
387 {CTRY_DEBUG, NO_ENUMRD, "DB", "DEBUG", YES, YES, YES, YES, YES, 7000 },
388 {CTRY_DEFAULT, DEF_REGDMN, "NA", "NO_COUNTRY_SET", YES, YES, YES, YES, YES, 7000 },
389 {CTRY_ALBANIA, NULL1_WORLD, "AL", "ALBANIA", YES, NO, YES, NO, YES, 7000 },
390 {CTRY_ALGERIA, NULL1_WORLD, "DZ", "ALGERIA", YES, NO, YES, NO, YES, 7000 },
391 {CTRY_ARGENTINA, APL3_WORLD, "AR", "ARGENTINA", YES, NO, NO, NO, NO, 7000 },
392 {CTRY_ARMENIA, ETSI4_WORLD, "AM", "ARMENIA", YES, NO, YES, NO, YES, 7000 },
393 {CTRY_AUSTRALIA, FCC6_WORLD, "AU", "AUSTRALIA", YES, YES, YES, YES, YES, 7000 },
394 {CTRY_AUSTRIA, ETSI2_WORLD, "AT", "AUSTRIA", YES, NO, YES, YES, YES, 7000 },
395 {CTRY_AZERBAIJAN, ETSI4_WORLD, "AZ", "AZERBAIJAN", YES, YES, YES, YES, YES, 7000 },
396 {CTRY_BAHRAIN, APL6_WORLD, "BH", "BAHRAIN", YES, NO, YES, NO, YES, 7000 },
397 {CTRY_BELARUS, ETSI1_WORLD, "BY", "BELARUS", YES, NO, YES, YES, YES, 7000 },
398 {CTRY_BELGIUM, ETSI1_WORLD, "BE", "BELGIUM", YES, NO, YES, YES, YES, 7000 },
399 {CTRY_BELIZE, APL1_ETSIC, "BZ", "BELIZE", YES, YES, YES, YES, YES, 7000 },
400 {CTRY_BOLIVIA, APL1_ETSIC, "BO", "BOLVIA", YES, YES, YES, YES, YES, 7000 },
401 {CTRY_BRAZIL, FCC3_WORLD, "BR", "BRAZIL", NO, NO, NO, NO, NO, 7000 },
402 {CTRY_BRUNEI_DARUSSALAM,APL1_WORLD,"BN", "BRUNEI DARUSSALAM", YES, YES, YES, YES, YES, 7000 },
403 {CTRY_BULGARIA, ETSI6_WORLD, "BG", "BULGARIA", YES, NO, YES, YES, YES, 7000 },
404 {CTRY_CANADA, FCC6_FCCA, "CA", "CANADA", YES, YES, YES, YES, YES, 7000 },
405 {CTRY_CHILE, APL6_WORLD, "CL", "CHILE", YES, YES, YES, YES, YES, 7000 },
406 {CTRY_CHINA, APL1_WORLD, "CN", "CHINA", YES, YES, YES, YES, YES, 7000 },
407 {CTRY_COLOMBIA, FCC1_FCCA, "CO", "COLOMBIA", YES, NO, YES, NO, YES, 7000 },
408 {CTRY_COSTA_RICA, FCC1_WORLD, "CR", "COSTA RICA", YES, NO, YES, NO, YES, 7000 },
409 {CTRY_CROATIA, ETSI3_WORLD, "HR", "CROATIA", YES, NO, YES, NO, YES, 7000 },
410 {CTRY_CYPRUS, ETSI3_WORLD, "CY", "CYPRUS", YES, YES, YES, YES, YES, 7000 },
411 {CTRY_CZECH, ETSI3_WORLD, "CZ", "CZECH REPUBLIC", YES, NO, YES, YES, YES, 7000 },
412 {CTRY_DENMARK, ETSI1_WORLD, "DK", "DENMARK", YES, NO, YES, YES, YES, 7000 },
413 {CTRY_DOMINICAN_REPUBLIC,FCC1_FCCA,"DO", "DOMINICAN REPUBLIC", YES, YES, YES, YES, YES, 7000 },
414 {CTRY_ECUADOR, FCC1_WORLD, "EC", "ECUADOR", YES, NO, NO, NO, YES, 7000 },
415 {CTRY_EGYPT, ETSI3_WORLD, "EG", "EGYPT", YES, NO, YES, NO, YES, 7000 },
416 {CTRY_EL_SALVADOR, FCC1_WORLD, "SV", "EL SALVADOR", YES, NO, YES, NO, YES, 7000 },
417 {CTRY_ESTONIA, ETSI1_WORLD, "EE", "ESTONIA", YES, NO, YES, YES, YES, 7000 },
418 {CTRY_FINLAND, ETSI1_WORLD, "FI", "FINLAND", YES, NO, YES, YES, YES, 7000 },
419 {CTRY_FRANCE, ETSI1_WORLD, "FR", "FRANCE", YES, NO, YES, YES, YES, 7000 },
420 {CTRY_FRANCE2, ETSI3_WORLD, "F2", "FRANCE_RES", YES, NO, YES, YES, YES, 7000 },
421 {CTRY_GEORGIA, ETSI4_WORLD, "GE", "GEORGIA", YES, YES, YES, YES, YES, 7000 },
422 {CTRY_GERMANY, ETSI1_WORLD, "DE", "GERMANY", YES, NO, YES, YES, YES, 7000 },
423 {CTRY_GREECE, ETSI1_WORLD, "GR", "GREECE", YES, NO, YES, YES, YES, 7000 },
424 {CTRY_GUATEMALA, FCC1_FCCA, "GT", "GUATEMALA", YES, YES, YES, YES, YES, 7000 },
425 {CTRY_HONDURAS, NULL1_WORLD, "HN", "HONDURAS", YES, NO, YES, NO, YES, 7000 },
426 {CTRY_HONG_KONG, FCC2_WORLD, "HK", "HONG KONG", YES, YES, YES, YES, YES, 7000 },
427 {CTRY_HUNGARY, ETSI4_WORLD, "HU", "HUNGARY", YES, NO, YES, YES, YES, 7000 },
428 {CTRY_ICELAND, ETSI1_WORLD, "IS", "ICELAND", YES, NO, YES, YES, YES, 7000 },
429 {CTRY_INDIA, APL6_WORLD, "IN", "INDIA", YES, NO, YES, NO, YES, 7000 },
430 {CTRY_INDONESIA, APL1_WORLD, "ID", "INDONESIA", YES, NO, YES, NO, YES, 7000 },
431 {CTRY_IRAN, APL1_WORLD, "IR", "IRAN", YES, YES, YES, YES, YES, 7000 },
432 {CTRY_IRELAND, ETSI1_WORLD, "IE", "IRELAND", YES, NO, YES, YES, YES, 7000 },
433 {CTRY_ISRAEL, ETSI3_WORLD, "IL", "ISRAEL", YES, NO, YES, NO, YES, 7000 },
434 {CTRY_ISRAEL2, NULL1_ETSIB, "ISR","ISRAEL_RES", YES, NO, YES, NO, YES, 7000 },
435 {CTRY_ITALY, ETSI1_WORLD, "IT", "ITALY", YES, NO, YES, YES, YES, 7000 },
436 {CTRY_JAMAICA, ETSI1_WORLD, "JM", "JAMAICA", YES, NO, YES, YES, YES, 7000 },
437 {CTRY_JAPAN, MKK1_MKKA, "JP", "JAPAN", YES, NO, NO, NO, NO, 7000 },
438 {CTRY_JAPAN1, MKK1_MKKB, "J1", "JAPAN1", YES, NO, NO, NO, NO, 7000 },
439 {CTRY_JAPAN2, MKK1_FCCA, "J2", "JAPAN2", YES, NO, NO, NO, NO, 7000 },
440 {CTRY_JAPAN3, MKK2_MKKA, "J3", "JAPAN3", YES, NO, NO, NO, NO, 7000 },
441 {CTRY_JAPAN4, MKK1_MKKA1, "J4", "JAPAN4", YES, NO, NO, NO, NO, 7000 },
442 {CTRY_JAPAN5, MKK1_MKKA2, "J5", "JAPAN5", YES, NO, NO, NO, NO, 7000 },
443 {CTRY_JAPAN6, MKK1_MKKC, "J6", "JAPAN6", YES, NO, NO, NO, NO, 7000 },
444 {CTRY_JAPAN7, MKK3_MKKB, "J7", "JAPAN7", YES, NO, NO, NO, NO, 7000 },
445 {CTRY_JAPAN8, MKK3_MKKA2, "J8", "JAPAN8", YES, NO, NO, NO, NO, 7000 },
446 {CTRY_JAPAN9, MKK3_MKKC, "J9", "JAPAN9", YES, NO, NO, NO, NO, 7000 },
447 {CTRY_JAPAN10, MKK4_MKKB, "J10", "JAPAN10", YES, NO, NO, NO, NO, 7000 },
448 {CTRY_JAPAN11, MKK4_MKKA2, "J11", "JAPAN11", YES, NO, NO, NO, NO, 7000 },
449 {CTRY_JAPAN12, MKK4_MKKC, "J12", "JAPAN12", YES, NO, NO, NO, NO, 7000 },
450 {CTRY_JAPAN13, MKK5_MKKB, "J13", "JAPAN13", YES, NO, NO, NO, NO, 7000 },
451 {CTRY_JAPAN14, MKK5_MKKA2, "J14", "JAPAN14", YES, NO, NO, NO, NO, 7000 },
452 {CTRY_JAPAN15, MKK5_MKKC, "J15", "JAPAN15", YES, NO, NO, NO, NO, 7000 },
453 {CTRY_JAPAN16, MKK6_MKKB, "J16", "JAPAN16", YES, NO, NO, NO, NO, 7000 },
454 {CTRY_JAPAN17, MKK6_MKKA2, "J17", "JAPAN17", YES, NO, NO, NO, NO, 7000 },
455 {CTRY_JAPAN18, MKK6_MKKC, "J18", "JAPAN18", YES, NO, NO, NO, NO, 7000 },
456 {CTRY_JAPAN19, MKK7_MKKB, "J19", "JAPAN19", YES, NO, NO, NO, NO, 7000 },
457 {CTRY_JAPAN20, MKK7_MKKA, "J20", "JAPAN20", YES, NO, NO, NO, NO, 7000 },
458 {CTRY_JAPAN21, MKK7_MKKC, "J21", "JAPAN21", YES, NO, NO, NO, NO, 7000 },
459 {CTRY_JAPAN22, MKK8_MKKB, "J22", "JAPAN22", YES, NO, NO, NO, NO, 7000 },
460 {CTRY_JAPAN23, MKK8_MKKA2, "J23", "JAPAN23", YES, NO, NO, NO, NO, 7000 },
461 {CTRY_JAPAN24, MKK8_MKKC, "J24", "JAPAN24", YES, NO, NO, NO, NO, 7000 },
462 {CTRY_JAPAN25, MKK3_MKKA, "J25", "JAPAN25", YES, NO, NO, NO, NO, 7000 },
463 {CTRY_JAPAN26, MKK3_MKKA1, "J26", "JAPAN26", YES, NO, NO, NO, NO, 7000 },
464 {CTRY_JAPAN27, MKK3_FCCA, "J27", "JAPAN27", YES, NO, NO, NO, NO, 7000 },
465 {CTRY_JAPAN28, MKK4_MKKA1, "J28", "JAPAN28", YES, NO, NO, NO, NO, 7000 },
466 {CTRY_JAPAN29, MKK4_FCCA, "J29", "JAPAN29", YES, NO, NO, NO, NO, 7000 },
467 {CTRY_JAPAN30, MKK6_MKKA1, "J30", "JAPAN30", YES, NO, NO, NO, NO, 7000 },
468 {CTRY_JAPAN31, MKK6_FCCA, "J31", "JAPAN31", YES, NO, NO, NO, NO, 7000 },
469 {CTRY_JAPAN32, MKK7_MKKA1, "J32", "JAPAN32", YES, NO, NO, NO, NO, 7000 },
470 {CTRY_JAPAN33, MKK7_FCCA, "J33", "JAPAN33", YES, NO, NO, NO, NO, 7000 },
471 {CTRY_JAPAN34, MKK9_MKKA, "J34", "JAPAN34", YES, NO, NO, NO, NO, 7000 },
472 {CTRY_JAPAN35, MKK10_MKKA, "J35", "JAPAN35", YES, NO, NO, NO, NO, 7000 },
473 {CTRY_JAPAN36, MKK4_MKKA, "J36", "JAPAN36", YES, NO, NO, NO, NO, 7000 },
474 {CTRY_JAPAN37, MKK9_FCCA, "J37", "JAPAN37", YES, NO, NO, NO, NO, 7000 },
475 {CTRY_JAPAN38, MKK9_MKKA1, "J38", "JAPAN38", YES, NO, NO, NO, NO, 7000 },
476 {CTRY_JAPAN39, MKK9_MKKC, "J39", "JAPAN39", YES, NO, NO, NO, NO, 7000 },
477 {CTRY_JAPAN40, MKK10_MKKA2, "J40", "JAPAN40", YES, NO, NO, NO, NO, 7000 },
478 {CTRY_JAPAN41, MKK10_FCCA, "J41", "JAPAN41", YES, NO, NO, NO, NO, 7000 },
479 {CTRY_JAPAN42, MKK10_MKKA1, "J42", "JAPAN42", YES, NO, NO, NO, NO, 7000 },
480 {CTRY_JAPAN43, MKK10_MKKC, "J43", "JAPAN43", YES, NO, NO, NO, NO, 7000 },
481 {CTRY_JAPAN44, MKK10_MKKA2, "J44", "JAPAN44", YES, NO, NO, NO, NO, 7000 },
482 {CTRY_JAPAN45, MKK11_MKKA, "J45", "JAPAN45", YES, NO, NO, NO, NO, 7000 },
483 {CTRY_JAPAN46, MKK11_FCCA, "J46", "JAPAN46", YES, NO, NO, NO, NO, 7000 },
484 {CTRY_JAPAN47, MKK11_MKKA1, "J47", "JAPAN47", YES, NO, NO, NO, NO, 7000 },
485 {CTRY_JAPAN48, MKK11_MKKC, "J48", "JAPAN48", YES, NO, NO, NO, NO, 7000 },
486 {CTRY_JAPAN49, MKK11_MKKA2, "J49", "JAPAN49", YES, NO, NO, NO, NO, 7000 },
487 {CTRY_JAPAN50, MKK12_MKKA, "J50", "JAPAN50", YES, NO, NO, NO, NO, 7000 },
488 {CTRY_JAPAN51, MKK12_FCCA, "J51", "JAPAN51", YES, NO, NO, NO, NO, 7000 },
489 {CTRY_JAPAN52, MKK12_MKKA1, "J52", "JAPAN52", YES, NO, NO, NO, NO, 7000 },
490 {CTRY_JAPAN53, MKK12_MKKC, "J53", "JAPAN53", YES, NO, NO, NO, NO, 7000 },
491 {CTRY_JAPAN54, MKK12_MKKA2, "J54", "JAPAN54", YES, NO, NO, NO, NO, 7000 },
492 {CTRY_JORDAN, ETSI2_WORLD, "JO", "JORDAN", YES, NO, YES, NO, YES, 7000 },
493 {CTRY_KAZAKHSTAN, NULL1_WORLD, "KZ", "KAZAKHSTAN", YES, NO, YES, NO, YES, 7000 },
494 {CTRY_KOREA_NORTH, APL9_WORLD, "KP", "NORTH KOREA", YES, NO, NO, YES, YES, 7000 },
495 {CTRY_KOREA_ROC, APL9_WORLD, "KR", "KOREA REPUBLIC", YES, NO, NO, NO, NO, 7000 },
496 {CTRY_KOREA_ROC2, APL2_APLD, "K2", "KOREA REPUBLIC2",YES, NO, NO, NO, NO, 7000 },
497 {CTRY_KOREA_ROC3, APL9_WORLD, "K3", "KOREA REPUBLIC3",YES, NO, NO, NO, NO, 7000 },
498 {CTRY_KUWAIT, NULL1_WORLD, "KW", "KUWAIT", YES, NO, YES, NO, YES, 7000 },
499 {CTRY_LATVIA, ETSI1_WORLD, "LV", "LATVIA", YES, NO, YES, YES, YES, 7000 },
500 {CTRY_LEBANON, NULL1_WORLD, "LB", "LEBANON", YES, NO, YES, NO, YES, 7000 },
501 {CTRY_LIECHTENSTEIN,ETSI1_WORLD, "LI", "LIECHTENSTEIN", YES, NO, YES, YES, YES, 7000 },
502 {CTRY_LITHUANIA, ETSI1_WORLD, "LT", "LITHUANIA", YES, NO, YES, YES, YES, 7000 },
503 {CTRY_LUXEMBOURG, ETSI1_WORLD, "LU", "LUXEMBOURG", YES, NO, YES, YES, YES, 7000 },
504 {CTRY_MACAU, FCC2_WORLD, "MO", "MACAU", YES, YES, YES, YES, YES, 7000 },
505 {CTRY_MACEDONIA, NULL1_WORLD, "MK", "MACEDONIA", YES, NO, YES, NO, YES, 7000 },
506 {CTRY_MALAYSIA, APL8_WORLD, "MY", "MALAYSIA", NO, NO, NO, NO, NO, 7000 },
507 {CTRY_MALTA, ETSI1_WORLD, "MT", "MALTA", YES, NO, YES, YES, YES, 7000 },
508 {CTRY_MEXICO, FCC1_FCCA, "MX", "MEXICO", YES, YES, YES, YES, YES, 7000 },
509 {CTRY_MONACO, ETSI4_WORLD, "MC", "MONACO", YES, YES, YES, YES, YES, 7000 },
510 {CTRY_MOROCCO, NULL1_WORLD, "MA", "MOROCCO", YES, NO, YES, NO, YES, 7000 },
511 {CTRY_NETHERLANDS, ETSI1_WORLD, "NL", "NETHERLANDS", YES, NO, YES, YES, YES, 7000 },
512 {CTRY_NETHERLANDS_ANT, ETSI1_WORLD, "AN", "NETHERLANDS-ANTILLES", YES, NO, YES, YES, YES, 7000 },
513 {CTRY_NEW_ZEALAND, FCC2_ETSIC, "NZ", "NEW ZEALAND", YES, NO, YES, NO, YES, 7000 },
514 {CTRY_NORWAY, ETSI1_WORLD, "NO", "NORWAY", YES, NO, YES, YES, YES, 7000 },
515 {CTRY_OMAN, APL6_WORLD, "OM", "OMAN", YES, NO, YES, NO, YES, 7000 },
516 {CTRY_PAKISTAN, NULL1_WORLD, "PK", "PAKISTAN", YES, NO, YES, NO, YES, 7000 },
517 {CTRY_PANAMA, FCC1_FCCA, "PA", "PANAMA", YES, YES, YES, YES, YES, 7000 },
518 {CTRY_PERU, APL1_WORLD, "PE", "PERU", YES, NO, YES, NO, YES, 7000 },
519 {CTRY_PHILIPPINES, APL1_WORLD, "PH", "PHILIPPINES", YES, YES, YES, YES, YES, 7000 },
520 {CTRY_POLAND, ETSI1_WORLD, "PL", "POLAND", YES, NO, YES, YES, YES, 7000 },
521 {CTRY_PORTUGAL, ETSI1_WORLD, "PT", "PORTUGAL", YES, NO, YES, YES, YES, 7000 },
522 {CTRY_PUERTO_RICO, FCC1_FCCA, "PR", "PUERTO RICO", YES, YES, YES, YES, YES, 7000 },
523 {CTRY_QATAR, NULL1_WORLD, "QA", "QATAR", YES, NO, YES, NO, YES, 7000 },
524 {CTRY_ROMANIA, NULL1_WORLD, "RO", "ROMANIA", YES, NO, YES, NO, YES, 7000 },
525 {CTRY_RUSSIA, NULL1_WORLD, "RU", "RUSSIA", YES, NO, YES, NO, YES, 7000 },
526 {CTRY_SAUDI_ARABIA,NULL1_WORLD, "SA", "SAUDI ARABIA", YES, NO, YES, NO, YES, 7000 },
527 {CTRY_SERBIA_MONT, ETSI1_WORLD, "CS", "SERBIA & MONTENEGRO", YES, NO, YES, YES, YES, 7000 },
528 {CTRY_SINGAPORE, APL6_WORLD, "SG", "SINGAPORE", YES, YES, YES, YES, YES, 7000 },
529 {CTRY_SLOVAKIA, ETSI1_WORLD, "SK", "SLOVAK REPUBLIC",YES, NO, YES, YES, YES, 7000 },
530 {CTRY_SLOVENIA, ETSI1_WORLD, "SI", "SLOVENIA", YES, NO, YES, YES, YES, 7000 },
531 {CTRY_SOUTH_AFRICA,FCC3_WORLD, "ZA", "SOUTH AFRICA", YES, NO, YES, NO, YES, 7000 },
532 {CTRY_SPAIN, ETSI1_WORLD, "ES", "SPAIN", YES, NO, YES, YES, YES, 7000 },
533 {CTRY_SRILANKA, FCC3_WORLD, "LK", "SRI LANKA", YES, NO, YES, NO, YES, 7000 },
534 {CTRY_SWEDEN, ETSI1_WORLD, "SE", "SWEDEN", YES, NO, YES, YES, YES, 7000 },
535 {CTRY_SWITZERLAND, ETSI1_WORLD, "CH", "SWITZERLAND", YES, NO, YES, YES, YES, 7000 },
536 {CTRY_SYRIA, NULL1_WORLD, "SY", "SYRIA", YES, NO, YES, NO, YES, 7000 },
537 {CTRY_TAIWAN, APL3_FCCA, "TW", "TAIWAN", YES, YES, YES, YES, YES, 7000 },
538 {CTRY_THAILAND, NULL1_WORLD, "TH", "THAILAND", YES, NO, YES, NO, YES, 7000 },
539 {CTRY_TRINIDAD_Y_TOBAGO,ETSI4_WORLD,"TT", "TRINIDAD & TOBAGO", YES, NO, YES, NO, YES, 7000 },
540 {CTRY_TUNISIA, ETSI3_WORLD, "TN", "TUNISIA", YES, NO, YES, NO, YES, 7000 },
541 {CTRY_TURKEY, ETSI3_WORLD, "TR", "TURKEY", YES, NO, YES, NO, YES, 7000 },
542 {CTRY_UKRAINE, NULL1_WORLD, "UA", "UKRAINE", YES, NO, YES, NO, YES, 7000 },
543 {CTRY_UAE, NULL1_WORLD, "AE", "UNITED ARAB EMIRATES", YES, NO, YES, NO, YES, 7000 },
544 {CTRY_UNITED_KINGDOM, ETSI1_WORLD,"GB", "UNITED KINGDOM", YES, NO, YES, NO, YES, 7000 },
545 {CTRY_UNITED_STATES, FCC3_FCCA, "US", "UNITED STATES", YES, YES, YES, YES, YES, 5825 },
546 {CTRY_UNITED_STATES_FCC49, FCC4_FCCA, "PS", "UNITED STATES (PUBLIC SAFETY)", YES, YES, YES, YES, YES, 7000 },
547 {CTRY_URUGUAY, FCC1_WORLD, "UY", "URUGUAY", YES, NO, YES, NO, YES, 7000 },
548 {CTRY_UZBEKISTAN, FCC3_FCCA, "UZ", "UZBEKISTAN", YES, YES, YES, YES, YES, 7000 },
549 {CTRY_VENEZUELA, APL2_ETSIC, "VE", "VENEZUELA", YES, NO, YES, NO, YES, 7000 },
550 {CTRY_VIET_NAM, NULL1_WORLD, "VN", "VIET NAM", YES, NO, YES, NO, YES, 7000 },
551 {CTRY_YEMEN, NULL1_WORLD, "YE", "YEMEN", YES, NO, YES, NO, YES, 7000 },
552 {CTRY_ZIMBABWE, NULL1_WORLD, "ZW", "ZIMBABWE", YES, NO, YES, NO, YES, 7000 }
553 };
554
555 typedef struct RegDmnFreqBand {
556 u16_t lowChannel; /* Low channel center in MHz */
557 u16_t highChannel; /* High Channel center in MHz */
558 u8_t powerDfs; /* Max power (dBm) for channel
559 range when using DFS */
560 u8_t antennaMax; /* Max allowed antenna gain */
561 u8_t channelBW; /* Bandwidth of the channel */
562 u8_t channelSep; /* Channel separation within
563 the band */
564 u64_t useDfs; /* Use DFS in the RegDomain
565 if corresponding bit is set */
566 u64_t usePassScan; /* Use Passive Scan in the RegDomain
567 if corresponding bit is set */
568 u8_t regClassId; /* Regulatory class id */
569 u8_t useExtChanDfs; /* Regulatory class id */
570 } REG_DMN_FREQ_BAND;
571
572 /* Bit masks for DFS per regdomain */
573
574 enum {
575 NO_DFS = 0x0000000000000000ULL,
576 DFS_FCC3 = 0x0000000000000001ULL,
577 DFS_ETSI = 0x0000000000000002ULL,
578 DFS_MKK4 = 0x0000000000000004ULL,
579 };
580
581 /* The table of frequency bands is indexed by a bitmask. The ordering
582 * must be consistent with the enum below. When adding a new
583 * frequency band, be sure to match the location in the enum with the
584 * comments
585 */
586
587 /*
588 * 5GHz 11A channel tags
589 */
590
591 enum {
592 F1_4915_4925,
593 F1_4935_4945,
594 F1_4920_4980,
595 F1_4942_4987,
596 F1_4945_4985,
597 F1_4950_4980,
598 F1_5035_5040,
599 F1_5040_5080,
600 F1_5055_5055,
601
602 F1_5120_5240,
603
604 F1_5170_5230,
605 F2_5170_5230,
606
607 F1_5180_5240,
608 F2_5180_5240,
609 F3_5180_5240,
610 F4_5180_5240,
611 F5_5180_5240,
612 F6_5180_5240,
613 F7_5180_5240,
614
615 F1_5180_5320,
616
617 F1_5240_5280,
618
619 F1_5260_5280,
620
621 F1_5260_5320,
622 F2_5260_5320,
623 F3_5260_5320,
624 F4_5260_5320,
625 F5_5260_5320,
626 F6_5260_5320,
627 F7_5260_5320,
628
629 F1_5260_5700,
630
631 F1_5280_5320,
632
633 F1_5500_5580,
634
635 F1_5500_5620,
636
637 F1_5500_5700,
638 F2_5500_5700,
639 F3_5500_5700,
640 F4_5500_5700,
641
642 F1_5660_5700,
643
644 F1_5745_5805,
645 F2_5745_5805,
646 F3_5745_5805,
647
648 F1_5745_5825,
649 F2_5745_5825,
650 F3_5745_5825,
651 F4_5745_5825,
652 F5_5745_5825,
653 F6_5745_5825,
654
655 W1_4920_4980,
656 W1_5040_5080,
657 W1_5170_5230,
658 W1_5180_5240,
659 W1_5260_5320,
660 W1_5745_5825,
661 W1_5500_5700,
662 W2_5260_5320,
663 W2_5180_5240,
664 W2_5825_5825,
665 };
666
667 static REG_DMN_FREQ_BAND regDmn5GhzFreq[] = {
668 { 4915, 4925, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2, 16, 0 }, /* F1_4915_4925 */
669 { 4935, 4945, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2, 16, 0 }, /* F1_4935_4945 */
670 { 4920, 4980, 23, 0, 20, 20, NO_DFS, PSCAN_MKK2, 7, 0 }, /* F1_4920_4980 */
671 { 4942, 4987, 27, 6, 5, 5, DFS_FCC3, PSCAN_FCC, 0, 0 }, /* F1_4942_4987 */
672 { 4945, 4985, 30, 6, 10, 5, DFS_FCC3, PSCAN_FCC, 0, 0 }, /* F1_4945_4985 */
673 { 4950, 4980, 33, 6, 20, 5, DFS_FCC3, PSCAN_FCC, 0, 0 }, /* F1_4950_4980 */
674 { 5035, 5040, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2, 12, 0 }, /* F1_5035_5040 */
675 { 5040, 5080, 23, 0, 20, 20, NO_DFS, PSCAN_MKK2, 2, 0 }, /* F1_5040_5080 */
676 { 5055, 5055, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2, 12, 0 }, /* F1_5055_5055 */
677
678 { 5120, 5240, 5, 6, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* F1_5120_5240 */
679
680 { 5170, 5230, 23, 0, 20, 20, NO_DFS, PSCAN_MKK1 | PSCAN_MKK2, 1, 0 }, /* F1_5170_5230 */
681 { 5170, 5230, 20, 0, 20, 20, NO_DFS, PSCAN_MKK1 | PSCAN_MKK2, 1, 0 }, /* F2_5170_5230 */
682
683 { 5180, 5240, 15, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0, 0 }, /* F1_5180_5240 */
684 { 5180, 5240, 17, 6, 20, 20, NO_DFS, PSCAN_FCC, 1, 0 }, /* F2_5180_5240 */
685 { 5180, 5240, 18, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0, 0 }, /* F3_5180_5240 */
686 { 5180, 5240, 20, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0, 0 }, /* F4_5180_5240 */
687 { 5180, 5240, 23, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0, 0 }, /* F5_5180_5240 */
688 { 5180, 5240, 23, 6, 20, 20, NO_DFS, PSCAN_FCC, 0, 0 }, /* F6_5180_5240 */
689 { 5180, 5240, 23, 6, 20, 20, NO_DFS, NO_PSCAN, 0 }, /* F7_5180_5240 */
690
691 { 5180, 5320, 20, 6, 20, 20, DFS_ETSI, PSCAN_ETSI, 0, 0 }, /* F1_5180_5320 */
692
693 { 5240, 5280, 23, 0, 20, 20, DFS_FCC3, PSCAN_FCC | PSCAN_ETSI, 0, 0 }, /* F1_5240_5280 */
694
695 { 5260, 5280, 23, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 0, 0 }, /* F1_5260_5280 */
696
697 { 5260, 5320, 18, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 0, 0 }, /* F1_5260_5320 */
698
699 { 5260, 5320, 20, 0, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK4, PSCAN_FCC | PSCAN_ETSI | PSCAN_MKK3 , 0, 0 },
700 /* F2_5260_5320 */
701
702 { 5260, 5320, 20, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 2, 0 }, /* F3_5260_5320 */
703 { 5260, 5320, 23, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 2, 0 }, /* F4_5260_5320 */
704 { 5260, 5320, 23, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 0, 0 }, /* F5_5260_5320 */
705 { 5260, 5320, 30, 0, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* F6_5260_5320 */
706 { 5260, 5320, 17, 6, 20, 20, DFS_ETSI, PSCAN_ETSI, 0, 0 }, /* F7_5260_5320 */
707
708 { 5260, 5700, 5, 6, 20, 20, DFS_FCC3 | DFS_ETSI, NO_PSCAN, 0, 0 }, /* F1_5260_5700 */
709
710 { 5280, 5320, 17, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 0, 0 }, /* F1_5280_5320 */
711
712 { 5500, 5580, 23, 6, 20, 20, DFS_FCC3, PSCAN_FCC, 0}, /* F1_5500_5580 */
713
714 { 5500, 5620, 30, 6, 20, 20, DFS_ETSI, PSCAN_ETSI, 0, 0 }, /* F1_5500_5620 */
715
716 { 5500, 5700, 20, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 4, 0 }, /* F1_5500_5700 */
717 { 5500, 5700, 27, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 0, 0 }, /* F2_5500_5700 */
718 { 5500, 5700, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 0, 0 }, /* F3_5500_5700 */
719 { 5500, 5700, 20, 0, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK4, PSCAN_MKK3 | PSCAN_FCC, 0, 0 },
720 /* F4_5500_5700 */
721
722 { 5660, 5700, 23, 6, 20, 20, DFS_FCC3, PSCAN_FCC, 0}, /* F1_5660_5700 */
723
724 { 5745, 5805, 23, 0, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* F1_5745_5805 */
725 { 5745, 5805, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* F2_5745_5805 */
726 { 5745, 5805, 30, 6, 20, 20, DFS_ETSI, PSCAN_ETSI, 0, 0 }, /* F3_5745_5805 */
727 { 5745, 5825, 5, 6, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* F1_5745_5825 */
728 { 5745, 5825, 17, 0, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* F2_5745_5825 */
729 { 5745, 5825, 20, 0, 20, 20, DFS_ETSI, NO_PSCAN, 0, 0 }, /* F3_5745_5825 */
730 { 5745, 5825, 30, 0, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* F4_5745_5825 */
731 { 5745, 5825, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 3, 0 }, /* F5_5745_5825 */
732 { 5745, 5825, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* F6_5745_5825 */
733
734 /*
735 * Below are the world roaming channels
736 * All WWR domains have no power limit, instead use the card's CTL
737 * or max power settings.
738 */
739 { 4920, 4980, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0, 0 }, /* W1_4920_4980 */
740 { 5040, 5080, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0 }, /* W1_5040_5080 */
741 { 5170, 5230, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0, 0 }, /* W1_5170_5230 */
742 { 5180, 5240, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0, 0 }, /* W1_5180_5240 */
743 { 5260, 5320, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0, 0 }, /* W1_5260_5320 */
744 { 5745, 5825, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0, 0 }, /* W1_5745_5825 */
745 { 5500, 5700, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0, 0 }, /* W1_5500_5700 */
746 { 5260, 5320, 30, 0, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* W2_5260_5320 */
747 { 5180, 5240, 30, 0, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* W2_5180_5240 */
748 { 5825, 5825, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0, 0 }, /* W2_5825_5825 */
749 };
750 /*
751 * 5GHz Turbo (dynamic & static) tags
752 */
753
754 enum {
755 T1_5130_5210,
756 T1_5250_5330,
757 T1_5370_5490,
758 T1_5530_5650,
759
760 T1_5150_5190,
761 T1_5230_5310,
762 T1_5350_5470,
763 T1_5510_5670,
764
765 T1_5200_5240,
766 T2_5200_5240,
767 T1_5210_5210,
768 T2_5210_5210,
769
770 T1_5280_5280,
771 T2_5280_5280,
772 T1_5250_5250,
773 T1_5290_5290,
774 T1_5250_5290,
775 T2_5250_5290,
776
777 T1_5540_5660,
778 T1_5760_5800,
779 T2_5760_5800,
780
781 T1_5765_5805,
782
783 WT1_5210_5250,
784 WT1_5290_5290,
785 WT1_5540_5660,
786 WT1_5760_5800,
787 };
788
789 static REG_DMN_FREQ_BAND regDmn5GhzTurboFreq[] = {
790 { 5130, 5210, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T1_5130_5210 */
791 { 5250, 5330, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN, 0, 0}, /* T1_5250_5330 */
792 { 5370, 5490, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T1_5370_5490 */
793 { 5530, 5650, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN, 0, 0}, /* T1_5530_5650 */
794
795 { 5150, 5190, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T1_5150_5190 */
796 { 5230, 5310, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN, 0, 0}, /* T1_5230_5310 */
797 { 5350, 5470, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T1_5350_5470 */
798 { 5510, 5670, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN, 0, 0}, /* T1_5510_5670 */
799
800 { 5200, 5240, 17, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T1_5200_5240 */
801 { 5200, 5240, 23, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T2_5200_5240 */
802 { 5210, 5210, 17, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T1_5210_5210 */
803 { 5210, 5210, 23, 0, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T2_5210_5210 */
804
805 { 5280, 5280, 23, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0, 0}, /* T1_5280_5280 */
806 { 5280, 5280, 20, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0, 0}, /* T2_5280_5280 */
807 { 5250, 5250, 17, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0, 0}, /* T1_5250_5250 */
808 { 5290, 5290, 20, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0, 0}, /* T1_5290_5290 */
809 { 5250, 5290, 20, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0, 0}, /* T1_5250_5290 */
810 { 5250, 5290, 23, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0, 0}, /* T2_5250_5290 */
811
812 { 5540, 5660, 20, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0, 0}, /* T1_5540_5660 */
813 { 5760, 5800, 20, 0, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T1_5760_5800 */
814 { 5760, 5800, 30, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T2_5760_5800 */
815
816 { 5765, 5805, 30, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T1_5765_5805 */
817
818 /*
819 * Below are the WWR frequencies
820 */
821
822 { 5210, 5250, 15, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0, 0}, /* WT1_5210_5250 */
823 { 5290, 5290, 18, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0, 0}, /* WT1_5290_5290 */
824 { 5540, 5660, 20, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0, 0}, /* WT1_5540_5660 */
825 { 5760, 5800, 20, 0, 40, 40, NO_DFS, PSCAN_WWR, 0, 0}, /* WT1_5760_5800 */
826 };
827
828 /*
829 * 2GHz 11b channel tags
830 */
831 enum {
832 F1_2312_2372,
833 F2_2312_2372,
834
835 F1_2412_2472,
836 F2_2412_2472,
837 F3_2412_2472,
838
839 F1_2412_2462,
840 F2_2412_2462,
841
842 F1_2432_2442,
843
844 F1_2457_2472,
845
846 F1_2467_2472,
847
848 F1_2484_2484,
849 F2_2484_2484,
850
851 F1_2512_2732,
852
853 W1_2312_2372,
854 W1_2412_2412,
855 W1_2417_2432,
856 W1_2437_2442,
857 W1_2447_2457,
858 W1_2462_2462,
859 W1_2467_2467,
860 W2_2467_2467,
861 W1_2472_2472,
862 W2_2472_2472,
863 W1_2484_2484,
864 W2_2484_2484,
865 };
866
867 static REG_DMN_FREQ_BAND regDmn2GhzFreq[] = {
868 { 2312, 2372, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* F1_2312_2372 */
869 { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* F2_2312_2372 */
870
871 { 2412, 2472, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* F1_2412_2472 */
872 { 2412, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA, 0, 0}, /* F2_2412_2472 */
873 { 2412, 2472, 30, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* F3_2412_2472 */
874
875 { 2412, 2462, 27, 6, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* F1_2412_2462 */
876 { 2412, 2462, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA, 0, 0}, /* F2_2412_2462 */
877 { 2432, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* F1_2432_2442 */
878
879 { 2457, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* F1_2457_2472 */
880
881 { 2467, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA2 | PSCAN_MKKA, 0, 0}, /* F1_2467_2472 */
882
883 { 2484, 2484, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* F1_2484_2484 */
884 { 2484, 2484, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA | PSCAN_MKKA1 | PSCAN_MKKA2, 0, 0}, /* F2_2484_2484 */
885
886 { 2512, 2732, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* F1_2512_2732 */
887
888 /*
889 * WWR have powers opened up to 20dBm. Limits should often come from CTL/Max powers
890 */
891
892 { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* W1_2312_2372 */
893 { 2412, 2412, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* W1_2412_2412 */
894 { 2417, 2432, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* W1_2417_2432 */
895 { 2437, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* W1_2437_2442 */
896 { 2447, 2457, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* W1_2447_2457 */
897 { 2462, 2462, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* W1_2462_2462 */
898 { 2467, 2467, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0, 0}, /* W1_2467_2467 */
899 { 2467, 2467, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0, 0}, /* W2_2467_2467 */
900 { 2472, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0, 0}, /* W1_2472_2472 */
901 { 2472, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0, 0}, /* W2_2472_2472 */
902 { 2484, 2484, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0, 0}, /* W1_2484_2484 */
903 { 2484, 2484, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0, 0}, /* W2_2484_2484 */
904 };
905
906
907 /*
908 * 2GHz 11g channel tags
909 */
910
911 enum {
912 G1_2312_2372,
913 G2_2312_2372,
914
915 G1_2412_2472,
916 G2_2412_2472,
917 G3_2412_2472,
918
919 G1_2412_2462,
920 G2_2412_2462,
921
922 G1_2432_2442,
923
924 G1_2457_2472,
925
926 G1_2512_2732,
927
928 G1_2467_2472 ,
929
930 WG1_2312_2372,
931 WG1_2412_2412,
932 WG1_2417_2432,
933 WG1_2437_2442,
934 WG1_2447_2457,
935 WG1_2462_2462,
936 WG1_2467_2467,
937 WG2_2467_2467,
938 WG1_2472_2472,
939 WG2_2472_2472,
940
941 };
942 static REG_DMN_FREQ_BAND regDmn2Ghz11gFreq[] = {
943 { 2312, 2372, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* G1_2312_2372 */
944 { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* G2_2312_2372 */
945
946 { 2412, 2472, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* G1_2412_2472 */
947 { 2412, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA_G, 0, 0}, /* G2_2412_2472 */
948 { 2412, 2472, 30, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* G3_2412_2472 */
949
950 { 2412, 2462, 27, 6, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* G1_2412_2462 */
951 { 2412, 2462, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA_G, 0, 0}, /* G2_2412_2462 */
952 { 2432, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* G1_2432_2442 */
953
954 { 2457, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* G1_2457_2472 */
955
956 { 2512, 2732, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* G1_2512_2732 */
957
958 { 2467, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA2 | PSCAN_MKKA, 0, 0 }, /* G1_2467_2472 */
959
960 /*
961 * WWR open up the power to 20dBm
962 */
963
964 { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* WG1_2312_2372 */
965 { 2412, 2412, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* WG1_2412_2412 */
966 { 2417, 2432, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* WG1_2417_2432 */
967 { 2437, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* WG1_2437_2442 */
968 { 2447, 2457, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* WG1_2447_2457 */
969 { 2462, 2462, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* WG1_2462_2462 */
970 { 2467, 2467, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0, 0}, /* WG1_2467_2467 */
971 { 2467, 2467, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0, 0}, /* WG2_2467_2467 */
972 { 2472, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0, 0}, /* WG1_2472_2472 */
973 { 2472, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0, 0}, /* WG2_2472_2472 */
974 };
975 /*
976 * 2GHz Dynamic turbo tags
977 */
978
979 enum {
980 T1_2312_2372,
981 T1_2437_2437,
982 T2_2437_2437,
983 T3_2437_2437,
984 T1_2512_2732
985 };
986
987 static REG_DMN_FREQ_BAND regDmn2Ghz11gTurboFreq[] = {
988 { 2312, 2372, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T1_2312_2372 */
989 { 2437, 2437, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T1_2437_2437 */
990 { 2437, 2437, 20, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T2_2437_2437 */
991 { 2437, 2437, 18, 6, 40, 40, NO_DFS, PSCAN_WWR, 0, 0}, /* T3_2437_2437 */
992 { 2512, 2732, 5, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* T1_2512_2732 */
993 };
994
995
996
997 /*
998 * 2GHz 11n frequency tags
999 */
1000 enum {
1001 NG1_2422_2452,
1002 NG2_2422_2452,
1003 NG3_2422_2452,
1004
1005 NG_DEMO_ALL_CHANNELS,
1006 };
1007
1008 static REG_DMN_FREQ_BAND regDmn2Ghz11ngFreq[] = {
1009 { 2422, 2452, 20, 0, 40, 5, NO_DFS, NO_PSCAN, 0, 0}, /* NG1_2422_2452 */
1010 { 2422, 2452, 27, 0, 40, 5, NO_DFS, NO_PSCAN, 0, 0}, /* NG2_2422_2452 */
1011 { 2422, 2452, 30, 0, 40, 5, NO_DFS, NO_PSCAN, 0, 0}, /* NG3_2422_2452 */
1012
1013 { 2312, 2732, 27, 6, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* NG_DEMO_ALL_CHANNELS */
1014 };
1015
1016
1017 /*
1018 * 5GHz 11n frequency tags
1019 */
1020 enum {
1021 NA1_5190_5230,
1022 NA2_5190_5230,
1023 NA3_5190_5230,
1024 NA4_5190_5230,
1025 NA5_5190_5230,
1026
1027 NA1_5270_5270,
1028
1029 NA1_5270_5310,
1030 NA2_5270_5310,
1031 NA3_5270_5310,
1032 NA4_5270_5310,
1033
1034 NA1_5310_5310,
1035
1036 NA1_5510_5630,
1037
1038 NA1_5510_5670,
1039 NA2_5510_5670,
1040 NA3_5510_5670,
1041
1042 NA1_5755_5795,
1043 NA2_5755_5795,
1044 NA3_5755_5795,
1045 NA4_5755_5795,
1046 NA5_5755_5795,
1047
1048 NA1_5795_5795,
1049
1050 NA_DEMO_ALL_CHANNELS,
1051 };
1052
1053 static REG_DMN_FREQ_BAND regDmn5Ghz11naFreq[] = {
1054 /*
1055 * ToDo: This table needs to be completely populated with 5GHz 11n properties
1056 */
1057 { 5190, 5230, 15, 0, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* NA1_5190_5230 */
1058 { 5190, 5230, 17, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* NA2_5190_5230 */
1059 { 5190, 5230, 18, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* NA3_5190_5230 */
1060 { 5190, 5230, 20, 0, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* NA4_5190_5230 */
1061 { 5190, 5230, 23, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* NA5_5190_5230 */
1062
1063 { 5270, 5270, 23, 6, 40, 40, DFS_FCC3|DFS_ETSI, NO_PSCAN, 0, 1}, /* NA1_5270_5270 */
1064
1065 { 5270, 5310, 18, 6, 40, 40, DFS_FCC3|DFS_ETSI, NO_PSCAN, 0, 1}, /* NA1_5270_5310 */
1066 { 5270, 5310, 20, 0, 40, 40, DFS_FCC3|DFS_ETSI|DFS_MKK4, NO_PSCAN, 0, 1}, /* NA2_5270_5310 */
1067 { 5270, 5310, 23, 6, 40, 40, DFS_FCC3|DFS_ETSI, NO_PSCAN, 0, 1}, /* NA3_5270_5310 */
1068 { 5270, 5310, 30, 6, 40, 40, DFS_FCC3|DFS_ETSI, NO_PSCAN, 0, 1}, /* NA4_5270_5310 */
1069
1070 { 5310, 5310, 17, 6, 40, 40, DFS_FCC3|DFS_ETSI, NO_PSCAN, 0, 1}, /* NA1_5310_5310 */
1071
1072 { 5510, 5630, 30, 6, 40, 40, DFS_FCC3|DFS_ETSI, NO_PSCAN, 0, 1}, /* NA1_5510_5630 */
1073
1074 { 5510, 5670, 20, 6, 40, 40, DFS_FCC3|DFS_ETSI|DFS_MKK4, NO_PSCAN, 0, 1}, /* NA1_5510_5670 */
1075 { 5510, 5670, 27, 0, 40, 40, DFS_FCC3|DFS_ETSI, NO_PSCAN, 0, 1}, /* NA2_5510_5670 */
1076 { 5510, 5670, 30, 6, 40, 40, DFS_FCC3, NO_PSCAN, 0, 1}, /* NA3_5510_5670 */
1077
1078 { 5755, 5795, 17, 0, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* NA1_5755_5795 */
1079 { 5755, 5795, 20, 6, 40, 40, DFS_ETSI, NO_PSCAN, 0, 0}, /* NA2_5755_5795 */
1080 { 5755, 5795, 23, 0, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* NA3_5755_5795 */
1081 { 5755, 5795, 30, 0, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* NA4_5755_5795 */
1082 { 5755, 5795, 30, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* NA5_5755_5795 */
1083
1084 { 5795, 5795, 30, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* NA1_5795_5795 */
1085
1086 { 4920, 6100, 30, 6, 40, 40, NO_DFS, NO_PSCAN, 0, 0}, /* NA_DEMO_ALL_CHANNELS */
1087 };
1088
1089 typedef struct regDomain {
1090 u16_t regDmnEnum; /* value from EnumRd table */
1091 u8_t conformanceTestLimit;
1092 u64_t dfsMask; /* DFS bitmask for 5Ghz tables */
1093 u64_t pscan; /* Bitmask for passive scan */
1094 u32_t flags; /* Requirement flags (AdHoc disallow, noise
1095 floor cal needed, etc) */
1096 u64_t chan11a[BMLEN];/* 128 bit bitmask for channel/band
1097 selection */
1098 u64_t chan11a_turbo[BMLEN];/* 128 bit bitmask for channel/band
1099 selection */
1100 u64_t chan11a_dyn_turbo[BMLEN]; /* 128 bit bitmask for channel/band
1101 selection */
1102 u64_t chan11b[BMLEN];/* 128 bit bitmask for channel/band
1103 selection */
1104 u64_t chan11g[BMLEN];/* 128 bit bitmask for channel/band
1105 selection */
1106 u64_t chan11g_turbo[BMLEN];/* 128 bit bitmask for channel/band
1107 selection */
1108 u64_t chan11ng[BMLEN];/* 128 bit bitmask for 11n in 2GHz */
1109 u64_t chan11na[BMLEN];/* 128 bit bitmask for 11n in 5GHz */
1110 } REG_DOMAIN;
1111
1112 static REG_DOMAIN regDomains[] = {
1113
1114 {DEBUG_REG_DMN, FCC, NO_DFS, NO_PSCAN, NO_REQ,
1115 BM(F1_5120_5240, F1_5260_5700, F1_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1116 BM(T1_5130_5210, T1_5250_5330, T1_5370_5490, T1_5530_5650, T1_5150_5190, T1_5230_5310, T1_5350_5470, T1_5510_5670, -1, -1, -1, -1),
1117 BM(T1_5200_5240, T1_5280_5280, T1_5540_5660, T1_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1),
1118 BM(F1_2312_2372, F1_2412_2472, F1_2484_2484, F1_2512_2732, -1, -1, -1, -1, -1, -1, -1, -1),
1119 BM(G1_2312_2372, G1_2412_2472, G1_2512_2732, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1120 BM(T1_2312_2372, T1_2437_2437, T1_2512_2732, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1121 BM(NG_DEMO_ALL_CHANNELS, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1122 BM(NA_DEMO_ALL_CHANNELS, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1123
1124 {APL1, ETSI, NO_DFS, NO_PSCAN, NO_REQ,
1125 BM(F4_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1126 BMZERO,
1127 BMZERO,
1128 BMZERO,
1129 BMZERO,
1130 BMZERO,
1131 BMZERO,
1132 BM(NA4_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1133
1134 {APL2, ETSI, NO_DFS, NO_PSCAN, NO_REQ,
1135 BM(F1_5745_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1136 BMZERO,
1137 BMZERO,
1138 BMZERO,
1139 BMZERO,
1140 BMZERO,
1141 BMZERO,
1142 BM(NA3_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1143
1144 {APL3, FCC, NO_DFS, NO_PSCAN, NO_REQ,
1145 BM(F1_5280_5320, F2_5745_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1146 BMZERO,
1147 BMZERO,
1148 BMZERO,
1149 BMZERO,
1150 BMZERO,
1151 BMZERO,
1152 BM(NA1_5310_5310, NA4_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1153
1154 {APL4, ETSI, NO_DFS, NO_PSCAN, NO_REQ,
1155 BM(F4_5180_5240, F3_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1156 BMZERO,
1157 BMZERO,
1158 BMZERO,
1159 BMZERO,
1160 BMZERO,
1161 BMZERO,
1162 BM(NA4_5190_5230, NA2_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1163
1164 {APL5, ETSI, NO_DFS, NO_PSCAN, NO_REQ,
1165 BM(F2_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1166 BMZERO,
1167 BMZERO,
1168 BMZERO,
1169 BMZERO,
1170 BMZERO,
1171 BMZERO,
1172 BM(NA1_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1173
1174 {APL6, ETSI, DFS_ETSI, PSCAN_FCC_T | PSCAN_FCC , NO_REQ,
1175 BM(F4_5180_5240, F2_5260_5320, F3_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1176 BM(T2_5210_5210, T1_5250_5290, T1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1177 BMZERO,
1178 BMZERO,
1179 BMZERO,
1180 BMZERO,
1181 BMZERO,
1182 BM(NA4_5190_5230, NA2_5270_5310, NA2_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1183
1184 {APL7, FCC, NO_DFS, PSCAN_FCC_T | PSCAN_FCC , NO_REQ,
1185 BM(F7_5260_5320, F4_5500_5700, F3_5745_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1186 BMZERO,
1187 BMZERO,
1188 BMZERO,
1189 BMZERO,
1190 BMZERO,
1191 BMZERO,
1192 BM(NA1_5310_5310, NA2_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1193 {APL8, ETSI, NO_DFS, NO_PSCAN, DISALLOW_ADHOC_11A|DISALLOW_ADHOC_11A_TURB,
1194 BM(F6_5260_5320, F4_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1195 BMZERO,
1196 BMZERO,
1197 BMZERO,
1198 BMZERO,
1199 BMZERO,
1200 BMZERO,
1201 BM(NA4_5270_5310, NA4_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1202
1203 {APL9, ETSI, DFS_ETSI, PSCAN_ETSI, DISALLOW_ADHOC_11A|DISALLOW_ADHOC_11A_TURB,
1204 BM(F1_5180_5320, F1_5500_5620, F3_5745_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1205 BMZERO,
1206 BMZERO,
1207 BMZERO,
1208 BMZERO,
1209 BMZERO,
1210 BMZERO,
1211 BM(NA4_5190_5230, NA2_5270_5310, NA1_5510_5630, NA4_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1)},
1212
1213 {ETSI1, ETSI, DFS_ETSI, PSCAN_ETSI, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
1214 BM(W2_5180_5240, F2_5260_5320, F2_5500_5700, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1215 BMZERO,
1216 BMZERO,
1217 BMZERO,
1218 BMZERO,
1219 BMZERO,
1220 BMZERO,
1221 BM(NA4_5190_5230, NA2_5270_5310, NA2_5510_5670, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1222
1223 {ETSI2, ETSI, DFS_ETSI, PSCAN_ETSI, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
1224 BM(F3_5180_5240, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1225 BMZERO,
1226 BMZERO,
1227 BMZERO,
1228 BMZERO,
1229 BMZERO,
1230 BMZERO,
1231 BM(NA3_5190_5230, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1232
1233 {ETSI3, ETSI, DFS_ETSI, PSCAN_ETSI, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
1234 BM(W2_5180_5240, F2_5260_5320, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1235 BMZERO,
1236 BMZERO,
1237 BMZERO,
1238 BMZERO,
1239 BMZERO,
1240 BMZERO,
1241 BM(NA4_5190_5230, NA2_5270_5310, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1242
1243 {ETSI4, ETSI, DFS_ETSI, PSCAN_ETSI, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
1244 BM(F3_5180_5240, F1_5260_5320, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1245 BMZERO,
1246 BMZERO,
1247 BMZERO,
1248 BMZERO,
1249 BMZERO,
1250 BMZERO,
1251 BM(NA3_5190_5230, NA1_5270_5310, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1252
1253 {ETSI5, ETSI, DFS_ETSI, PSCAN_ETSI, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
1254 BM(F1_5180_5240, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1255 BMZERO,
1256 BMZERO,
1257 BMZERO,
1258 BMZERO,
1259 BMZERO,
1260 BMZERO,
1261 BM(NA1_5190_5230, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1262
1263 {ETSI6, ETSI, DFS_ETSI, PSCAN_ETSI, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
1264 BM(F5_5180_5240, F1_5260_5280, F3_5500_5700, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1265 BMZERO,
1266 BMZERO,
1267 BMZERO,
1268 BMZERO,
1269 BMZERO,
1270 BMZERO,
1271 BM(NA5_5190_5230, NA1_5270_5270, NA3_5510_5670, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1272
1273 {FCC1, FCC, NO_DFS, NO_PSCAN, NO_REQ,
1274 BM(F2_5180_5240, F4_5260_5320, F5_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1275 BM(T1_5210_5210, T2_5250_5290, T2_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1276 BM(T1_5200_5240, T1_5280_5280, T1_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1277 BMZERO,
1278 BMZERO,
1279 BMZERO,
1280 BMZERO,
1281 BM(NA2_5190_5230, NA3_5270_5310, NA4_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1282
1283 {FCC2, FCC, NO_DFS, NO_PSCAN, NO_REQ,
1284 BM(F6_5180_5240, F5_5260_5320, F6_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1285 BM(-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1286 BM(T2_5200_5240, T1_5280_5280, T1_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1287 BMZERO,
1288 BMZERO,
1289 BMZERO,
1290 BMZERO,
1291 BM(NA5_5190_5230, NA3_5270_5310, NA4_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1292
1293 {FCC3, FCC, DFS_FCC3, PSCAN_FCC | PSCAN_FCC_T, NO_REQ,
1294 BM(F2_5180_5240, F3_5260_5320, F1_5500_5700, F5_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1),
1295 BM(T1_5210_5210, T1_5250_5250, T1_5290_5290, T2_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1),
1296 BM(T1_5200_5240, T2_5280_5280, T1_5540_5660, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1297 BMZERO,
1298 BMZERO,
1299 BMZERO,
1300 BMZERO,
1301 BM(NA2_5190_5230, NA2_5270_5310, NA3_5510_5670, NA4_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1)},
1302
1303 {FCC4, FCC, DFS_FCC3, PSCAN_FCC | PSCAN_FCC_T, NO_REQ,
1304 BM(F1_4942_4987, F1_4945_4985, F1_4950_4980, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1305 BMZERO,
1306 BMZERO,
1307 BMZERO,
1308 BMZERO,
1309 BMZERO,
1310 BMZERO,
1311 BMZERO},
1312
1313 {FCC5, FCC, NO_DFS, NO_PSCAN, NO_REQ,
1314 BM(F2_5180_5240, F5_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1315 BMZERO,
1316 BMZERO,
1317 BMZERO,
1318 BMZERO,
1319 BMZERO,
1320 BMZERO,
1321 BM(NA2_5190_5230, NA4_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1322
1323 {FCC6, FCC, DFS_FCC3, PSCAN_FCC, NO_REQ,
1324 BM(F7_5180_5240, F5_5260_5320, F1_5500_5580, F1_5660_5700, F6_5745_5825, -1, -1, -1, -1, -1, -1, -1),
1325 BM(-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1326 BM(T2_5200_5240, T1_5280_5280, T1_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1327 BMZERO,
1328 BMZERO,
1329 BMZERO,
1330 BMZERO,
1331 BM(NA5_5190_5230, NA5_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1332
1333 {MKK1, MKK, NO_DFS, PSCAN_MKK1, DISALLOW_ADHOC_11A_TURB,
1334 BM(F1_5170_5230, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1335 BMZERO,
1336 BMZERO,
1337 BMZERO,
1338 BMZERO,
1339 BMZERO,
1340 BMZERO,
1341 BMZERO},
1342
1343 {MKK2, MKK, NO_DFS, PSCAN_MKK2, DISALLOW_ADHOC_11A_TURB,
1344 BM(F1_4915_4925, F1_4935_4945, F1_4920_4980, F1_5035_5040, F1_5055_5055, F1_5040_5080, F1_5170_5230, -1, -1, -1, -1, -1),
1345 BMZERO,
1346 BMZERO,
1347 BMZERO,
1348 BMZERO,
1349 BMZERO,
1350 BMZERO,
1351 BMZERO},
1352
1353 /* UNI-1 even */
1354 {MKK3, MKK, NO_DFS, PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB,
1355 BM(F4_5180_5240, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1356 BMZERO,
1357 BMZERO,
1358 BMZERO,
1359 BMZERO,
1360 BMZERO,
1361 BMZERO,
1362 BM(NA4_5190_5230, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1363
1364 /* UNI-1 even + UNI-2 */
1365 {MKK4, MKK, DFS_MKK4, PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB,
1366 BM(F4_5180_5240, F2_5260_5320, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1367 BMZERO,
1368 BMZERO,
1369 BMZERO,
1370 BMZERO,
1371 BMZERO,
1372 BMZERO,
1373 BM(NA4_5190_5230, NA2_5270_5310, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1374
1375 /* UNI-1 even + UNI-2 + mid-band */
1376 {MKK5, MKK, DFS_MKK4, PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB,
1377 BM(F4_5180_5240, F2_5260_5320, F4_5500_5700, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1378 BMZERO,
1379 BMZERO,
1380 BMZERO,
1381 BMZERO,
1382 BMZERO,
1383 BMZERO,
1384 BM(NA4_5190_5230, NA2_5270_5310, NA1_5510_5670, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1385
1386 /* UNI-1 odd + even */
1387 {MKK6, MKK, DFS_MKK4, PSCAN_MKK1, DISALLOW_ADHOC_11A_TURB,
1388 BM(F2_5170_5230, F4_5180_5240, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1389 BMZERO,
1390 BMZERO,
1391 BMZERO,
1392 BMZERO,
1393 BMZERO,
1394 BMZERO,
1395 BM(NA4_5190_5230, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1396
1397 /* UNI-1 odd + UNI-1 even + UNI-2 */
1398 {MKK7, MKK, DFS_MKK4, PSCAN_MKK1 | PSCAN_MKK3 , DISALLOW_ADHOC_11A_TURB,
1399 BM(F2_5170_5230, F4_5180_5240, F2_5260_5320, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1400 BMZERO,
1401 BMZERO,
1402 BMZERO,
1403 BMZERO,
1404 BMZERO,
1405 BMZERO,
1406 BM(NA4_5190_5230, NA2_5270_5310, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1407
1408 /* UNI-1 odd + UNI-1 even + UNI-2 + mid-band */
1409 {MKK8, MKK, DFS_MKK4, PSCAN_MKK1 | PSCAN_MKK3 , DISALLOW_ADHOC_11A_TURB,
1410 BM(F2_5170_5230, F4_5180_5240, F2_5260_5320, F4_5500_5700, -1, -1, -1, -1, -1, -1, -1, -1),
1411 BMZERO,
1412 BMZERO,
1413 BMZERO,
1414 BMZERO,
1415 BMZERO,
1416 BMZERO,
1417 BM(NA4_5190_5230, NA2_5270_5310, NA1_5510_5670, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1418
1419 /* UNI-1 even + 4.9 GHZ */
1420 {MKK9, MKK, NO_DFS, NO_PSCAN, DISALLOW_ADHOC_11A_TURB,
1421 BM(F1_4915_4925, F1_4935_4945, F1_4920_4980, F1_5035_5040, F1_5055_5055, F1_5040_5080, F4_5180_5240, -1, -1, -1, -1, -1),
1422 BMZERO,
1423 BMZERO,
1424 BMZERO,
1425 BMZERO,
1426 BMZERO,
1427 BMZERO,
1428 BMZERO},
1429
1430 /* UNI-1 even + UNI-2 + 4.9 GHZ */
1431 {MKK10, MKK, DFS_MKK4, PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB,
1432 BM(F1_4915_4925, F1_4935_4945, F1_4920_4980, F1_5035_5040, F1_5055_5055, F1_5040_5080, F4_5180_5240, F2_5260_5320, -1, -1, -1, -1),
1433 BMZERO,
1434 BMZERO,
1435 BMZERO,
1436 BMZERO,
1437 BMZERO,
1438 BMZERO,
1439 BMZERO},
1440
1441 /* UNI-1 even + UNI-2 + 4.9 GHZ + mid-band */
1442 {MKK11, MKK, DFS_MKK4, PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB,
1443 BM(F1_4915_4925, F1_4935_4945, F1_4920_4980, F1_5035_5040, F1_5055_5055, F1_5040_5080, F4_5180_5240, F2_5260_5320, F4_5500_5700, -1, -1, -1),
1444 BMZERO,
1445 BMZERO,
1446 BMZERO,
1447 BMZERO,
1448 BMZERO,
1449 BMZERO,
1450 BMZERO},
1451
1452 /* UNI-1 even + UNI-1 odd + UNI-2 + 4.9 GHZ + mid-band */
1453 {MKK12, MKK, DFS_MKK4, PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB,
1454 BM(F1_4915_4925, F1_4935_4945, F1_4920_4980, F1_5035_5040, F1_5055_5055, F1_5040_5080, F1_5170_5230, F4_5180_5240, F2_5260_5320, F4_5500_5700, -1, -1),
1455 BMZERO,
1456 BMZERO,
1457 BMZERO,
1458 BMZERO,
1459 BMZERO,
1460 BMZERO,
1461 BMZERO},
1462
1463 /* Defined here to use when 2G channels are authorised for country K2 */
1464 {APLD, NO_CTL, NO_DFS, NO_PSCAN, NO_REQ,
1465 BMZERO,
1466 BMZERO,
1467 BMZERO,
1468 BM(F2_2312_2372,F2_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1469 BM(G2_2312_2372,G2_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1470 BMZERO,
1471 BMZERO,
1472 BMZERO},
1473
1474 {ETSIA, NO_CTL, NO_DFS, PSCAN_ETSIA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
1475 BMZERO,
1476 BMZERO,
1477 BMZERO,
1478 BM(F1_2457_2472,-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1479 BM(G1_2457_2472,-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1480 BM(T2_2437_2437,-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1481 BMZERO,
1482 BMZERO},
1483
1484 {ETSIB, ETSI, NO_DFS, PSCAN_ETSIB, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
1485 BMZERO,
1486 BMZERO,
1487 BMZERO,
1488 BM(F1_2432_2442,-1,-1,-1,-1,-1,-1,-1, -1, -1, -1, -1),
1489 BM(G1_2432_2442,-1,-1,-1,-1,-1,-1,-1, -1, -1, -1, -1),
1490 BM(T2_2437_2437,-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1491 BMZERO,
1492 BMZERO},
1493
1494 {ETSIC, ETSI, NO_DFS, PSCAN_ETSIC, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
1495 BMZERO,
1496 BMZERO,
1497 BMZERO,
1498 BM(F3_2412_2472,-1,-1,-1,-1,-1,-1,-1, -1, -1, -1, -1),
1499 BM(G3_2412_2472,-1,-1,-1,-1,-1,-1,-1, -1, -1, -1, -1),
1500 BM(T2_2437_2437,-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1501 BMZERO,
1502 BMZERO},
1503
1504 {FCCA, FCC, NO_DFS, NO_PSCAN, NO_REQ,
1505 BMZERO,
1506 BMZERO,
1507 BMZERO,
1508 BM(F1_2412_2462,-1,-1,-1,-1,-1,-1,-1, -1, -1, -1, -1),
1509 BM(G1_2412_2462,-1,-1,-1,-1,-1,-1,-1, -1, -1, -1, -1),
1510 BM(T2_2437_2437,-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1511 BM(NG2_2422_2452,-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1512 BMZERO},
1513
1514 {MKKA, MKK, NO_DFS, PSCAN_MKKA | PSCAN_MKKA_G | PSCAN_MKKA1 | PSCAN_MKKA1_G | PSCAN_MKKA2 | PSCAN_MKKA2_G, DISALLOW_ADHOC_11A_TURB,
1515 BMZERO,
1516 BMZERO,
1517 BMZERO,
1518 BM(F2_2412_2462, F1_2467_2472, F2_2484_2484, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1519 BM(G2_2412_2462, G1_2467_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1520 BM(T2_2437_2437,-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1521 BM(NG1_2422_2452,-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1522 BMZERO},
1523
1524 {MKKC, MKK, NO_DFS, NO_PSCAN, NO_REQ,
1525 BMZERO,
1526 BMZERO,
1527 BMZERO,
1528 BM(F2_2412_2472,-1,-1,-1,-1,-1,-1,-1, -1, -1, -1, -1),
1529 BM(G2_2412_2472,-1,-1,-1,-1,-1,-1,-1, -1, -1, -1, -1),
1530 BM(T2_2437_2437,-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1531 BM(NG1_2422_2452,-1,-1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1532 BMZERO},
1533
1534 {WORLD, ETSI, NO_DFS, NO_PSCAN, NO_REQ,
1535 BMZERO,
1536 BMZERO,
1537 BMZERO,
1538 BM(F2_2412_2472,-1,-1,-1,-1,-1,-1,-1, -1, -1, -1, -1),
1539 BM(G2_2412_2472,-1,-1,-1,-1,-1,-1,-1, -1, -1, -1, -1),
1540 BM(T2_2437_2437,-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1541 BM(NG1_2422_2452,-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1542 BMZERO},
1543
1544 {WOR0_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_PER_11D,
1545 BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, W1_5500_5700, -1, -1, -1, -1, -1, -1, -1),
1546 BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1547 BMZERO,
1548 BM(W1_2412_2412,W1_2437_2442,W1_2462_2462,W1_2472_2472,W1_2417_2432, W1_2447_2457, W1_2467_2467, W1_2484_2484, -1, -1, -1, -1),
1549 BM(WG1_2412_2412,WG1_2437_2442,WG1_2462_2462,WG1_2472_2472,WG1_2417_2432,WG1_2447_2457,WG1_2467_2467, -1, -1, -1, -1, -1),
1550 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1551 BMZERO,
1552 BMZERO},
1553
1554 {WOR01_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_PER_11D,
1555 BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, W1_5500_5700, -1, -1, -1, -1, -1, -1, -1),
1556 BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1557 BMZERO,
1558 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2417_2432, W1_2447_2457, -1, -1, -1, -1, -1, -1, -1),
1559 BM(WG1_2412_2412, WG1_2437_2442, WG1_2462_2462, WG1_2417_2432, WG1_2447_2457, -1, -1, -1, -1, -1, -1, -1),
1560 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1561 BMZERO,
1562 BMZERO},
1563
1564 {WOR02_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_PER_11D,
1565 BM(W1_5260_5320, W1_5180_5240,W1_5170_5230,W1_5745_5825,W1_5500_5700, -1, -1, -1, -1, -1, -1, -1),
1566 BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1567 BMZERO,
1568 BM(W1_2412_2412,W1_2437_2442,W1_2462_2462, W1_2472_2472,W1_2417_2432, W1_2447_2457, W1_2467_2467, -1, -1, -1, -1, -1),
1569 BM(WG1_2412_2412,WG1_2437_2442,WG1_2462_2462, WG1_2472_2472,WG1_2417_2432, WG1_2447_2457, WG1_2467_2467, -1, -1, -1, -1, -1),
1570 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1571 BMZERO,
1572 BMZERO},
1573
1574 {EU1_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_PER_11D,
1575 BM(W1_5260_5320, W1_5180_5240,W1_5170_5230,W1_5745_5825,W1_5500_5700, -1, -1, -1, -1, -1, -1, -1),
1576 BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1577 BMZERO,
1578 BM(W1_2412_2412,W1_2437_2442,W1_2462_2462, W2_2472_2472,W1_2417_2432, W1_2447_2457, W2_2467_2467, -1, -1, -1, -1, -1),
1579 BM(WG1_2412_2412,WG1_2437_2442,WG1_2462_2462, WG2_2472_2472,WG1_2417_2432, WG1_2447_2457, WG2_2467_2467, -1, -1, -1, -1, -1),
1580 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1581 BMZERO,
1582 BMZERO},
1583
1584 {WOR1_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A,
1585 BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, W1_5500_5700, -1, -1, -1, -1, -1, -1, -1),
1586 BMZERO,
1587 BMZERO,
1588 BM(W1_2412_2412,W1_2437_2442,W1_2462_2462,W1_2472_2472,W1_2417_2432, W1_2447_2457, W1_2467_2467, W1_2484_2484, -1, -1, -1, -1),
1589 BM(WG1_2412_2412,WG1_2437_2442,WG1_2462_2462,WG1_2472_2472,WG1_2417_2432,WG1_2447_2457,WG1_2467_2467, -1, -1, -1, -1, -1),
1590 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1591 BMZERO,
1592 BMZERO},
1593
1594 {WOR2_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A,
1595 BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, W1_5500_5700, -1, -1, -1, -1, -1, -1, -1),
1596 BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1597 BMZERO,
1598 BM(W1_2412_2412,W1_2437_2442,W1_2462_2462,W1_2472_2472,W1_2417_2432, W1_2447_2457, W1_2467_2467, W1_2484_2484, -1, -1, -1, -1),
1599 BM(WG1_2412_2412,WG1_2437_2442,WG1_2462_2462,WG1_2472_2472,WG1_2417_2432,WG1_2447_2457,WG1_2467_2467, -1, -1, -1, -1, -1),
1600 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1601 BMZERO,
1602 BMZERO},
1603
1604 {WOR3_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_PER_11D,
1605 BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1),
1606 BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1607 BMZERO,
1608 BM(W1_2412_2412,W1_2437_2442,W1_2462_2462,W1_2472_2472,W1_2417_2432, W1_2447_2457, W1_2467_2467, -1, -1, -1, -1, -1),
1609 BM(WG1_2412_2412,WG1_2437_2442,WG1_2462_2462,WG1_2472_2472,WG1_2417_2432,WG1_2447_2457,WG1_2467_2467,-1, -1, -1, -1, -1),
1610 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1611 BMZERO,
1612 BMZERO},
1613
1614 {WOR4_WORLD, NO_CTL, DFS_FCC3, PSCAN_WWR, ADHOC_NO_11A,
1615 BM(W2_5260_5320, W2_5180_5240, F2_5745_5805, W2_5825_5825, -1, -1, -1, -1, -1, -1, -1, -1),
1616 BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1617 BMZERO,
1618 BM(W1_2412_2412,W1_2437_2442,W1_2462_2462, W1_2417_2432,W1_2447_2457,-1, -1, -1, -1, -1, -1, -1),
1619 BM(WG1_2412_2412,WG1_2437_2442,WG1_2462_2462, WG1_2417_2432,WG1_2447_2457,-1, -1, -1, -1, -1, -1, -1),
1620 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1621 BMZERO,
1622 BMZERO},
1623
1624 {WOR5_ETSIC, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A,
1625 BM(W1_5260_5320, W2_5180_5240, F6_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1626 BMZERO,
1627 BMZERO,
1628 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W2_2472_2472, W1_2417_2432, W1_2447_2457, W2_2467_2467, -1, -1, -1, -1, -1),
1629 BM(WG1_2412_2412, WG1_2437_2442, WG1_2462_2462, WG1_2472_2472, WG1_2417_2432, WG1_2447_2457, WG1_2467_2467, -1, -1, -1, -1, -1),
1630 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1631 BMZERO,
1632 BMZERO},
1633
1634 {WOR9_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A,
1635 BM(W1_5260_5320, W1_5180_5240, W1_5745_5825, W1_5500_5700, -1, -1, -1, -1, -1, -1, -1, -1),
1636 BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1637 BMZERO,
1638 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2417_2432, W1_2447_2457, -1, -1, -1, -1, -1, -1, -1),
1639 BM(WG1_2412_2412, WG1_2437_2442, WG1_2462_2462, WG1_2417_2432, WG1_2447_2457, -1, -1, -1, -1, -1, -1, -1),
1640 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1641 BMZERO,
1642 BMZERO},
1643
1644 {WORA_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A,
1645 BM(W1_5260_5320, W1_5180_5240, W1_5745_5825, W1_5500_5700, -1, -1, -1, -1, -1, -1, -1, -1),
1646 BMZERO,
1647 BMZERO,
1648 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472, W1_2417_2432, W1_2447_2457, W1_2467_2467, -1, -1, -1, -1, -1),
1649 BM(WG1_2412_2412, WG1_2437_2442, WG1_2462_2462, WG1_2472_2472, WG1_2417_2432, WG1_2447_2457, WG1_2467_2467, -1, -1, -1, -1, -1),
1650 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1651 BMZERO,
1652 BMZERO},
1653
1654 {NULL1, NO_CTL, NO_DFS, NO_PSCAN, NO_REQ,
1655 BMZERO,
1656 BMZERO,
1657 BMZERO,
1658 BMZERO,
1659 BMZERO,
1660 BMZERO,
1661 BMZERO,
1662 BMZERO},
1663 };
1664
1665 struct cmode {
1666 u16_t mode;
1667 u32_t flags;
1668 };
1669
1670 static const struct cmode modes[] = {
1671 { HAL_MODE_TURBO, CHANNEL_ST}, /* TURBO means 11a Static Turbo */
1672 { HAL_MODE_11A, CHANNEL_A},
1673 { HAL_MODE_11B, CHANNEL_B},
1674 { HAL_MODE_11G, CHANNEL_G},
1675 { HAL_MODE_11G_TURBO, CHANNEL_108G},
1676 { HAL_MODE_11A_TURBO, CHANNEL_108A},
1677 { HAL_MODE_11NA, CHANNEL_A_HT40},
1678 { HAL_MODE_11NA, CHANNEL_A_HT20},
1679 { HAL_MODE_11NG, CHANNEL_G_HT40},
1680 { HAL_MODE_11NG, CHANNEL_G_HT20},
1681 };
1682
1683 /*
1684 * Return the Wireless Mode Regulatory Domain based
1685 * on the country code and the wireless mode.
1686 */
1687 u8_t GetWmRD(u16_t regionCode, u16_t channelFlag, REG_DOMAIN *rd)
1688 {
1689 s16_t i, found, regDmn;
1690 u64_t flags=NO_REQ;
1691 REG_DMN_PAIR_MAPPING *regPair=NULL;
1692
1693 for (i=0, found=0; (i<N(regDomainPairs))&&(!found); i++)
1694 {
1695 if (regDomainPairs[i].regDmnEnum == regionCode)
1696 {
1697 regPair = &regDomainPairs[i];
1698 found = 1;
1699 }
1700 }
1701 if (!found)
1702 {
1703 zm_debug_msg1("Failed to find reg domain pair ", regionCode);
1704 return FALSE;
1705 }
1706
1707 if (channelFlag & ZM_REG_FLAG_CHANNEL_2GHZ)
1708 {
1709 regDmn = regPair->regDmn2GHz;
1710 flags = regPair->flags2GHz;
1711 }
1712 else
1713 {
1714 regDmn = regPair->regDmn5GHz;
1715 flags = regPair->flags5GHz;
1716 }
1717
1718 /*
1719 * We either started with a unitary reg domain or we've found the
1720 * unitary reg domain of the pair
1721 */
1722
1723 for (i=0;i<N(regDomains); i++)
1724 {
1725 if (regDomains[i].regDmnEnum == regDmn)
1726 {
1727 if (rd != NULL)
1728 {
1729 zfMemoryCopy((u8_t *)rd, (u8_t *)&regDomains[i],
1730 sizeof(REG_DOMAIN));
1731 }
1732 }
1733 }
1734 rd->pscan &= regPair->pscanMask;
1735 rd->flags = (u32_t)flags;
1736 return TRUE;
1737 }
1738
1739 /*
1740 * Test to see if the bitmask array is all zeros
1741 */
1742 u8_t isChanBitMaskZero(u64_t *bitmask)
1743 {
1744 u16_t i;
1745
1746 for (i=0; i<BMLEN; i++) {
1747 if (bitmask[i] != 0)
1748 return FALSE;
1749 }
1750 return TRUE;
1751 }
1752
1753 u8_t IS_BIT_SET(u32_t bit, u64_t *bitmask)
1754 {
1755 u32_t byteOffset, bitnum;
1756 u64_t val;
1757
1758 byteOffset = bit/64;
1759 bitnum = bit - byteOffset*64;
1760 val = ((u64_t) 1) << bitnum;
1761 if (bitmask[byteOffset] & val)
1762 return TRUE;
1763 else
1764 return FALSE;
1765 }
1766
1767
1768 void zfHpGetRegulationTable(zdev_t* dev, u16_t regionCode, u16_t c_lo, u16_t c_hi)
1769 {
1770 REG_DOMAIN rd5GHz, rd2GHz;
1771 const struct cmode *cm;
1772 s16_t next=0,b;
1773 struct zsHpPriv* hpPriv;
1774
1775 zmw_get_wlan_dev(dev);
1776 hpPriv=wd->hpPrivate;
1777
1778 zmw_declare_for_critical_section();
1779
1780 if (!GetWmRD(regionCode, ~ZM_REG_FLAG_CHANNEL_2GHZ, &rd5GHz))
1781 {
1782 zm_debug_msg1("couldn't find unitary 5GHz reg domain for Region Code ", regionCode);
1783 return;
1784 }
1785 if (!GetWmRD(regionCode, ZM_REG_FLAG_CHANNEL_2GHZ, &rd2GHz))
1786 {
1787 zm_debug_msg1("couldn't find unitary 2GHz reg domain for Region Code ", regionCode);
1788 return;
1789 }
1790 if (wd->regulationTable.regionCode == regionCode)
1791 {
1792 zm_debug_msg1("current region code is the same with Region Code ", regionCode);
1793 return;
1794 }
1795 else
1796 {
1797 wd->regulationTable.regionCode = regionCode;
1798 }
1799
1800 next = 0;
1801
1802 zmw_enter_critical_section(dev);
1803
1804 for (cm = modes; cm < &modes[N(modes)]; cm++)
1805 {
1806 u16_t c;
1807 u64_t *channelBM=NULL;
1808 REG_DOMAIN *rd=NULL;
1809 REG_DMN_FREQ_BAND *fband=NULL,*freqs=NULL;
1810
1811 switch (cm->mode)
1812 {
1813 case HAL_MODE_TURBO:
1814 //we don't have turbo mode so we disable it
1815 //zm_debug_msg0("CWY - HAL_MODE_TURBO");
1816 channelBM = NULL;
1817 //rd = &rd5GHz;
1818 //channelBM = rd->chan11a_turbo;
1819 //freqs = &regDmn5GhzTurboFreq[0];
1820 //ctl = rd->conformanceTestLimit | CTL_TURBO;
1821 break;
1822 case HAL_MODE_11A:
1823 if ((hpPriv->OpFlags & 0x1) != 0)
1824 {
1825 rd = &rd5GHz;
1826 channelBM = rd->chan11a;
1827 freqs = &regDmn5GhzFreq[0];
1828 c_lo = 4920; //from channel 184
1829 c_hi = 5825; //to channel 165
1830 //ctl = rd->conformanceTestLimit;
1831 //zm_debug_msg2("CWY - HAL_MODE_11A, channelBM = 0x", *channelBM);
1832 }
1833 //else
1834 {
1835 //channelBM = NULL;
1836 }
1837 break;
1838 case HAL_MODE_11B:
1839 //Disable 11B mode because it only has difference with 11G in PowerDFS Data,
1840 //and we don't use this now.
1841 //zm_debug_msg0("CWY - HAL_MODE_11B");
1842 channelBM = NULL;
1843 //rd = &rd2GHz;
1844 //channelBM = rd->chan11b;
1845 //freqs = &regDmn2GhzFreq[0];
1846 //ctl = rd->conformanceTestLimit | CTL_11B;
1847 //zm_debug_msg2("CWY - HAL_MODE_11B, channelBM = 0x", *channelBM);
1848 break;
1849 case HAL_MODE_11G:
1850 if ((hpPriv->OpFlags & 0x2) != 0)
1851 {
1852 rd = &rd2GHz;
1853 channelBM = rd->chan11g;
1854 freqs = &regDmn2Ghz11gFreq[0];
1855 c_lo = 2412; //from channel 1
1856 //c_hi = 2462; //to channel 11
1857 c_hi = 2472; //to channel 13
1858 //ctl = rd->conformanceTestLimit | CTL_11G;
1859 //zm_debug_msg2("CWY - HAL_MODE_11G, channelBM = 0x", *channelBM);
1860 }
1861 //else
1862 {
1863 //channelBM = NULL;
1864 }
1865 break;
1866 case HAL_MODE_11G_TURBO:
1867 //we don't have turbo mode so we disable it
1868 //zm_debug_msg0("CWY - HAL_MODE_11G_TURBO");
1869 channelBM = NULL;
1870 //rd = &rd2GHz;
1871 //channelBM = rd->chan11g_turbo;
1872 //freqs = &regDmn2Ghz11gTurboFreq[0];
1873 //ctl = rd->conformanceTestLimit | CTL_108G;
1874 break;
1875 case HAL_MODE_11A_TURBO:
1876 //we don't have turbo mode so we disable it
1877 //zm_debug_msg0("CWY - HAL_MODE_11A_TURBO");
1878 channelBM = NULL;
1879 //rd = &rd5GHz;
1880 //channelBM = rd->chan11a_dyn_turbo;
1881 //freqs = &regDmn5GhzTurboFreq[0];
1882 //ctl = rd->conformanceTestLimit | CTL_108G;
1883 break;
1884 default:
1885 zm_debug_msg1("Unkonwn HAL mode ", cm->mode);
1886 continue;
1887 }
1888 if (channelBM == NULL)
1889 {
1890 //zm_debug_msg0("CWY - channelBM is NULL");
1891 continue;
1892 }
1893 if (isChanBitMaskZero(channelBM))
1894 {
1895 //zm_debug_msg0("CWY - BitMask is Zero");
1896 continue;
1897 }
1898
1899 // RAY:Is it ok??
1900 if (freqs == NULL )
1901 {
1902 continue;
1903 }
1904
1905 for (b=0;b<64*BMLEN; b++)
1906 {
1907 if (IS_BIT_SET(b,channelBM))
1908 {
1909 fband = &freqs[b];
1910
1911 //zm_debug_msg1("CWY - lowChannel = ", fband->lowChannel);
1912 //zm_debug_msg1("CWY - highChannel = ", fband->highChannel);
1913 //zm_debug_msg1("CWY - channelSep = ", fband->channelSep);
1914 for (c=fband->lowChannel; c <= fband->highChannel;
1915 c += fband->channelSep)
1916 {
1917 ZM_HAL_CHANNEL icv;
1918
1919 //Disable all DFS channel
1920 if ((hpPriv->disableDfsCh==0) || (!(fband->useDfs & rd->dfsMask)))
1921 {
1922 if( fband->channelBW < 20 )
1923 {
1924 /**************************************************************/
1925 /* */
1926 /* Temporary discard channel that BW < 20MHz (5 or 10MHz) */
1927 /* Our architecture does not implemnt it !!! */
1928 /* */
1929 /**************************************************************/
1930 continue;
1931 }
1932 if ((c >= c_lo) && (c <= c_hi))
1933 {
1934 icv.channel = c;
1935 icv.channelFlags = cm->flags;
1936 icv.maxRegTxPower = fband->powerDfs;
1937 if (fband->usePassScan & rd->pscan)
1938 icv.channelFlags |= ZM_REG_FLAG_CHANNEL_PASSIVE;
1939 else
1940 icv.channelFlags &= ~ZM_REG_FLAG_CHANNEL_PASSIVE;
1941 if (fband->useDfs & rd->dfsMask)
1942 icv.privFlags = ZM_REG_FLAG_CHANNEL_DFS;
1943 else
1944 icv.privFlags = 0;
1945
1946 /* For now disable radar for FCC3 */
1947 if (fband->useDfs & rd->dfsMask & DFS_FCC3)
1948 {
1949 icv.privFlags &= ~ZM_REG_FLAG_CHANNEL_DFS;
1950 icv.privFlags |= ZM_REG_FLAG_CHANNEL_DFS_CLEAR;
1951 }
1952
1953 if(rd->flags & LIMIT_FRAME_4MS)
1954 icv.privFlags |= ZM_REG_FLAG_CHANNEL_DFS_CLEAR;
1955
1956 icv.minTxPower = 0;
1957 icv.maxTxPower = 0;
1958
1959 zm_assert(next < 60);
1960
1961 wd->regulationTable.allowChannel[next++] = icv;
1962 }
1963 }
1964 }
1965 }
1966 }
1967 }
1968 wd->regulationTable.allowChannelCnt = next;
1969
1970 #if 0
1971 {
1972 /* debug print */
1973 u32_t i;
1974 DbgPrint("\n-------------------------------------------\n");
1975 DbgPrint("zfHpGetRegulationTable print all channel info regincode = 0x%x\n", wd->regulationTable.regionCode);
1976 DbgPrint("index channel channelFlags maxRegTxPower privFlags useDFS\n");
1977
1978 for (i=0; i<wd->regulationTable.allowChannelCnt; i++)
1979 {
1980 DbgPrint("%02d %d %04x %02d %x %x\n",
1981 i,
1982 wd->regulationTable.allowChannel[i].channel,
1983 wd->regulationTable.allowChannel[i].channelFlags,
1984 wd->regulationTable.allowChannel[i].maxRegTxPower,
1985 wd->regulationTable.allowChannel[i].privFlags,
1986 wd->regulationTable.allowChannel[i].privFlags & ZM_REG_FLAG_CHANNEL_DFS);
1987 }
1988 }
1989 #endif
1990
1991 zmw_leave_critical_section(dev);
1992 }
1993
1994 void zfHpGetRegulationTablefromRegionCode(zdev_t* dev, u16_t regionCode)
1995 {
1996 u16_t c_lo = 2000, c_hi = 6000; //default channel is all enable
1997 u8_t isoName[3] = {'N', 'A', 0};
1998
1999 zfCoreSetIsoName(dev, isoName);
2000
2001 zfHpGetRegulationTable(dev, regionCode, c_lo, c_hi);
2002 }
2003
2004 void zfHpGetRegulationTablefromCountry(zdev_t* dev, u16_t CountryCode)
2005 {
2006 u16_t i;
2007 u16_t c_lo = 2000, c_hi = 6000; //default channel is all enable
2008 u16_t RegDomain;
2009
2010 zmw_get_wlan_dev(dev);
2011
2012 zmw_declare_for_critical_section();
2013
2014 for (i = 0; i < N(allCountries); i++)
2015 {
2016 if (CountryCode == allCountries[i].countryCode)
2017 {
2018 RegDomain = allCountries[i].regDmnEnum;
2019
2020 // read the ACU country code from EEPROM
2021 zfCoreSetIsoName(dev, (u8_t*)allCountries[i].isoName);
2022
2023 //zm_debug_msg_s("CWY - Country Name = ", allCountries[i].name);
2024
2025 if (wd->regulationTable.regionCode != RegDomain)
2026 {
2027 //zm_debug_msg0("CWY - Change regulatory table");
2028
2029 zfHpGetRegulationTable(dev, RegDomain, c_lo, c_hi);
2030 }
2031 return;
2032 }
2033 }
2034 zm_debug_msg1("Invalid CountryCode = ", CountryCode);
2035 }
2036
2037 u8_t zfHpGetRegulationTablefromISO(zdev_t* dev, u8_t *countryInfo, u8_t length)
2038 {
2039 u16_t i;
2040 u16_t RegDomain;
2041 u16_t c_lo = 2000, c_hi = 6000; //default channel is all enable
2042 //u8_t strLen = 2;
2043
2044 zmw_get_wlan_dev(dev);
2045
2046 zmw_declare_for_critical_section();
2047
2048 if (countryInfo[4] != 0x20)
2049 { // with (I)ndoor/(O)utdoor info
2050 //strLen = 3;
2051 }
2052 //zm_debug_msg_s("Desired iso name = ", isoName);
2053 for (i = 0; i < N(allCountries); i++)
2054 {
2055 //zm_debug_msg_s("Current iso name = ", allCountries[i].isoName);
2056 if (zfMemoryIsEqual((u8_t *)allCountries[i].isoName, (u8_t *)&countryInfo[2], length-1))
2057 {
2058 //DbgPrint("Set current iso name = %s\n", allCountries[i].isoName);
2059 //zm_debug_msg0("iso name hit!!");
2060
2061 RegDomain = allCountries[i].regDmnEnum;
2062
2063 if (wd->regulationTable.regionCode != RegDomain)
2064 {
2065 zfHpGetRegulationTable(dev, RegDomain, c_lo, c_hi);
2066 }
2067
2068 //while (index < (countryInfo[1]+2))
2069 //{
2070 // if (countryInfo[index] <= 14)
2071 // {
2072 // /* calculate 2.4GHz low boundary channel frequency */
2073 // ch = countryInfo[index];
2074 // if ( ch == 14 )
2075 // c_lo = ZM_CH_G_14;
2076 // else
2077 // c_lo = ZM_CH_G_1 + (ch - 1) * 5;
2078 // /* calculate 2.4GHz high boundary channel frequency */
2079 // ch = countryInfo[index] + countryInfo[index + 1] - 1;
2080 // if ( ch == 14 )
2081 // c_hi = ZM_CH_G_14;
2082 // else
2083 // c_hi = ZM_CH_G_1 + (ch - 1) * 5;
2084 // }
2085 // else
2086 // {
2087 // /* calculate 5GHz low boundary channel frequency */
2088 // ch = countryInfo[index];
2089 // if ( (ch >= 184)&&(ch <= 196) )
2090 // c_lo = 4000 + ch*5;
2091 // else
2092 // c_lo = 5000 + ch*5;
2093 // /* calculate 5GHz high boundary channel frequency */
2094 // ch = countryInfo[index] + countryInfo[index + 1] - 1;
2095 // if ( (ch >= 184)&&(ch <= 196) )
2096 // c_hi = 4000 + ch*5;
2097 // else
2098 // c_hi = 5000 + ch*5;
2099 // }
2100 //
2101 // zfHpGetRegulationTable(dev, RegDomain, c_lo, c_hi);
2102 //
2103 // index+=3;
2104 //}
2105
2106 return 0;
2107 }
2108 }
2109 //zm_debug_msg_s("Invalid iso name = ", &countryInfo[2]);
2110 return 1;
2111 }
2112
2113 const char* zfHpGetisoNamefromregionCode(zdev_t* dev, u16_t regionCode)
2114 {
2115 u16_t i;
2116
2117 for (i = 0; i < N(allCountries); i++)
2118 {
2119 if (allCountries[i].regDmnEnum == regionCode)
2120 {
2121 return allCountries[i].isoName;
2122 }
2123 }
2124 /* no matching item, return default */
2125 return allCountries[0].isoName;
2126 }
2127
2128 u16_t zfHpGetRegionCodeFromIsoName(zdev_t* dev, u8_t *countryIsoName)
2129 {
2130 u16_t i;
2131 u16_t regionCode;
2132
2133 /* if no matching item, return default */
2134 regionCode = DEF_REGDMN;
2135
2136 for (i = 0; i < N(allCountries); i++)
2137 {
2138 if (zfMemoryIsEqual((u8_t *)allCountries[i].isoName, countryIsoName, 2))
2139 {
2140 regionCode = allCountries[i].regDmnEnum;
2141 break;
2142 }
2143 }
2144
2145 return regionCode;
2146 }
2147
2148 /************************************************************************/
2149 /* */
2150 /* FUNCTION DESCRIPTION zfHpDeleteAllowChannel */
2151 /* Delete Allow Channel. */
2152 /* */
2153 /* INPUTS */
2154 /* dev : device pointer */
2155 /* freq : frequency */
2156 /* */
2157 /* OUTPUTS */
2158 /* 0 : success */
2159 /* other : fail */
2160 /* */
2161 /* AUTHOR */
2162 /* Chao-Wen Yang ZyDAS Technology Corporation 2007.3 */
2163 /* */
2164 /************************************************************************/
2165 u16_t zfHpDeleteAllowChannel(zdev_t* dev, u16_t freq)
2166 {
2167 u16_t i, bandIndex = 0;
2168 u16_t dfs5GBand[][2] = {{5150, 5240}, {5260, 5350}, {5450, 5700}, {5725, 5825}};
2169
2170 zmw_get_wlan_dev(dev);
2171 /* Find which band does this frequency belong */
2172 for (i = 0; i < 4; i++)
2173 {
2174 if ((freq >= dfs5GBand[i][0]) && (freq <= dfs5GBand[i][1]))
2175 bandIndex = i + 1;
2176 }
2177
2178 if (bandIndex == 0)
2179 {
2180 /* 2.4G, don't care */
2181 return 0;
2182 }
2183 else
2184 {
2185 bandIndex--;
2186 }
2187 /* Set all channels in this band to passive scan */
2188 for (i = 0; i < wd->regulationTable.allowChannelCnt; i++)
2189 {
2190 if ((wd->regulationTable.allowChannel[i].channel >= dfs5GBand[bandIndex][0]) &&
2191 (wd->regulationTable.allowChannel[i].channel <= dfs5GBand[bandIndex][1]))
2192 {
2193 /* if channel is not passive, set it to be passive and mark it */
2194 if ((wd->regulationTable.allowChannel[i].channelFlags &
2195 ZM_REG_FLAG_CHANNEL_PASSIVE) == 0)
2196 {
2197 wd->regulationTable.allowChannel[i].channelFlags |=
2198 (ZM_REG_FLAG_CHANNEL_PASSIVE | ZM_REG_FLAG_CHANNEL_CSA);
2199 }
2200 }
2201 }
2202
2203 return 0;
2204 }
2205
2206 u16_t zfHpAddAllowChannel(zdev_t* dev, u16_t freq)
2207 {
2208 u16_t i, j, arrayIndex;
2209
2210 zmw_get_wlan_dev(dev);
2211
2212 for (i = 0; i < wd->regulationTable.allowChannelCnt; i++)
2213 {
2214 if (wd->regulationTable.allowChannel[i].channel == freq)
2215 break;
2216 }
2217
2218 if ( i == wd->regulationTable.allowChannelCnt)
2219 {
2220 for (j = 0; j < wd->regulationTable.allowChannelCnt; j++)
2221 {
2222 if (wd->regulationTable.allowChannel[j].channel > freq)
2223 break;
2224 }
2225
2226 //zm_debug_msg1("CWY - add frequency = ", freq);
2227 //zm_debug_msg1("CWY - channel array index = ", j);
2228
2229 arrayIndex = j;
2230
2231 if (arrayIndex < wd->regulationTable.allowChannelCnt)
2232 {
2233 for (j = wd->regulationTable.allowChannelCnt; j > arrayIndex; j--)
2234 wd->regulationTable.allowChannel[j] = wd->regulationTable.allowChannel[j - 1];
2235 }
2236 wd->regulationTable.allowChannel[arrayIndex].channel = freq;
2237
2238 wd->regulationTable.allowChannelCnt++;
2239 }
2240
2241 return 0;
2242 }
2243
2244 u16_t zfHpIsDfsChannelNCS(zdev_t* dev, u16_t freq)
2245 {
2246 u8_t flag = ZM_REG_FLAG_CHANNEL_DFS;
2247 u16_t i;
2248 zmw_get_wlan_dev(dev);
2249
2250 for (i = 0; i < wd->regulationTable.allowChannelCnt; i++)
2251 {
2252 //DbgPrint("DFS:freq=%d, chan=%d", freq, wd->regulationTable.allowChannel[i].channel);
2253 if (wd->regulationTable.allowChannel[i].channel == freq)
2254 {
2255 flag = wd->regulationTable.allowChannel[i].privFlags;
2256 break;
2257 }
2258 }
2259
2260 return (flag & (ZM_REG_FLAG_CHANNEL_DFS|ZM_REG_FLAG_CHANNEL_DFS_CLEAR));
2261 }
2262
2263 u16_t zfHpIsDfsChannel(zdev_t* dev, u16_t freq)
2264 {
2265 u8_t flag = ZM_REG_FLAG_CHANNEL_DFS;
2266 u16_t i;
2267 zmw_get_wlan_dev(dev);
2268
2269 zmw_declare_for_critical_section();
2270
2271 zmw_enter_critical_section(dev);
2272
2273 for (i = 0; i < wd->regulationTable.allowChannelCnt; i++)
2274 {
2275 //DbgPrint("DFS:freq=%d, chan=%d", freq, wd->regulationTable.allowChannel[i].channel);
2276 if (wd->regulationTable.allowChannel[i].channel == freq)
2277 {
2278 flag = wd->regulationTable.allowChannel[i].privFlags;
2279 break;
2280 }
2281 }
2282
2283 zmw_leave_critical_section(dev);
2284
2285 return (flag & (ZM_REG_FLAG_CHANNEL_DFS|ZM_REG_FLAG_CHANNEL_DFS_CLEAR));
2286 }
2287
2288 u16_t zfHpIsAllowedChannel(zdev_t* dev, u16_t freq)
2289 {
2290 u16_t i;
2291 zmw_get_wlan_dev(dev);
2292
2293 for (i = 0; i < wd->regulationTable.allowChannelCnt; i++)
2294 {
2295 if (wd->regulationTable.allowChannel[i].channel == freq)
2296 {
2297 return 1;
2298 }
2299 }
2300
2301 return 0;
2302 }
2303
2304 u16_t zfHpFindFirstNonDfsChannel(zdev_t* dev, u16_t aBand)
2305 {
2306 u16_t chan = 2412;
2307 u16_t i;
2308 zmw_get_wlan_dev(dev);
2309
2310 zmw_declare_for_critical_section();
2311
2312 zmw_enter_critical_section(dev);
2313
2314 for (i = 0; i < wd->regulationTable.allowChannelCnt; i++)
2315 {
2316 if ((wd->regulationTable.allowChannel[i].privFlags & ZM_REG_FLAG_CHANNEL_DFS) != 0)
2317 {
2318 if (aBand)
2319 {
2320 if (wd->regulationTable.allowChannel[i].channel > 3000)
2321 {
2322 chan = wd->regulationTable.allowChannel[i].channel;
2323 break;
2324 }
2325 }
2326 else
2327 {
2328 if (wd->regulationTable.allowChannel[i].channel < 3000)
2329 {
2330 chan = wd->regulationTable.allowChannel[i].channel;
2331 break;
2332 }
2333 }
2334 }
2335 }
2336
2337 zmw_leave_critical_section(dev);
2338
2339 return chan;
2340 }
2341
2342
2343 /* porting from ACU */
2344 /* save RegulatoryDomain in hpriv */
2345 u8_t zfHpGetRegulatoryDomain(zdev_t* dev)
2346 {
2347 zmw_get_wlan_dev(dev);
2348
2349 switch (wd->regulationTable.regionCode)
2350 {
2351 case NO_ENUMRD:
2352 return 0;
2353 break;
2354 case FCC1_FCCA:
2355 case FCC1_WORLD:
2356 case FCC4_FCCA:
2357 case FCC5_FCCA:
2358 case FCC2_WORLD:
2359 case FCC2_ETSIC:
2360 case FCC3_FCCA:
2361 case FCC3_WORLD:
2362 case FCC1:
2363 case FCC2:
2364 case FCC3:
2365 case FCC4:
2366 case FCC5:
2367 case FCCA:
2368 return 0x10;//WG_AMERICAS DOT11_REG_DOMAIN_FCC United States
2369 break;
2370
2371 case FCC2_FCCA:
2372 return 0x20;//DOT11_REG_DOMAIN_DOC Canada
2373 break;
2374
2375 case ETSI1_WORLD:
2376 case ETSI3_ETSIA:
2377 case ETSI2_WORLD:
2378 case ETSI3_WORLD:
2379 case ETSI4_WORLD:
2380 case ETSI4_ETSIC:
2381 case ETSI5_WORLD:
2382 case ETSI6_WORLD:
2383 case ETSI_RESERVED:
2384 case ETSI1:
2385 case ETSI2:
2386 case ETSI3:
2387 case ETSI4:
2388 case ETSI5:
2389 case ETSI6:
2390 case ETSIA:
2391 case ETSIB:
2392 case ETSIC:
2393 return 0x30;//WG_EMEA DOT11_REG_DOMAIN_ETSI Most of Europe
2394 break;
2395
2396 case MKK1_MKKA:
2397 case MKK1_MKKB:
2398 case MKK2_MKKA:
2399 case MKK1_FCCA:
2400 case MKK1_MKKA1:
2401 case MKK1_MKKA2:
2402 case MKK1_MKKC:
2403 case MKK3_MKKB:
2404 case MKK3_MKKA2:
2405 case MKK3_MKKC:
2406 case MKK4_MKKB:
2407 case MKK4_MKKA2:
2408 case MKK4_MKKC:
2409 case MKK5_MKKB:
2410 case MKK5_MKKA2:
2411 case MKK5_MKKC:
2412 case MKK6_MKKB:
2413 case MKK6_MKKA2:
2414 case MKK6_MKKC:
2415 case MKK7_MKKB:
2416 case MKK7_MKKA:
2417 case MKK7_MKKC:
2418 case MKK8_MKKB:
2419 case MKK8_MKKA2:
2420 case MKK8_MKKC:
2421 case MKK6_MKKA1:
2422 case MKK6_FCCA:
2423 case MKK7_MKKA1:
2424 case MKK7_FCCA:
2425 case MKK9_FCCA:
2426 case MKK9_MKKA1:
2427 case MKK9_MKKC:
2428 case MKK9_MKKA2:
2429 case MKK10_FCCA:
2430 case MKK10_MKKA1:
2431 case MKK10_MKKC:
2432 case MKK10_MKKA2:
2433 case MKK11_MKKA:
2434 case MKK11_FCCA:
2435 case MKK11_MKKA1:
2436 case MKK11_MKKC:
2437 case MKK11_MKKA2:
2438 case MKK12_MKKA:
2439 case MKK12_FCCA:
2440 case MKK12_MKKA1:
2441 case MKK12_MKKC:
2442 case MKK12_MKKA2:
2443 case MKK3_MKKA:
2444 case MKK3_MKKA1:
2445 case MKK3_FCCA:
2446 case MKK4_MKKA:
2447 case MKK4_MKKA1:
2448 case MKK4_FCCA:
2449 case MKK9_MKKA:
2450 case MKK10_MKKA:
2451 case MKK1:
2452 case MKK2:
2453 case MKK3:
2454 case MKK4:
2455 case MKK5:
2456 case MKK6:
2457 case MKK7:
2458 case MKK8:
2459 case MKK9:
2460 case MKK10:
2461 case MKK11:
2462 case MKK12:
2463 case MKKA:
2464 case MKKC:
2465 return 0x40;//WG_JAPAN DOT11_REG_DOMAIN_MKK Japan
2466 break;
2467
2468 default:
2469 break;
2470 }
2471 return 0xFF;// Didn't input RegDmn by mean to distinguish by customer
2472
2473 }
2474
2475
2476 void zfHpDisableDfsChannel(zdev_t* dev, u8_t disableFlag)
2477 {
2478 struct zsHpPriv* hpPriv;
2479
2480 zmw_get_wlan_dev(dev);
2481 hpPriv=wd->hpPrivate;
2482 hpPriv->disableDfsCh = disableFlag;
2483 return;
2484 }
Linux for Ginger Game Console