drivers/staging/rtl8192e/r819xE_phy.h

   1 #ifndef _R819XU_PHY_H
   2 #define _R819XU_PHY_H
   3 /* Channel switch:The size of command tables for switch channel*/
   4 #define MAX_PRECMD_CNT 16
   5 #define MAX_RFDEPENDCMD_CNT 16
   6 #define MAX_POSTCMD_CNT 16
   7
   8 #ifdef RTL8190P
   9 #define MACPHY_Array_PGLength 21
  10 #define Rtl819XMACPHY_Array_PG                  Rtl8190PciMACPHY_Array_PG
  11 #define Rtl819XMACPHY_Array                             Rtl8190PciMACPHY_Array
  12 #define RadioC_ArrayLength 246
  13 #define RadioD_ArrayLength 78
  14 #define Rtl819XRadioA_Array                                     Rtl8190PciRadioA_Array
  15 #define Rtl819XRadioB_Array                                     Rtl8190PciRadioB_Array
  16 #define Rtl819XRadioC_Array                                     Rtl8190PciRadioC_Array
  17 #define Rtl819XRadioD_Array                                     Rtl8190PciRadioD_Array
  18 #define Rtl819XAGCTAB_Array                             Rtl8190PciAGCTAB_Array
  19 #define PHY_REGArrayLength                              280
  20 #define Rtl819XPHY_REGArray                             Rtl8190PciPHY_REGArray
  21 #define PHY_REG_1T2RArrayLength                 280
  22 #define Rtl819XPHY_REG_1T2RArray                Rtl8190PciPHY_REG_1T2RArray
  23 #endif
  24
  25         #ifdef RTL8192E
  26         #define MACPHY_Array_PGLength 30
  27         #define Rtl819XMACPHY_Array_PG                  Rtl8192PciEMACPHY_Array_PG
  28         #define Rtl819XMACPHY_Array                             Rtl8192PciEMACPHY_Array
  29         #define RadioC_ArrayLength 1
  30         #define RadioD_ArrayLength 1
  31         #define Rtl819XRadioA_Array                                     Rtl8192PciERadioA_Array
  32         #define Rtl819XRadioB_Array                                     Rtl8192PciERadioB_Array
  33         #define Rtl819XRadioC_Array                                     Rtl8192PciERadioC_Array
  34         #define Rtl819XRadioD_Array                                     Rtl8192PciERadioD_Array
  35         #define Rtl819XAGCTAB_Array                             Rtl8192PciEAGCTAB_Array
  36         #define PHY_REGArrayLength                              1
  37         #define Rtl819XPHY_REGArray                             Rtl8192PciEPHY_REGArray
  38         #define PHY_REG_1T2RArrayLength                 296
  39         #define Rtl819XPHY_REG_1T2RArray                Rtl8192PciEPHY_REG_1T2RArray
  40         #endif
  41 #define AGCTAB_ArrayLength 384
  42 #define MACPHY_ArrayLength 18
  43
  44 #define RadioA_ArrayLength 246
  45 #define RadioB_ArrayLength 78
  46
  47
  48 typedef enum _SwChnlCmdID{
  49         CmdID_End,
  50         CmdID_SetTxPowerLevel,
  51         CmdID_BBRegWrite10,
  52         CmdID_WritePortUlong,
  53         CmdID_WritePortUshort,
  54         CmdID_WritePortUchar,
  55         CmdID_RF_WriteReg,
  56 }SwChnlCmdID;
  57
  58 /*--------------------------------Define structure--------------------------------*/
  59 /* 1. Switch channel related */
  60 typedef struct _SwChnlCmd{
  61         SwChnlCmdID     CmdID;
  62         u32                     Para1;
  63         u32                     Para2;
  64         u32                     msDelay;
  65 }__attribute__ ((packed)) SwChnlCmd;
  66
  67 extern u32 rtl819XMACPHY_Array_PG[];
  68 extern u32 rtl819XPHY_REG_1T2RArray[];
  69 extern u32 rtl819XAGCTAB_Array[];
  70 extern u32 rtl819XRadioA_Array[];
  71 extern u32 rtl819XRadioB_Array[];
  72 extern u32 rtl819XRadioC_Array[];
  73 extern u32 rtl819XRadioD_Array[];
  74
  75 typedef enum _HW90_BLOCK{
  76         HW90_BLOCK_MAC = 0,
  77         HW90_BLOCK_PHY0 = 1,
  78         HW90_BLOCK_PHY1 = 2,
  79         HW90_BLOCK_RF = 3,
  80         HW90_BLOCK_MAXIMUM = 4, // Never use this
  81 }HW90_BLOCK_E, *PHW90_BLOCK_E;
  82
  83 typedef enum _RF90_RADIO_PATH{
  84         RF90_PATH_A = 0,                        //Radio Path A
  85         RF90_PATH_B = 1,                        //Radio Path B
  86         RF90_PATH_C = 2,                        //Radio Path C
  87         RF90_PATH_D = 3,                        //Radio Path D
  88         RF90_PATH_MAX                           //Max RF number 92 support
  89 }RF90_RADIO_PATH_E, *PRF90_RADIO_PATH_E;
  90
  91 #define bMaskByte0                0xff
  92 #define bMaskByte1                0xff00
  93 #define bMaskByte2                0xff0000
  94 #define bMaskByte3                0xff000000
  95 #define bMaskHWord                0xffff0000
  96 #define bMaskLWord                0x0000ffff
  97 #define bMaskDWord                0xffffffff
  98
  99 //extern u32 rtl8192_CalculateBitShift(u32 dwBitMask);
 100 extern u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath);
 101 extern void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData);
 102 extern u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask);
 103 //extern u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset);
 104 //extern void rtl8192_phy_RFSerialWrite(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data);
 105 extern void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
 106 extern u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask);
 107 extern void rtl8192_phy_configmac(struct net_device* dev);
 108 extern void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType);
 109 //extern void rtl8192_InitBBRFRegDef(struct net_device* dev);
 110 extern RT_STATUS rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath);
 111 //extern RT_STATUS rtl8192_BB_Config_ParaFile(struct net_device* dev);
 112 extern RT_STATUS rtl8192_BBConfig(struct net_device* dev);
 113 extern void rtl8192_phy_getTxPower(struct net_device* dev);
 114 extern void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel);
 115 extern RT_STATUS rtl8192_phy_RFConfig(struct net_device* dev);
 116 extern void rtl8192_phy_updateInitGain(struct net_device* dev);
 117 extern u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E  eRFPath);
 118
 119 extern u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel);
 120 extern void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH  Bandwidth, HT_EXTCHNL_OFFSET Offset);
 121 extern void rtl8192_SwChnl_WorkItem(struct net_device *dev);
 122 extern void rtl8192_SetBWModeWorkItem(struct net_device *dev);
 123 extern void InitialGain819xPci(struct net_device *dev, u8 Operation);
 124
 125 #endif